[u-boot.git] / cpu / arm926ejs / at91 / at91sam9261_devices.c

/*
 * (C) Copyright 2007-2008
 * Stelian Pop <[email protected]>
 * Lead Tech Design <www.leadtechdesign.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/io.h>

void at91_serial0_hw_init(void)
{
	at91_set_a_periph(AT91_PIO_PORTC, 8, 1);		/* TXD0 */
	at91_set_a_periph(AT91_PIO_PORTC, 9, 0);		/* RXD0 */
	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US0);
}

void at91_serial1_hw_init(void)
{
	at91_set_a_periph(AT91_PIO_PORTC, 12, 1);		/* TXD1 */
	at91_set_a_periph(AT91_PIO_PORTC, 13, 0);		/* RXD1 */
	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US1);
}

void at91_serial2_hw_init(void)
{
	at91_set_a_periph(AT91_PIO_PORTC, 14, 1);		/* TXD2 */
	at91_set_a_periph(AT91_PIO_PORTC, 15, 0);		/* RXD2 */
	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US2);
}

void at91_serial3_hw_init(void)
{
	at91_set_a_periph(AT91_PIO_PORTA, 9, 0);		/* DRXD */
	at91_set_a_periph(AT91_PIO_PORTA, 10, 1);		/* DTXD */
	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
}

void at91_serial_hw_init(void)
{
#ifdef CONFIG_USART0
	at91_serial0_hw_init();
#endif

#ifdef CONFIG_USART1
	at91_serial1_hw_init();
#endif

#ifdef CONFIG_USART2
	at91_serial2_hw_init();
#endif

#ifdef CONFIG_USART3	/* DBGU */
	at91_serial3_hw_init();
#endif
}

#ifdef CONFIG_HAS_DATAFLASH
void at91_spi0_hw_init(unsigned long cs_mask)
{
	at91_set_a_periph(AT91_PIO_PORTA, 0, 0);	/* SPI0_MISO */
	at91_set_a_periph(AT91_PIO_PORTA, 1, 0);	/* SPI0_MOSI */
	at91_set_a_periph(AT91_PIO_PORTA, 2, 0);	/* SPI0_SPCK */

	/* Enable clock */
	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_SPI0);

	if (cs_mask & (1 << 0)) {
		at91_set_a_periph(AT91_PIO_PORTA, 3, 1);
	}
	if (cs_mask & (1 << 1)) {
		at91_set_a_periph(AT91_PIO_PORTA, 4, 1);
	}
	if (cs_mask & (1 << 2)) {
		at91_set_a_periph(AT91_PIO_PORTA, 5, 1);
	}
	if (cs_mask & (1 << 3)) {
		at91_set_a_periph(AT91_PIO_PORTA, 6, 1);
	}
	if (cs_mask & (1 << 4)) {
		at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
	}
	if (cs_mask & (1 << 5)) {
		at91_set_pio_output(AT91_PIO_PORTA, 4, 1);
	}
	if (cs_mask & (1 << 6)) {
		at91_set_pio_output(AT91_PIO_PORTA, 5, 1);
	}
	if (cs_mask & (1 << 7)) {
		at91_set_pio_output(AT91_PIO_PORTA, 6, 1);
	}
}

void at91_spi1_hw_init(unsigned long cs_mask)
{
	at91_set_a_periph(AT91_PIO_PORTB, 30, 0);	/* SPI1_MISO */
	at91_set_a_periph(AT91_PIO_PORTB, 31, 0);	/* SPI1_MOSI */
	at91_set_a_periph(AT91_PIO_PORTB, 29, 0);	/* SPI1_SPCK */

	/* Enable clock */
	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_SPI1);

	if (cs_mask & (1 << 0)) {
		at91_set_a_periph(AT91_PIO_PORTB, 28, 1);
	}
	if (cs_mask & (1 << 1)) {
		at91_set_b_periph(AT91_PIO_PORTA, 24, 1);
	}
	if (cs_mask & (1 << 2)) {
		at91_set_b_periph(AT91_PIO_PORTA, 25, 1);
	}
	if (cs_mask & (1 << 3)) {
		at91_set_a_periph(AT91_PIO_PORTA, 26, 1);
	}
	if (cs_mask & (1 << 4)) {
		at91_set_pio_output(AT91_PIO_PORTB, 28, 1);
	}
	if (cs_mask & (1 << 5)) {
		at91_set_pio_output(AT91_PIO_PORTA, 24, 1);
	}
	if (cs_mask & (1 << 6)) {
		at91_set_pio_output(AT91_PIO_PORTA, 25, 1);
	}
	if (cs_mask & (1 << 7)) {
		at91_set_pio_output(AT91_PIO_PORTA, 26, 1);
	}
}
#endif
Commit	Line	Data
7ebafb7e JCPV	1	/*
	2	* (C) Copyright 2007-2008
	3	* Stelian Pop <[email protected]>
	4	* Lead Tech Design <www.leadtechdesign.com>
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	#include <common.h>
	26	#include <asm/arch/at91_common.h>
	27	#include <asm/arch/at91_pmc.h>
	28	#include <asm/arch/gpio.h>
	29	#include <asm/arch/io.h>
	30
1699da62 JCPV	31	void at91_serial0_hw_init(void)
1699da62 JCPV	32	{
7f9e8633 JS	33	at91_set_a_periph(AT91_PIO_PORTC, 8, 1); /* TXD0 */
7f9e8633 JS	34	at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* RXD0 */
1699da62 JCPV	35	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US0);
	36	}
	37
	38	void at91_serial1_hw_init(void)
	39	{
7f9e8633 JS	40	at91_set_a_periph(AT91_PIO_PORTC, 12, 1); /* TXD1 */
7f9e8633 JS	41	at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RXD1 */
1699da62 JCPV	42	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US1);
	43	}
	44
	45	void at91_serial2_hw_init(void)
	46	{
7f9e8633 JS	47	at91_set_a_periph(AT91_PIO_PORTC, 14, 1); /* TXD2 */
7f9e8633 JS	48	at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* RXD2 */
1699da62 JCPV	49	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US2);
	50	}
	51
	52	void at91_serial3_hw_init(void)
	53	{
7f9e8633 JS	54	at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */
7f9e8633 JS	55	at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */
1699da62 JCPV	56	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
	57	}
	58
	59	void at91_serial_hw_init(void)
	60	{
	61	#ifdef CONFIG_USART0
	62	at91_serial0_hw_init();
	63	#endif
	64
	65	#ifdef CONFIG_USART1
	66	at91_serial1_hw_init();
	67	#endif
	68
	69	#ifdef CONFIG_USART2
	70	at91_serial2_hw_init();
	71	#endif
	72
	73	#ifdef CONFIG_USART3 /* DBGU */
	74	at91_serial3_hw_init();
	75	#endif
	76	}
	77
	78	#ifdef CONFIG_HAS_DATAFLASH
7ebafb7e JCPV	79	void at91_spi0_hw_init(unsigned long cs_mask)
7ebafb7e JCPV	80	{
7f9e8633 JS	81	at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* SPI0_MISO */
	82	at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* SPI0_MOSI */
	83	at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* SPI0_SPCK */
7ebafb7e JCPV	84
	85	/* Enable clock */
	86	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_SPI0);
	87
	88	if (cs_mask & (1 << 0)) {
7f9e8633	89	at91_set_a_periph(AT91_PIO_PORTA, 3, 1);
7ebafb7e JCPV	90	}
7ebafb7e JCPV	91	if (cs_mask & (1 << 1)) {
7f9e8633	92	at91_set_a_periph(AT91_PIO_PORTA, 4, 1);
7ebafb7e JCPV	93	}
7ebafb7e JCPV	94	if (cs_mask & (1 << 2)) {
7f9e8633	95	at91_set_a_periph(AT91_PIO_PORTA, 5, 1);
7ebafb7e JCPV	96	}
7ebafb7e JCPV	97	if (cs_mask & (1 << 3)) {
7f9e8633	98	at91_set_a_periph(AT91_PIO_PORTA, 6, 1);
a47492ac JCPV	99	}
a47492ac JCPV	100	if (cs_mask & (1 << 4)) {
7f9e8633	101	at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
a47492ac JCPV	102	}
a47492ac JCPV	103	if (cs_mask & (1 << 5)) {
7f9e8633	104	at91_set_pio_output(AT91_PIO_PORTA, 4, 1);
a47492ac JCPV	105	}
a47492ac JCPV	106	if (cs_mask & (1 << 6)) {
7f9e8633	107	at91_set_pio_output(AT91_PIO_PORTA, 5, 1);
a47492ac JCPV	108	}
a47492ac JCPV	109	if (cs_mask & (1 << 7)) {
7f9e8633	110	at91_set_pio_output(AT91_PIO_PORTA, 6, 1);
7ebafb7e JCPV	111	}
	112	}
	113
	114	void at91_spi1_hw_init(unsigned long cs_mask)
	115	{
7f9e8633 JS	116	at91_set_a_periph(AT91_PIO_PORTB, 30, 0); /* SPI1_MISO */
	117	at91_set_a_periph(AT91_PIO_PORTB, 31, 0); /* SPI1_MOSI */
	118	at91_set_a_periph(AT91_PIO_PORTB, 29, 0); /* SPI1_SPCK */
7ebafb7e JCPV	119
	120	/* Enable clock */
	121	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_SPI1);
	122
	123	if (cs_mask & (1 << 0)) {
7f9e8633	124	at91_set_a_periph(AT91_PIO_PORTB, 28, 1);
7ebafb7e JCPV	125	}
7ebafb7e JCPV	126	if (cs_mask & (1 << 1)) {
7f9e8633	127	at91_set_b_periph(AT91_PIO_PORTA, 24, 1);
7ebafb7e JCPV	128	}
7ebafb7e JCPV	129	if (cs_mask & (1 << 2)) {
7f9e8633	130	at91_set_b_periph(AT91_PIO_PORTA, 25, 1);
7ebafb7e JCPV	131	}
7ebafb7e JCPV	132	if (cs_mask & (1 << 3)) {
7f9e8633	133	at91_set_a_periph(AT91_PIO_PORTA, 26, 1);
a47492ac JCPV	134	}
a47492ac JCPV	135	if (cs_mask & (1 << 4)) {
7f9e8633	136	at91_set_pio_output(AT91_PIO_PORTB, 28, 1);
a47492ac JCPV	137	}
a47492ac JCPV	138	if (cs_mask & (1 << 5)) {
7f9e8633	139	at91_set_pio_output(AT91_PIO_PORTA, 24, 1);
a47492ac JCPV	140	}
a47492ac JCPV	141	if (cs_mask & (1 << 6)) {
7f9e8633	142	at91_set_pio_output(AT91_PIO_PORTA, 25, 1);
a47492ac JCPV	143	}
a47492ac JCPV	144	if (cs_mask & (1 << 7)) {
7f9e8633	145	at91_set_pio_output(AT91_PIO_PORTA, 26, 1);
7ebafb7e JCPV	146	}
7ebafb7e JCPV	147	}
1699da62	148	#endif