[u-boot.git] / include / configs / m53menlo.h

/* SPDX-License-Identifier: GPL-2.0+ */

/*
 * Menlosystems M53Menlo configuration
 * Copyright (C) 2012-2017 Marek Vasut <[email protected]>
 * Copyright (C) 2014-2017 Olaf Mandel <[email protected]>
 */

#ifndef __M53MENLO_CONFIG_H__
#define __M53MENLO_CONFIG_H__

#include <asm/arch/imx-regs.h>

#define CONFIG_REVISION_TAG
#define CONFIG_SYS_FSL_CLK

#define CONFIG_TIMESTAMP		/* Print image info with timestamp */

/*
 * Memory configurations
 */
#define PHYS_SDRAM_1			CSD0_BASE_ADDR
#define PHYS_SDRAM_1_SIZE		(gd->bd->bi_dram[0].size)
#define PHYS_SDRAM_2			CSD1_BASE_ADDR
#define PHYS_SDRAM_2_SIZE		(gd->bd->bi_dram[1].size)
#define PHYS_SDRAM_SIZE			(gd->ram_size)

#define CONFIG_SYS_SDRAM_BASE		(PHYS_SDRAM_1)
#define CONFIG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR)
#define CONFIG_SYS_INIT_RAM_SIZE	(IRAM_SIZE)

#define CONFIG_SYS_INIT_SP_OFFSET \
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

/*
 * U-Boot general configurations
 */
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O buffer size */
#define CONFIG_SYS_MAXARGS	32		/* Max number of command args */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
						/* Boot argument buffer size */

/*
 * Serial Driver
 */
#define CONFIG_MXC_UART_BASE		UART1_BASE

/*
 * MMC Driver
 */
#ifdef CONFIG_CMD_MMC
#define CONFIG_SYS_FSL_ESDHC_ADDR	0
#define CONFIG_SYS_FSL_ESDHC_NUM	1
#endif

/*
 * NAND
 */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_SYS_NAND_BASE		NFC_BASE_ADDR_AXI
#define CONFIG_MXC_NAND_REGS_BASE	NFC_BASE_ADDR_AXI
#define CONFIG_MXC_NAND_IP_REGS_BASE	NFC_BASE_ADDR
#define CONFIG_SYS_NAND_LARGEPAGE
#define CONFIG_MXC_NAND_HWECC

/* Environment is in NAND */
#define CONFIG_ENV_RANGE		(0x00080000) /* 512 KiB */
#endif

/*
 * Ethernet on SOC (FEC)
 */
#ifdef CONFIG_CMD_NET
#define CONFIG_FEC_MXC
#define IMX_FEC_BASE			FEC_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR		0x0
#define CONFIG_MII
#define CONFIG_DISCOVER_PHY
#define CONFIG_FEC_XCV_TYPE		RMII
#define CONFIG_ETHPRIME			"FEC0"
#endif

#define CONFIG_SYS_RTC_BUS_NUM		1 /* I2C2 */

/*
 * RTC
 */
#ifdef CONFIG_CMD_DATE
#define CONFIG_SYS_I2C_RTC_ADDR		0x68
#define CONFIG_SYS_M41T11_BASE_YEAR	2000
#endif

/*
 * USB
 */
#ifdef CONFIG_CMD_USB
#define CONFIG_MXC_USB_PORT		1
#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS		0
#endif

/*
 * SATA
 */
#ifdef CONFIG_CMD_SATA
#define CONFIG_SYS_SATA_MAX_DEVICE	1
#define CONFIG_DWC_AHSATA_PORT_ID	0
#define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_BASE_ADDR
#define CONFIG_LBA48
#endif

/*
 * LCD
 */
#define CONFIG_VIDEO_LOGO
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE	(2 << 20)

/* LVDS display */
#define CONFIG_SYS_LDB_CLOCK			33260000
#define CONFIG_IMX_VIDEO_SKIP

/* IIM Fuses */
#define CONFIG_FSL_IIM

/* Watchdog */

/*
 * Boot Linux
 */
#define CONFIG_CMDLINE_TAG
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_BOOTFILE		"boot/fitImage"
#define CONFIG_BOOTCOMMAND	"run mmc_mmc"

/*
 * NAND SPL
 */
#define CONFIG_SPL_TARGET		"u-boot-with-nand-spl.imx"
#define CONFIG_SPL_PAD_TO		0x8000
#define CONFIG_SPL_STACK		0x70004000

#define CONFIG_SYS_NAND_U_BOOT_OFFS	CONFIG_SPL_PAD_TO
#define CONFIG_SYS_NAND_PAGE_SIZE	2048
#define CONFIG_SYS_NAND_OOBSIZE		64
#define CONFIG_SYS_NAND_PAGE_COUNT	64
#define CONFIG_SYS_NAND_SIZE		(256 * 1024 * 1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0

/*
 * Extra Environments
 */
#define CONFIG_HOSTNAME		"m53menlo"

#define CONFIG_EXTRA_ENV_SETTINGS					\
	"consdev=ttymxc0\0"						\
	"baudrate=115200\0"						\
	"bootscript=boot.scr\0"						\
	"mmcdev=0\0"							\
	"mmcpart=1\0"							\
	"rootpath=/srv/\0"						\
	"kernel_addr_r=0x72000000\0"					\
	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0"				\
	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"			\
	"netdev=eth0\0"							\
	"splashsource=mmc_fs\0"						\
	"splashfile=boot/usplash.bmp.gz\0"				\
	"splashimage=0x88000000\0"					\
	"splashpos=m,m\0"						\
	"stdout=serial,vidconsole\0"					\
	"stderr=serial,vidconsole\0"					\
	"addcons="							\
		"setenv bootargs ${bootargs} "				\
		"console=${consdev},${baudrate}\0"			\
	"addip="							\
		"setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off\0"				\
	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
	"addmisc="							\
		"setenv bootargs ${bootargs} ${miscargs}\0"		\
	"addargs=run addcons addmisc addmtd\0"				\
	"mmcload="							\
		"mmc rescan ; load mmc ${mmcdev}:${mmcpart} "		\
		"${kernel_addr_r} ${bootfile}\0"			\
	"miscargs=nohlt panic=1\0"					\
	"mmcargs=setenv bootargs root=/dev/mmcblk0p${mmcpart} rw "	\
		"rootwait\0"						\
	"mmc_mmc="							\
		"run mmcload mmcargs addargs ; "			\
		"bootm ${kernel_addr_r}\0"				\
	"netload=tftp ${kernel_addr_r} ${hostname}/${bootfile}\0"	\
	"net_nfs="							\
		"run netload nfsargs addip addargs ; "			\
		"bootm ${kernel_addr_r}\0"				\
	"nfsargs="							\
		"setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}${hostname},v3,tcp\0"	\
	"try_bootscript="						\
		"mmc rescan;"						\
		"if test -e mmc 0:1 ${bootscript} ; then "		\
		"if load mmc 0:1 ${kernel_addr_r} ${bootscript};"	\
		"then ; "						\
			"echo Running bootscript... ; "			\
			"source ${kernel_addr_r} ; "			\
		"fi ; "							\
		"fi\0"

#if defined(CONFIG_SPL_BUILD)
#undef CONFIG_WATCHDOG
#define CONFIG_HW_WATCHDOG
#endif

#endif	/* __M53MENLO_CONFIG_H__ */
Commit	Line	Data
39cb4f3c MV	1	/* SPDX-License-Identifier: GPL-2.0+ */
	2
	3	/*
	4	* Menlosystems M53Menlo configuration
	5	* Copyright (C) 2012-2017 Marek Vasut <[email protected]>
	6	* Copyright (C) 2014-2017 Olaf Mandel <[email protected]>
	7	*/
	8
	9	#ifndef __M53MENLO_CONFIG_H__
	10	#define __M53MENLO_CONFIG_H__
	11
	12	#include <asm/arch/imx-regs.h>
	13
	14	#define CONFIG_REVISION_TAG
	15	#define CONFIG_SYS_FSL_CLK
	16
	17	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
	18
	19	/*
	20	* Memory configurations
	21	*/
	22	#define PHYS_SDRAM_1 CSD0_BASE_ADDR
	23	#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size)
	24	#define PHYS_SDRAM_2 CSD1_BASE_ADDR
	25	#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size)
	26	#define PHYS_SDRAM_SIZE (gd->ram_size)
39cb4f3c MV	27
	28	#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
	29	#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
	30	#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
	31
	32	#define CONFIG_SYS_INIT_SP_OFFSET \
	33	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	34	#define CONFIG_SYS_INIT_SP_ADDR \
	35	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
	36
	37	/*
	38	* U-Boot general configurations
	39	*/
	40	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
	41	#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
	42	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	43	/* Boot argument buffer size */
	44
	45	/*
	46	* Serial Driver
	47	*/
39cb4f3c MV	48	#define CONFIG_MXC_UART_BASE UART1_BASE
	49
	50	/*
	51	* MMC Driver
	52	*/
	53	#ifdef CONFIG_CMD_MMC
	54	#define CONFIG_SYS_FSL_ESDHC_ADDR 0
	55	#define CONFIG_SYS_FSL_ESDHC_NUM 1
	56	#endif
	57
	58	/*
	59	* NAND
	60	*/
39cb4f3c MV	61	#ifdef CONFIG_CMD_NAND
	62	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	63	#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR_AXI
	64	#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI
	65	#define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR
	66	#define CONFIG_SYS_NAND_LARGEPAGE
	67	#define CONFIG_MXC_NAND_HWECC
39cb4f3c MV	68
39cb4f3c MV	69	/* Environment is in NAND */
a09fea1d	70	#define CONFIG_ENV_RANGE (0x00080000) /* 512 KiB */
39cb4f3c MV	71	#endif
	72
	73	/*
	74	* Ethernet on SOC (FEC)
	75	*/
	76	#ifdef CONFIG_CMD_NET
	77	#define CONFIG_FEC_MXC
	78	#define IMX_FEC_BASE FEC_BASE_ADDR
	79	#define CONFIG_FEC_MXC_PHYADDR 0x0
	80	#define CONFIG_MII
	81	#define CONFIG_DISCOVER_PHY
	82	#define CONFIG_FEC_XCV_TYPE RMII
	83	#define CONFIG_ETHPRIME "FEC0"
	84	#endif
	85
39cb4f3c	86	#define CONFIG_SYS_RTC_BUS_NUM 1 /* I2C2 */
39cb4f3c MV	87
	88	/*
	89	* RTC
	90	*/
	91	#ifdef CONFIG_CMD_DATE
39cb4f3c MV	92	#define CONFIG_SYS_I2C_RTC_ADDR 0x68
	93	#define CONFIG_SYS_M41T11_BASE_YEAR 2000
	94	#endif
	95
	96	/*
	97	* USB
	98	*/
	99	#ifdef CONFIG_CMD_USB
39cb4f3c MV	100	#define CONFIG_MXC_USB_PORT 1
	101	#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI \| PORT_PTS_PTW)
	102	#define CONFIG_MXC_USB_FLAGS 0
	103	#endif
	104
	105	/*
	106	* SATA
	107	*/
	108	#ifdef CONFIG_CMD_SATA
	109	#define CONFIG_SYS_SATA_MAX_DEVICE 1
	110	#define CONFIG_DWC_AHSATA_PORT_ID 0
	111	#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR
	112	#define CONFIG_LBA48
	113	#endif
	114
	115	/*
	116	* LCD
	117	*/
39cb4f3c MV	118	#define CONFIG_VIDEO_LOGO
39cb4f3c MV	119	#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
39cb4f3c MV	120
	121	/* LVDS display */
	122	#define CONFIG_SYS_LDB_CLOCK 33260000
	123	#define CONFIG_IMX_VIDEO_SKIP
39cb4f3c MV	124
	125	/* IIM Fuses */
	126	#define CONFIG_FSL_IIM
	127
bf413781	128	/* Watchdog */
bf413781	129
39cb4f3c MV	130	/*
	131	* Boot Linux
	132	*/
	133	#define CONFIG_CMDLINE_TAG
	134	#define CONFIG_INITRD_TAG
	135	#define CONFIG_REVISION_TAG
	136	#define CONFIG_SETUP_MEMORY_TAGS
	137	#define CONFIG_BOOTFILE "boot/fitImage"
39cb4f3c	138	#define CONFIG_BOOTCOMMAND "run mmc_mmc"
39cb4f3c MV	139
	140	/*
	141	* NAND SPL
	142	*/
	143	#define CONFIG_SPL_TARGET "u-boot-with-nand-spl.imx"
39cb4f3c MV	144	#define CONFIG_SPL_PAD_TO 0x8000
	145	#define CONFIG_SPL_STACK 0x70004000
	146
	147	#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
	148	#define CONFIG_SYS_NAND_PAGE_SIZE 2048
	149	#define CONFIG_SYS_NAND_OOBSIZE 64
	150	#define CONFIG_SYS_NAND_PAGE_COUNT 64
	151	#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
	152	#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
	153
	154	/*
	155	* Extra Environments
	156	*/
39cb4f3c MV	157	#define CONFIG_HOSTNAME "m53menlo"
	158
	159	#define CONFIG_EXTRA_ENV_SETTINGS \
	160	"consdev=ttymxc0\0" \
	161	"baudrate=115200\0" \
	162	"bootscript=boot.scr\0" \
	163	"mmcdev=0\0" \
	164	"mmcpart=1\0" \
	165	"rootpath=/srv/\0" \
	166	"kernel_addr_r=0x72000000\0" \
	167	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
	168	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
	169	"netdev=eth0\0" \
	170	"splashsource=mmc_fs\0" \
de5def1c	171	"splashfile=boot/usplash.bmp.gz\0" \
39cb4f3c MV	172	"splashimage=0x88000000\0" \
39cb4f3c MV	173	"splashpos=m,m\0" \
f0be8ff4 MV	174	"stdout=serial,vidconsole\0" \
f0be8ff4 MV	175	"stderr=serial,vidconsole\0" \
39cb4f3c MV	176	"addcons=" \
	177	"setenv bootargs ${bootargs} " \
	178	"console=${consdev},${baudrate}\0" \
	179	"addip=" \
	180	"setenv bootargs ${bootargs} " \
	181	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	182	":${hostname}:${netdev}:off\0" \
88b5002b	183	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
39cb4f3c MV	184	"addmisc=" \
	185	"setenv bootargs ${bootargs} ${miscargs}\0" \
	186	"addargs=run addcons addmisc addmtd\0" \
	187	"mmcload=" \
	188	"mmc rescan ; load mmc ${mmcdev}:${mmcpart} " \
	189	"${kernel_addr_r} ${bootfile}\0" \
	190	"miscargs=nohlt panic=1\0" \
	191	"mmcargs=setenv bootargs root=/dev/mmcblk0p${mmcpart} rw " \
	192	"rootwait\0" \
	193	"mmc_mmc=" \
	194	"run mmcload mmcargs addargs ; " \
	195	"bootm ${kernel_addr_r}\0" \
	196	"netload=tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \
	197	"net_nfs=" \
	198	"run netload nfsargs addip addargs ; " \
	199	"bootm ${kernel_addr_r}\0" \
	200	"nfsargs=" \
	201	"setenv bootargs root=/dev/nfs rw " \
	202	"nfsroot=${serverip}:${rootpath}${hostname},v3,tcp\0" \
	203	"try_bootscript=" \
	204	"mmc rescan;" \
	205	"if test -e mmc 0:1 ${bootscript} ; then " \
	206	"if load mmc 0:1 ${kernel_addr_r} ${bootscript};" \
	207	"then ; " \
	208	"echo Running bootscript... ; " \
	209	"source ${kernel_addr_r} ; " \
	210	"fi ; " \
	211	"fi\0"
	212
9ac5dda5 MV	213	#if defined(CONFIG_SPL_BUILD)
	214	#undef CONFIG_WATCHDOG
	215	#define CONFIG_HW_WATCHDOG
	216	#endif
	217
39cb4f3c	218	#endif /* __M53MENLO_CONFIG_H__ */