projects / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 8d67c368 SL |
2 | /* |
| 3 | * Copyright 2014 Freescale Semiconductor, Inc. | |
| 34f39ce8 | 4 | * Copyright 2020-2021 NXP |
| 8d67c368 SL |
5 | */ |
| 6 | ||
| 7 | /* | |
| 8 | * T2080 RDB/PCIe board configuration file | |
| 9 | */ | |
| 10 | ||
| 11 | #ifndef __T2080RDB_H | |
| 12 | #define __T2080RDB_H | |
| 13 | ||
| 1af3c7f4 SG |
14 | #include <linux/stringify.h> |
| 15 | ||
| 8d67c368 | 16 | #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ |
| 8d67c368 SL |
17 | #define CONFIG_FSL_SATA_V2 |
| 18 | ||
| 19 | /* High Level Configuration Options */ | |
| 8d67c368 | 20 | #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ |
| 8d67c368 SL |
21 | #define CONFIG_ENABLE_36BIT_PHYS |
| 22 | ||
| 8d67c368 | 23 | #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ |
| 51370d56 | 24 | #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS |
| 8d67c368 SL |
25 | |
| 26 | #ifdef CONFIG_RAMBOOT_PBL | |
| 4d666683 | 27 | #define CONFIG_SPL_FLUSH_IMAGE |
| 4d666683 SL |
28 | #define CONFIG_SPL_PAD_TO 0x40000 |
| 29 | #define CONFIG_SPL_MAX_SIZE 0x28000 | |
| 30 | #define RESET_VECTOR_OFFSET 0x27FFC | |
| 31 | #define BOOT_PAGE_OFFSET 0x27000 | |
| 32 | #ifdef CONFIG_SPL_BUILD | |
| 33 | #define CONFIG_SPL_SKIP_RELOCATE | |
| 34 | #define CONFIG_SPL_COMMON_INIT_DDR | |
| 35 | #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE | |
| 4d666683 SL |
36 | #endif |
| 37 | ||
| 88718be3 | 38 | #ifdef CONFIG_MTD_RAW_NAND |
| 4d666683 SL |
39 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) |
| 40 | #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 | |
| 41 | #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 | |
| 42 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) | |
| 4d666683 SL |
43 | #endif |
| 44 | ||
| 45 | #ifdef CONFIG_SPIFLASH | |
| 46 | #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC | |
| 4d666683 SL |
47 | #define CONFIG_SPL_SPI_FLASH_MINIMAL |
| 48 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) | |
| 49 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) | |
| 50 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) | |
| 51 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) | |
| 4d666683 SL |
52 | #ifndef CONFIG_SPL_BUILD |
| 53 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC | |
| 54 | #endif | |
| 4d666683 SL |
55 | #endif |
| 56 | ||
| 57 | #ifdef CONFIG_SDCARD | |
| 58 | #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC | |
| 4d666683 SL |
59 | #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) |
| 60 | #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) | |
| 61 | #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) | |
| 62 | #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) | |
| 4d666683 SL |
63 | #ifndef CONFIG_SPL_BUILD |
| 64 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC | |
| 65 | #endif | |
| 8d67c368 SL |
66 | #endif |
| 67 | ||
| 4d666683 SL |
68 | #endif /* CONFIG_RAMBOOT_PBL */ |
| 69 | ||
| 8d67c368 SL |
70 | #define CONFIG_SRIO_PCIE_BOOT_MASTER |
| 71 | #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE | |
| 72 | /* Set 1M boot space */ | |
| 73 | #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) | |
| 74 | #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ | |
| 75 | (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) | |
| 76 | #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc | |
| 8d67c368 SL |
77 | #endif |
| 78 | ||
| 8d67c368 SL |
79 | #ifndef CONFIG_RESET_VECTOR_ADDRESS |
| 80 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc | |
| 81 | #endif | |
| 82 | ||
| 83 | /* | |
| 84 | * These can be toggled for performance analysis, otherwise use default. | |
| 85 | */ | |
| 86 | #define CONFIG_SYS_CACHE_STASHING | |
| 87 | #define CONFIG_BTB /* toggle branch predition */ | |
| 8d67c368 | 88 | #ifdef CONFIG_DDR_ECC |
| 8d67c368 SL |
89 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef |
| 90 | #endif | |
| 91 | ||
| 8d67c368 SL |
92 | #ifndef __ASSEMBLY__ |
| 93 | unsigned long get_board_sys_clk(void); | |
| 8d67c368 SL |
94 | #endif |
| 95 | ||
| 96 | #define CONFIG_SYS_CLK_FREQ 66660000 | |
| 8d67c368 SL |
97 | |
| 98 | /* | |
| 99 | * Config the L3 Cache as L3 SRAM | |
| 100 | */ | |
| 4d666683 SL |
101 | #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 |
| 102 | #define CONFIG_SYS_L3_SIZE (512 << 10) | |
| 103 | #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) | |
| a09fea1d | 104 | #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) |
| 4d666683 SL |
105 | #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) |
| 106 | #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) | |
| 107 | #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) | |
| 8d67c368 SL |
108 | |
| 109 | #define CONFIG_SYS_DCSRBAR 0xf0000000 | |
| 110 | #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull | |
| 111 | ||
| 112 | /* EEPROM */ | |
| 8d67c368 SL |
113 | #define CONFIG_SYS_I2C_EEPROM_NXID |
| 114 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 | |
| 8d67c368 SL |
115 | |
| 116 | /* | |
| 117 | * DDR Setup | |
| 118 | */ | |
| 119 | #define CONFIG_VERY_BIG_RAM | |
| 120 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
| 121 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
| 122 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
| 123 | #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
| 8d67c368 SL |
124 | #define CONFIG_SYS_SPD_BUS_NUM 0 |
| 125 | #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ | |
| 126 | #define SPD_EEPROM_ADDRESS1 0x51 | |
| 127 | #define SPD_EEPROM_ADDRESS2 0x52 | |
| 128 | #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 | |
| 129 | #define CTRL_INTLV_PREFERED cacheline | |
| 130 | ||
| 131 | /* | |
| 132 | * IFC Definitions | |
| 133 | */ | |
| 134 | #define CONFIG_SYS_FLASH_BASE 0xe8000000 | |
| 135 | #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) | |
| 136 | #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) | |
| 137 | #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ | |
| 138 | CSPR_PORT_SIZE_16 | \ | |
| 139 | CSPR_MSEL_NOR | \ | |
| 140 | CSPR_V) | |
| 141 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) | |
| 142 | ||
| 143 | /* NOR Flash Timing Params */ | |
| 144 | #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 | |
| 145 | ||
| 146 | #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ | |
| 147 | FTIM0_NOR_TEADC(0x5) | \ | |
| 148 | FTIM0_NOR_TEAHC(0x5)) | |
| 149 | #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ | |
| 150 | FTIM1_NOR_TRAD_NOR(0x1A) |\ | |
| 151 | FTIM1_NOR_TSEQRAD_NOR(0x13)) | |
| 152 | #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ | |
| 153 | FTIM2_NOR_TCH(0x4) | \ | |
| 154 | FTIM2_NOR_TWPH(0x0E) | \ | |
| 155 | FTIM2_NOR_TWP(0x1c)) | |
| 156 | #define CONFIG_SYS_NOR_FTIM3 0x0 | |
| 157 | ||
| 158 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
| 159 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
| 160 | ||
| 161 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
| 162 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
| 163 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
| 164 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
| 165 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
| 166 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS } | |
| 167 | ||
| 168 | /* CPLD on IFC */ | |
| 169 | #define CONFIG_SYS_CPLD_BASE 0xffdf0000 | |
| 170 | #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) | |
| 171 | #define CONFIG_SYS_CSPR2_EXT (0xf) | |
| 172 | #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ | |
| 173 | | CSPR_PORT_SIZE_8 \ | |
| 174 | | CSPR_MSEL_GPCM \ | |
| 175 | | CSPR_V) | |
| 176 | #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) | |
| 177 | #define CONFIG_SYS_CSOR2 0x0 | |
| 178 | ||
| 179 | /* CPLD Timing parameters for IFC CS2 */ | |
| 180 | #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ | |
| 181 | FTIM0_GPCM_TEADC(0x0e) | \ | |
| 182 | FTIM0_GPCM_TEAHC(0x0e)) | |
| 183 | #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ | |
| 184 | FTIM1_GPCM_TRAD(0x1f)) | |
| 185 | #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ | |
| de519163 | 186 | FTIM2_GPCM_TCH(0x8) | \ |
| 8d67c368 SL |
187 | FTIM2_GPCM_TWP(0x1f)) |
| 188 | #define CONFIG_SYS_CS2_FTIM3 0x0 | |
| 189 | ||
| 190 | /* NAND Flash on IFC */ | |
| 191 | #define CONFIG_NAND_FSL_IFC | |
| 192 | #define CONFIG_SYS_NAND_BASE 0xff800000 | |
| 193 | #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) | |
| 194 | ||
| 195 | #define CONFIG_SYS_NAND_CSPR_EXT (0xf) | |
| 196 | #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | |
| 197 | | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ | |
| 198 | | CSPR_MSEL_NAND /* MSEL = NAND */ \ | |
| 199 | | CSPR_V) | |
| 200 | #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) | |
| 201 | ||
| 202 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | |
| 203 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | |
| 204 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | |
| 205 | | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ | |
| 206 | | CSOR_NAND_PGS_2K /* Page Size = 2K */\ | |
| 207 | | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ | |
| 208 | | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ | |
| 209 | ||
| 210 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
| 211 | ||
| 212 | /* ONFI NAND Flash mode0 Timing Params */ | |
| 213 | #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ | |
| 214 | FTIM0_NAND_TWP(0x18) | \ | |
| 215 | FTIM0_NAND_TWCHT(0x07) | \ | |
| 216 | FTIM0_NAND_TWH(0x0a)) | |
| 217 | #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ | |
| 218 | FTIM1_NAND_TWBE(0x39) | \ | |
| 219 | FTIM1_NAND_TRR(0x0e) | \ | |
| 220 | FTIM1_NAND_TRP(0x18)) | |
| 221 | #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ | |
| 222 | FTIM2_NAND_TREH(0x0a) | \ | |
| 223 | FTIM2_NAND_TWHRE(0x1e)) | |
| 224 | #define CONFIG_SYS_NAND_FTIM3 0x0 | |
| 225 | ||
| 226 | #define CONFIG_SYS_NAND_DDR_LAW 11 | |
| 227 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } | |
| 228 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
| 8d67c368 SL |
229 | #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) |
| 230 | ||
| 88718be3 | 231 | #if defined(CONFIG_MTD_RAW_NAND) |
| 8d67c368 SL |
232 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT |
| 233 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR | |
| 234 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK | |
| 235 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR | |
| 236 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
| 237 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
| 238 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
| 239 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
| 240 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT | |
| 241 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR | |
| 242 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK | |
| 243 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR | |
| 244 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
| 245 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
| 246 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
| 247 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
| 248 | #else | |
| 249 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT | |
| 250 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR | |
| 251 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK | |
| 252 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR | |
| 253 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
| 254 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
| 255 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
| 256 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
| 257 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT | |
| 258 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR | |
| 259 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK | |
| 260 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR | |
| 261 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
| 262 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
| 263 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
| 264 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
| 265 | #endif | |
| 266 | ||
| 267 | #if defined(CONFIG_RAMBOOT_PBL) | |
| 268 | #define CONFIG_SYS_RAMBOOT | |
| 269 | #endif | |
| 270 | ||
| 4d666683 SL |
271 | #ifdef CONFIG_SPL_BUILD |
| 272 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE | |
| 273 | #else | |
| 274 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ | |
| 275 | #endif | |
| 276 | ||
| 8d67c368 SL |
277 | #define CONFIG_HWCONFIG |
| 278 | ||
| 279 | /* define to use L1 as initial stack */ | |
| 280 | #define CONFIG_L1_INIT_RAM | |
| 281 | #define CONFIG_SYS_INIT_RAM_LOCK | |
| 282 | #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ | |
| 283 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf | |
| b3142e2c | 284 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 |
| 8d67c368 SL |
285 | /* The assembler doesn't like typecast */ |
| 286 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ | |
| 287 | ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ | |
| 288 | CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) | |
| 289 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 | |
| 290 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ | |
| 291 | GENERATED_GBL_DATA_SIZE) | |
| 292 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
| 9307cbab | 293 | #define CONFIG_SYS_MONITOR_LEN (768 * 1024) |
| 8d67c368 SL |
294 | |
| 295 | /* | |
| 296 | * Serial Port | |
| 297 | */ | |
| 8d67c368 SL |
298 | #define CONFIG_SYS_NS16550_SERIAL |
| 299 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
| 300 | #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) | |
| 301 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
| 302 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
| 303 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) | |
| 304 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) | |
| 305 | #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) | |
| 306 | #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) | |
| 307 | ||
| 8d67c368 SL |
308 | /* |
| 309 | * I2C | |
| 310 | */ | |
| 8e4be6df | 311 | |
| 8d67c368 SL |
312 | #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ |
| 313 | #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ | |
| 314 | #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ | |
| 315 | #define I2C_MUX_CH_DEFAULT 0x8 | |
| 316 | ||
| e5abb92c YZ |
317 | #define I2C_MUX_CH_VOL_MONITOR 0xa |
| 318 | ||
| 319 | #define CONFIG_VID_FLS_ENV "t208xrdb_vdd_mv" | |
| 320 | #ifndef CONFIG_SPL_BUILD | |
| 321 | #define CONFIG_VID | |
| 322 | #endif | |
| 323 | #define CONFIG_VOL_MONITOR_IR36021_SET | |
| 324 | #define CONFIG_VOL_MONITOR_IR36021_READ | |
| 325 | /* The lowest and highest voltage allowed for T208xRDB */ | |
| 326 | #define VDD_MV_MIN 819 | |
| 327 | #define VDD_MV_MAX 1212 | |
| 8d67c368 SL |
328 | |
| 329 | /* | |
| 330 | * RapidIO | |
| 331 | */ | |
| 332 | #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 | |
| 333 | #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull | |
| 334 | #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ | |
| 335 | #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 | |
| 336 | #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull | |
| 337 | #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ | |
| 338 | /* | |
| 339 | * for slave u-boot IMAGE instored in master memory space, | |
| 340 | * PHYS must be aligned based on the SIZE | |
| 341 | */ | |
| e4911815 LG |
342 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull |
| 343 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull | |
| 344 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ | |
| 345 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull | |
| 8d67c368 SL |
346 | /* |
| 347 | * for slave UCODE and ENV instored in master memory space, | |
| 348 | * PHYS must be aligned based on the SIZE | |
| 349 | */ | |
| e4911815 | 350 | #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull |
| 8d67c368 SL |
351 | #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull |
| 352 | #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ | |
| 353 | ||
| 354 | /* slave core release by master*/ | |
| 355 | #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 | |
| 356 | #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ | |
| 357 | ||
| 358 | /* | |
| 359 | * SRIO_PCIE_BOOT - SLAVE | |
| 360 | */ | |
| 361 | #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE | |
| 362 | #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 | |
| 363 | #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ | |
| 364 | (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) | |
| 365 | #endif | |
| 366 | ||
| 367 | /* | |
| 368 | * eSPI - Enhanced SPI | |
| 369 | */ | |
| 8d67c368 SL |
370 | |
| 371 | /* | |
| 372 | * General PCI | |
| 373 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
| 374 | */ | |
| b38eaec5 RD |
375 | #define CONFIG_PCIE1 /* PCIE controller 1 */ |
| 376 | #define CONFIG_PCIE2 /* PCIE controller 2 */ | |
| 377 | #define CONFIG_PCIE3 /* PCIE controller 3 */ | |
| 378 | #define CONFIG_PCIE4 /* PCIE controller 4 */ | |
| 8d67c368 SL |
379 | #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ |
| 380 | /* controller 1, direct to uli, tgtid 3, Base address 20000 */ | |
| 381 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 | |
| 8d67c368 | 382 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull |
| 8d67c368 | 383 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 |
| 8d67c368 | 384 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull |
| 8d67c368 SL |
385 | |
| 386 | /* controller 2, Slot 2, tgtid 2, Base address 201000 */ | |
| 387 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 | |
| 8d67c368 | 388 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull |
| 8d67c368 | 389 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 |
| 8d67c368 | 390 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull |
| 8d67c368 SL |
391 | |
| 392 | /* controller 3, Slot 1, tgtid 1, Base address 202000 */ | |
| 393 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 | |
| 8d67c368 | 394 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull |
| 8d67c368 | 395 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 |
| 8d67c368 | 396 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull |
| 8d67c368 SL |
397 | |
| 398 | /* controller 4, Base address 203000 */ | |
| 399 | #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 | |
| 8d67c368 | 400 | #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull |
| 8d67c368 | 401 | #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull |
| 8d67c368 SL |
402 | |
| 403 | #ifdef CONFIG_PCI | |
| 8d67c368 | 404 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
| 8d67c368 SL |
405 | #endif |
| 406 | ||
| 407 | /* Qman/Bman */ | |
| 408 | #ifndef CONFIG_NOBQFMAN | |
| 8d67c368 SL |
409 | #define CONFIG_SYS_BMAN_NUM_PORTALS 18 |
| 410 | #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 | |
| 411 | #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull | |
| 412 | #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 | |
| 3fa66db4 JL |
413 | #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 |
| 414 | #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 | |
| 415 | #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE | |
| 416 | #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) | |
| 417 | #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ | |
| 418 | CONFIG_SYS_BMAN_CENA_SIZE) | |
| 419 | #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) | |
| 420 | #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 | |
| 8d67c368 SL |
421 | #define CONFIG_SYS_QMAN_NUM_PORTALS 18 |
| 422 | #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 | |
| 423 | #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull | |
| 424 | #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 | |
| 3fa66db4 JL |
425 | #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 |
| 426 | #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 | |
| 427 | #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE | |
| 428 | #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) | |
| 429 | #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ | |
| 430 | CONFIG_SYS_QMAN_CENA_SIZE) | |
| 431 | #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) | |
| 432 | #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 | |
| 8d67c368 SL |
433 | |
| 434 | #define CONFIG_SYS_DPAA_FMAN | |
| 435 | #define CONFIG_SYS_DPAA_PME | |
| 436 | #define CONFIG_SYS_PMAN | |
| 437 | #define CONFIG_SYS_DPAA_DCE | |
| 438 | #define CONFIG_SYS_DPAA_RMAN /* RMan */ | |
| 439 | #define CONFIG_SYS_INTERLAKEN | |
| 440 | ||
| 441 | /* Default address of microcode for the Linux Fman driver */ | |
| 442 | #if defined(CONFIG_SPIFLASH) | |
| 443 | /* | |
| 444 | * env is stored at 0x100000, sector size is 0x10000, ucode is stored after | |
| 445 | * env, so we got 0x110000. | |
| 446 | */ | |
| ef531c73 | 447 | #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 |
| 8d67c368 SL |
448 | |
| 449 | #elif defined(CONFIG_SDCARD) | |
| 450 | /* | |
| 451 | * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is | |
| 4d666683 SL |
452 | * about 1MB (2048 blocks), Env is stored after the image, and the env size is |
| 453 | * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. | |
| 8d67c368 | 454 | */ |
| 4d666683 | 455 | #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) |
| 8d67c368 | 456 | |
| 88718be3 | 457 | #elif defined(CONFIG_MTD_RAW_NAND) |
| 4d666683 | 458 | #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) |
| 8d67c368 SL |
459 | #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) |
| 460 | /* | |
| 461 | * Slave has no ucode locally, it can fetch this from remote. When implementing | |
| 462 | * in two corenet boards, slave's ucode could be stored in master's memory | |
| 463 | * space, the address can be mapped from slave TLB->slave LAW-> | |
| 464 | * slave SRIO or PCIE outbound window->master inbound window-> | |
| 465 | * master LAW->the ucode address in master's memory space. | |
| 466 | */ | |
| ef531c73 | 467 | #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 |
| 8d67c368 | 468 | #else |
| ef531c73 | 469 | #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 |
| 8d67c368 SL |
470 | #endif |
| 471 | #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 | |
| 472 | #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) | |
| 473 | #endif /* CONFIG_NOBQFMAN */ | |
| 474 | ||
| 475 | #ifdef CONFIG_SYS_DPAA_FMAN | |
| 8d67c368 SL |
476 | #define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */ |
| 477 | #define RGMII_PHY2_ADDR 0x02 | |
| 478 | #define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */ | |
| 479 | #define CORTINA_PHY_ADDR2 0x0d | |
| 4e21a555 CG |
480 | /* Aquantia AQ1202 10G Base-T used by board revisions up to C */ |
| 481 | #define FM1_10GEC3_PHY_ADDR 0x00 | |
| 8d67c368 | 482 | #define FM1_10GEC4_PHY_ADDR 0x01 |
| 4e21a555 CG |
483 | /* Aquantia AQR113C 10G Base-T used by board revisions D and up */ |
| 484 | #define AQR113C_PHY_ADDR1 0x00 | |
| 485 | #define AQR113C_PHY_ADDR2 0x08 | |
| 8d67c368 SL |
486 | #endif |
| 487 | ||
| 8d67c368 | 488 | #ifdef CONFIG_FMAN_ENET |
| 8d67c368 | 489 | #define CONFIG_ETHPRIME "FM1@DTSEC3" |
| 8d67c368 SL |
490 | #endif |
| 491 | ||
| 492 | /* | |
| 493 | * SATA | |
| 494 | */ | |
| 495 | #ifdef CONFIG_FSL_SATA_V2 | |
| 8d67c368 SL |
496 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 |
| 497 | #define CONFIG_SATA1 | |
| 498 | #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR | |
| 499 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
| 500 | #define CONFIG_SATA2 | |
| 501 | #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR | |
| 502 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA | |
| 503 | #define CONFIG_LBA48 | |
| 8d67c368 SL |
504 | #endif |
| 505 | ||
| 506 | /* | |
| 507 | * USB | |
| 508 | */ | |
| 8850c5d5 | 509 | #ifdef CONFIG_USB_EHCI_HCD |
| 8d67c368 SL |
510 | #define CONFIG_USB_EHCI_FSL |
| 511 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
| 8d67c368 SL |
512 | #define CONFIG_HAS_FSL_DR_USB |
| 513 | #endif | |
| 514 | ||
| 515 | /* | |
| 516 | * SDHC | |
| 517 | */ | |
| 518 | #ifdef CONFIG_MMC | |
| 8d67c368 SL |
519 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR |
| 520 | #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT | |
| 8d67c368 SL |
521 | #endif |
| 522 | ||
| 4feac1c6 SL |
523 | /* |
| 524 | * Dynamic MTD Partition support with mtdparts | |
| 525 | */ | |
| 4feac1c6 | 526 | |
| 8d67c368 SL |
527 | /* |
| 528 | * Environment | |
| 529 | */ | |
| 530 | ||
| 8d67c368 SL |
531 | /* |
| 532 | * Miscellaneous configurable options | |
| 533 | */ | |
| 8d67c368 SL |
534 | |
| 535 | /* | |
| 536 | * For booting Linux, the board info and command line data | |
| 537 | * have to be in the first 64 MB of memory, since this is | |
| 538 | * the maximum mapped by the Linux kernel during initialization. | |
| 539 | */ | |
| 540 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ | |
| 541 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
| 542 | ||
| 543 | #ifdef CONFIG_CMD_KGDB | |
| 544 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
| 545 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
| 546 | #endif | |
| 547 | ||
| 548 | /* | |
| 549 | * Environment Configuration | |
| 550 | */ | |
| 551 | #define CONFIG_ROOTPATH "/opt/nfsroot" | |
| 552 | #define CONFIG_BOOTFILE "uImage" | |
| 553 | #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ | |
| 554 | ||
| 8d67c368 SL |
555 | #define __USB_PHY_TYPE utmi |
| 556 | ||
| 557 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 558 | "hwconfig=fsl_ddr:" \ | |
| 559 | "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ | |
| 560 | "bank_intlv=auto;" \ | |
| 561 | "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ | |
| 562 | "netdev=eth0\0" \ | |
| 563 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ | |
| 564 | "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ | |
| 565 | "tftpflash=tftpboot $loadaddr $uboot && " \ | |
| 566 | "protect off $ubootaddr +$filesize && " \ | |
| 567 | "erase $ubootaddr +$filesize && " \ | |
| 568 | "cp.b $loadaddr $ubootaddr $filesize && " \ | |
| 569 | "protect on $ubootaddr +$filesize && " \ | |
| 570 | "cmp.b $loadaddr $ubootaddr $filesize\0" \ | |
| 571 | "consoledev=ttyS0\0" \ | |
| 572 | "ramdiskaddr=2000000\0" \ | |
| 573 | "ramdiskfile=t2080rdb/ramdisk.uboot\0" \ | |
| b24a4f62 | 574 | "fdtaddr=1e00000\0" \ |
| 8d67c368 | 575 | "fdtfile=t2080rdb/t2080rdb.dtb\0" \ |
| 3246584d | 576 | "bdev=sda3\0" |
| 8d67c368 SL |
577 | |
| 578 | /* | |
| 579 | * For emulation this causes u-boot to jump to the start of the | |
| 580 | * proof point app code automatically | |
| 581 | */ | |
| 7ae1b080 | 582 | #define PROOF_POINTS \ |
| 8d67c368 SL |
583 | "setenv bootargs root=/dev/$bdev rw " \ |
| 584 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 585 | "cpu 1 release 0x29000000 - - -;" \ | |
| 586 | "cpu 2 release 0x29000000 - - -;" \ | |
| 587 | "cpu 3 release 0x29000000 - - -;" \ | |
| 588 | "cpu 4 release 0x29000000 - - -;" \ | |
| 589 | "cpu 5 release 0x29000000 - - -;" \ | |
| 590 | "cpu 6 release 0x29000000 - - -;" \ | |
| 591 | "cpu 7 release 0x29000000 - - -;" \ | |
| 592 | "go 0x29000000" | |
| 593 | ||
| 7ae1b080 | 594 | #define HVBOOT \ |
| 8d67c368 SL |
595 | "setenv bootargs config-addr=0x60000000; " \ |
| 596 | "bootm 0x01000000 - 0x00f00000" | |
| 597 | ||
| 7ae1b080 | 598 | #define ALU \ |
| 8d67c368 SL |
599 | "setenv bootargs root=/dev/$bdev rw " \ |
| 600 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 601 | "cpu 1 release 0x01000000 - - -;" \ | |
| 602 | "cpu 2 release 0x01000000 - - -;" \ | |
| 603 | "cpu 3 release 0x01000000 - - -;" \ | |
| 604 | "cpu 4 release 0x01000000 - - -;" \ | |
| 605 | "cpu 5 release 0x01000000 - - -;" \ | |
| 606 | "cpu 6 release 0x01000000 - - -;" \ | |
| 607 | "cpu 7 release 0x01000000 - - -;" \ | |
| 608 | "go 0x01000000" | |
| 609 | ||
| 7ae1b080 | 610 | #define LINUXBOOTCOMMAND \ |
| 8d67c368 SL |
611 | "setenv bootargs root=/dev/ram rw " \ |
| 612 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 613 | "setenv ramdiskaddr 0x02000000;" \ | |
| 614 | "setenv fdtaddr 0x00c00000;" \ | |
| 615 | "setenv loadaddr 0x1000000;" \ | |
| 616 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
| 617 | ||
| 7ae1b080 | 618 | #define HDBOOT \ |
| 8d67c368 SL |
619 | "setenv bootargs root=/dev/$bdev rw " \ |
| 620 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 621 | "tftp $loadaddr $bootfile;" \ | |
| 622 | "tftp $fdtaddr $fdtfile;" \ | |
| 623 | "bootm $loadaddr - $fdtaddr" | |
| 624 | ||
| 7ae1b080 | 625 | #define NFSBOOTCOMMAND \ |
| 8d67c368 SL |
626 | "setenv bootargs root=/dev/nfs rw " \ |
| 627 | "nfsroot=$serverip:$rootpath " \ | |
| 628 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
| 629 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 630 | "tftp $loadaddr $bootfile;" \ | |
| 631 | "tftp $fdtaddr $fdtfile;" \ | |
| 632 | "bootm $loadaddr - $fdtaddr" | |
| 633 | ||
| 7ae1b080 | 634 | #define RAMBOOTCOMMAND \ |
| 8d67c368 SL |
635 | "setenv bootargs root=/dev/ram rw " \ |
| 636 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 637 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
| 638 | "tftp $loadaddr $bootfile;" \ | |
| 639 | "tftp $fdtaddr $fdtfile;" \ | |
| 640 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
| 641 | ||
| 7ae1b080 | 642 | #define CONFIG_BOOTCOMMAND LINUXBOOTCOMMAND |
| 8d67c368 | 643 | |
| 8d67c368 | 644 | #include <asm/fsl_secure_boot.h> |
| ef6c55a2 | 645 | |
| 8d67c368 | 646 | #endif /* __T2080RDB_H */ |