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b1babef8 HZ |
1 | /* |
2 | * Keystone2: DDR3 configuration | |
3 | * | |
4 | * (C) Copyright 2012-2014 | |
5 | * Texas Instruments Incorporated, <www.ti.com> | |
6 | * | |
7 | * SPDX-License-Identifier: GPL-2.0+ | |
8 | */ | |
9 | ||
10 | #ifndef __DDR3_CFG_H | |
11 | #define __DDR3_CFG_H | |
12 | ||
d9a76e77 | 13 | #include <asm/arch/ddr3.h> |
a9068479 | 14 | |
345af534 HZ |
15 | extern struct ddr3_phy_config ddr3phy_1600_2g; |
16 | extern struct ddr3_emif_config ddr3_1600_2g; | |
17 | ||
d9a76e77 | 18 | int ddr3_get_dimm_params_from_spd(struct ddr3_spd_cb *spd_cb); |
b1babef8 HZ |
19 | |
20 | #endif /* __DDR3_CFG_H */ |