[u-boot.git] / include / configs / caddy2.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * esd vme8349 U-Boot configuration file
 * Copyright (c) 2008, 2009 esd gmbh Hannover Germany
 *
 * (C) Copyright 2006-2010
 * Wolfgang Denk, DENX Software Engineering, [email protected].
 *
 * [email protected]
 * Based on the MPC8349EMDS config.
 */

/*
 * vme8349 board configuration file.
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_E300		1	/* E300 Family */

/* Don't enable PCI2 on vme834x - it doesn't exist physically. */
#undef CONFIG_MPC83XX_PCI2		/* support for 2nd PCI controller */

#undef CONFIG_SYS_DRAM_TEST			/* memory test, takes time */
#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest region */
#define CONFIG_SYS_MEMTEST_END		0x00100000

/*
 * DDR Setup
 */
#define CONFIG_DDR_ECC			/* only for ECC DDR module */
#define CONFIG_DDR_ECC_CMD		/* use DDR ECC user commands */
#define CONFIG_SPD_EEPROM
#define SPD_EEPROM_ADDRESS		0x54
#define CONFIG_SYS_READ_SPD		vme8349_read_spd
#define CONFIG_SYS_83XX_DDR_USES_CS0	/* esd; Fsl board uses CS2/CS3 */

/*
 * 32-bit data path mode.
 *
 * Please note that using this mode for devices with the real density of 64-bit
 * effectively reduces the amount of available memory due to the effect of
 * wrapping around while translating address to row/columns, for example in the
 * 256MB module the upper 128MB get aliased with contents of the lower
 * 128MB); normally this define should be used for devices with real 32-bit
 * data path.
 */
#undef CONFIG_DDR_32BIT

#define CONFIG_SYS_DDR_BASE		0x00000000	/* DDR is sys memory*/
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN \
					| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
#define CONFIG_DDR_2T_TIMING
#define CONFIG_SYS_DDRCDR		(DDRCDR_DHC_EN \
					| DDRCDR_ODT \
					| DDRCDR_Q_DRN)
					/* 0x80080001 */

/*
 * FLASH on the Local Bus
 */
#define CONFIG_SYS_FLASH_BASE		0xffc00000	/* start of FLASH   */
#define CONFIG_SYS_FLASH_SIZE		4		/* flash size in MB */


#define CONFIG_SYS_WINDOW1_BASE		0xf0000000


#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device*/

#undef CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase TO (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write TO (ms) */

#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */

#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#else
#undef CONFIG_SYS_RAMBOOT
#endif

#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xF7000000	/* Initial RAM addr */
#define CONFIG_SYS_INIT_RAM_SIZE		0x1000		/* size */

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
					 GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB */
#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)	/* Malloc size */

/*
 * Local Bus LCRR and LBCR regs
 *    LCRR:  no DLL bypass, Clock divider is 4
 * External Local Bus rate is
 *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
 */
#define CONFIG_SYS_LBC_LBCR	0x00000000

#undef CONFIG_SYS_LB_SDRAM	/* if board has SDRAM on local bus */

/*
 * Serial Port
 */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_BAUDRATE_TABLE  \
		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}

#define CONFIG_SYS_NS16550_COM1		(CONFIG_SYS_IMMR + 0x4500)
#define CONFIG_SYS_NS16550_COM2		(CONFIG_SYS_IMMR + 0x4600)

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
#define CONFIG_SYS_FSL_I2C2_SPEED	400000
#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */

#define CONFIG_SYS_I2C_8574_ADDR2       0x20    /* I2C1, PCF8574 */

/* TSEC */
#define CONFIG_SYS_TSEC1_OFFSET	0x24000
#define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
#define CONFIG_SYS_TSEC2_OFFSET 0x25000
#define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)

/*
 * General PCI
 * Addresses are mapped 1-1.
 */
#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI1_IO_BASE		0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS		0xE2000000
#define CONFIG_SYS_PCI1_IO_SIZE		0x00100000	/* 1M */

#define CONFIG_SYS_PCI2_MEM_BASE	0xA0000000
#define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BASE
#define CONFIG_SYS_PCI2_MEM_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI2_MMIO_BASE	0xB0000000
#define CONFIG_SYS_PCI2_MMIO_PHYS	CONFIG_SYS_PCI2_MMIO_BASE
#define CONFIG_SYS_PCI2_MMIO_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI2_IO_BASE		0x00000000
#define CONFIG_SYS_PCI2_IO_PHYS		0xE2100000
#define CONFIG_SYS_PCI2_IO_SIZE		0x00100000	/* 1M */

#if defined(CONFIG_PCI)

#undef CONFIG_EEPRO100
#undef CONFIG_TULIP

#if !defined(CONFIG_PCI_PNP)
	#define PCI_ENET0_IOADDR	0xFIXME
	#define PCI_ENET0_MEMADDR	0xFIXME
	#define PCI_IDSEL_NUMBER	0xFIXME
#endif

#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID	0x1957	/* Freescale */

#endif	/* CONFIG_PCI */

/*
 * TSEC configuration
 */

#if defined(CONFIG_TSEC_ENET)

#define CONFIG_GMII			/* MII PHY management */
#define CONFIG_TSEC1
#define CONFIG_TSEC1_NAME	"TSEC0"
#define CONFIG_TSEC2
#define CONFIG_TSEC2_NAME	"TSEC1"
#define CONFIG_PHY_M88E1111
#define TSEC1_PHY_ADDR		0x08
#define TSEC2_PHY_ADDR		0x10
#define TSEC1_PHYIDX		0
#define TSEC2_PHYIDX		0
#define TSEC1_FLAGS		TSEC_GIGABIT
#define TSEC2_FLAGS		TSEC_GIGABIT

/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME		"TSEC0"

#endif	/* CONFIG_TSEC_ENET */

/*
 * Environment
 */
#ifndef CONFIG_SYS_RAMBOOT
	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0xc0000)
	#define CONFIG_ENV_SECT_SIZE	0x20000	/* 128K(one sector) for env */
	#define CONFIG_ENV_SIZE		0x2000

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)

#else
	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
	#define CONFIG_ENV_SIZE		0x2000
#endif

#define CONFIG_LOADS_ECHO		/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE

/*
 * Command line configuration.
 */
#define CONFIG_SYS_RTC_BUS_NUM  0x01
#define CONFIG_SYS_I2C_RTC_ADDR	0x32
#define CONFIG_RTC_RX8025

/* Pass Ethernet MAC to VxWorks */
#define CONFIG_SYS_VXWORKS_MAC_PTR	0x000043f0

#undef CONFIG_WATCHDOG			/* watchdog disabled */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 256 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)	/* Init Memory map for Linux*/

#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */

/* System IO Config */
#define CONFIG_SYS_SICRH 0
#define CONFIG_SYS_SICRL SICRL_LDP_A

#define CONFIG_SYS_GPIO1_PRELIM
#define CONFIG_SYS_GPIO1_DIR	0x00100000
#define CONFIG_SYS_GPIO1_DAT	0x00100000

#define CONFIG_SYS_GPIO2_PRELIM
#define CONFIG_SYS_GPIO2_DIR	0x78900000
#define CONFIG_SYS_GPIO2_DAT	0x70100000

#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
#endif

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
#endif

/*
 * Environment Configuration
 */
#define CONFIG_ENV_OVERWRITE

#if defined(CONFIG_TSEC_ENET)
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#endif

#define CONFIG_HOSTNAME		"VME8349"
#define CONFIG_ROOTPATH		"/tftpboot/rootfs"
#define CONFIG_BOOTFILE		"uImage"

#define CONFIG_LOADADDR		800000	/* def location for tftp and bootm */

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"hostname=vme8349\0"						\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
	"flash_nfs=run nfsargs addip addtty;"				\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip addtty;"				\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"	\
		"bootm\0"						\
	"load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0"		\
	"update=protect off fff00000 fff3ffff; "			\
		"era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
	"upd=run load update\0"						\
	"fdtaddr=780000\0"						\
	"fdtfile=vme8349.dtb\0"						\
	""

#define CONFIG_NFSBOOTCOMMAND						\
	"setenv bootargs root=/dev/nfs rw "				\
		"nfsroot=$serverip:$rootpath "				\
		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"	\
							"$netdev:off "	\
		"console=$consoledev,$baudrate $othbootargs;"		\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr - $fdtaddr"

#define CONFIG_RAMBOOTCOMMAND						\
	"setenv bootargs root=/dev/ram rw "				\
		"console=$consoledev,$baudrate $othbootargs;"		\
	"tftp $ramdiskaddr $ramdiskfile;"				\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr $ramdiskaddr $fdtaddr"

#define CONFIG_BOOTCOMMAND	"run flash_self"

#ifndef __ASSEMBLY__
int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen,
		     unsigned char *buffer, int len);
#endif

#endif	/* __CONFIG_H */
Commit	Line	Data
904c47fc MS	1	/* SPDX-License-Identifier: GPL-2.0+ */
	2	/*
	3	* esd vme8349 U-Boot configuration file
	4	* Copyright (c) 2008, 2009 esd gmbh Hannover Germany
	5	*
	6	* (C) Copyright 2006-2010
	7	* Wolfgang Denk, DENX Software Engineering, [email protected].
	8	*
	9	* [email protected]
	10	* Based on the MPC8349EMDS config.
	11	*/
	12
	13	/*
	14	* vme8349 board configuration file.
	15	*/
	16
	17	#ifndef __CONFIG_H
	18	#define __CONFIG_H
	19
	20	/*
	21	* High Level Configuration Options
	22	*/
	23	#define CONFIG_E300 1 /* E300 Family */
	24
	25	/* Don't enable PCI2 on vme834x - it doesn't exist physically. */
	26	#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
	27
904c47fc MS	28	#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
	29	#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
	30	#define CONFIG_SYS_MEMTEST_END 0x00100000
	31
	32	/*
	33	* DDR Setup
	34	*/
	35	#define CONFIG_DDR_ECC /* only for ECC DDR module */
	36	#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
	37	#define CONFIG_SPD_EEPROM
	38	#define SPD_EEPROM_ADDRESS 0x54
	39	#define CONFIG_SYS_READ_SPD vme8349_read_spd
	40	#define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */
	41
	42	/*
	43	* 32-bit data path mode.
	44	*
	45	* Please note that using this mode for devices with the real density of 64-bit
	46	* effectively reduces the amount of available memory due to the effect of
	47	* wrapping around while translating address to row/columns, for example in the
	48	* 256MB module the upper 128MB get aliased with contents of the lower
	49	* 128MB); normally this define should be used for devices with real 32-bit
	50	* data path.
	51	*/
	52	#undef CONFIG_DDR_32BIT
	53
	54	#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/
	55	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
	56	#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
	57	#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
	58	\| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
	59	#define CONFIG_DDR_2T_TIMING
	60	#define CONFIG_SYS_DDRCDR (DDRCDR_DHC_EN \
	61	\| DDRCDR_ODT \
	62	\| DDRCDR_Q_DRN)
	63	/* 0x80080001 */
	64
	65	/*
	66	* FLASH on the Local Bus
	67	*/
	68	#define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */
	69	#define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */
904c47fc	70
904c47fc MS	71
904c47fc MS	72	#define CONFIG_SYS_WINDOW1_BASE 0xf0000000
a8f97539	73
904c47fc MS	74
	75	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
	76	#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/
	77
	78	#undef CONFIG_SYS_FLASH_CHECKSUM
	79	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */
	80	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */
	81
	82	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
	83
	84	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
	85	#define CONFIG_SYS_RAMBOOT
	86	#else
	87	#undef CONFIG_SYS_RAMBOOT
	88	#endif
	89
	90	#define CONFIG_SYS_INIT_RAM_LOCK 1
	91	#define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000 /* Initial RAM addr */
	92	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* size */
	93
	94	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
	95	GENERATED_GBL_DATA_SIZE)
	96	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
	97
	98	#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */
	99	#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */
	100
	101	/*
	102	* Local Bus LCRR and LBCR regs
	103	* LCRR: no DLL bypass, Clock divider is 4
	104	* External Local Bus rate is
	105	* CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
	106	*/
904c47fc MS	107	#define CONFIG_SYS_LBC_LBCR 0x00000000
	108
	109	#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
	110
	111	/*
	112	* Serial Port
	113	*/
	114	#define CONFIG_SYS_NS16550_SERIAL
	115	#define CONFIG_SYS_NS16550_REG_SIZE 1
	116	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
	117
	118	#define CONFIG_SYS_BAUDRATE_TABLE \
	119	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
	120
	121	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
	122	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
	123
	124	/* I2C */
	125	#define CONFIG_SYS_I2C
	126	#define CONFIG_SYS_I2C_FSL
	127	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	128	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	129	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
	130	#define CONFIG_SYS_FSL_I2C2_SPEED 400000
	131	#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
	132	#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
	133	#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
	134	/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
	135
	136	#define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */
	137
	138	/* TSEC */
	139	#define CONFIG_SYS_TSEC1_OFFSET 0x24000
	140	#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
	141	#define CONFIG_SYS_TSEC2_OFFSET 0x25000
	142	#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
	143
	144	/*
	145	* General PCI
	146	* Addresses are mapped 1-1.
	147	*/
	148	#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
	149	#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
	150	#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
	151	#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
	152	#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
	153	#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
	154	#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
	155	#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
	156	#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
	157
	158	#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
	159	#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
	160	#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
	161	#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
	162	#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
	163	#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
	164	#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
	165	#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
	166	#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
	167
	168	#if defined(CONFIG_PCI)
	169
904c47fc MS	170	#undef CONFIG_EEPRO100
	171	#undef CONFIG_TULIP
	172
	173	#if !defined(CONFIG_PCI_PNP)
	174	#define PCI_ENET0_IOADDR 0xFIXME
	175	#define PCI_ENET0_MEMADDR 0xFIXME
	176	#define PCI_IDSEL_NUMBER 0xFIXME
	177	#endif
	178
	179	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
	180	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
	181
	182	#endif /* CONFIG_PCI */
	183
	184	/*
	185	* TSEC configuration
	186	*/
	187
	188	#if defined(CONFIG_TSEC_ENET)
	189
	190	#define CONFIG_GMII /* MII PHY management */
	191	#define CONFIG_TSEC1
	192	#define CONFIG_TSEC1_NAME "TSEC0"
	193	#define CONFIG_TSEC2
	194	#define CONFIG_TSEC2_NAME "TSEC1"
	195	#define CONFIG_PHY_M88E1111
	196	#define TSEC1_PHY_ADDR 0x08
	197	#define TSEC2_PHY_ADDR 0x10
	198	#define TSEC1_PHYIDX 0
	199	#define TSEC2_PHYIDX 0
	200	#define TSEC1_FLAGS TSEC_GIGABIT
	201	#define TSEC2_FLAGS TSEC_GIGABIT
	202
	203	/* Options are: TSEC[0-1] */
	204	#define CONFIG_ETHPRIME "TSEC0"
	205
	206	#endif /* CONFIG_TSEC_ENET */
	207
	208	/*
	209	* Environment
	210	*/
	211	#ifndef CONFIG_SYS_RAMBOOT
	212	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0xc0000)
	213	#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
	214	#define CONFIG_ENV_SIZE 0x2000
	215
	216	/* Address and size of Redundant Environment Sector */
	217	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
	218	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
	219
	220	#else
	221	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
	222	#define CONFIG_ENV_SIZE 0x2000
	223	#endif
	224
	225	#define CONFIG_LOADS_ECHO /* echo on for serial download */
	226	#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
	227
	228	/*
	229	* BOOTP options
	230	*/
	231	#define CONFIG_BOOTP_BOOTFILESIZE
	232
	233	/*
234	* Command line configuration.
235	*/
236	#define CONFIG_SYS_RTC_BUS_NUM 0x01
237	#define CONFIG_SYS_I2C_RTC_ADDR 0x32
238	#define CONFIG_RTC_RX8025
239
240	/* Pass Ethernet MAC to VxWorks */
241	#define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0
242
243	#undef CONFIG_WATCHDOG /* watchdog disabled */
244
245	/*
246	* Miscellaneous configurable options
247	*/
248	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
249
250	/*
251	* For booting Linux, the board info and command line data
252	* have to be in the first 256 MB of memory, since this is
253	* the maximum mapped by the Linux kernel during initialization.
254	*/
255	#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Init Memory map for Linux*/
256
257	#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
258
904c47fc MS	259	/* System IO Config */
	260	#define CONFIG_SYS_SICRH 0
	261	#define CONFIG_SYS_SICRL SICRL_LDP_A
	262
904c47fc MS	263	#define CONFIG_SYS_GPIO1_PRELIM
	264	#define CONFIG_SYS_GPIO1_DIR 0x00100000
	265	#define CONFIG_SYS_GPIO1_DAT 0x00100000
	266
	267	#define CONFIG_SYS_GPIO2_PRELIM
	268	#define CONFIG_SYS_GPIO2_DIR 0x78900000
	269	#define CONFIG_SYS_GPIO2_DAT 0x70100000
	270
904c47fc MS	271	#ifdef CONFIG_PCI
904c47fc MS	272	#define CONFIG_PCI_INDIRECT_BRIDGE
904c47fc MS	273	#endif
904c47fc MS	274
904c47fc MS	275	#if defined(CONFIG_CMD_KGDB)
	276	#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
	277	#endif
	278
	279	/*
	280	* Environment Configuration
	281	*/
	282	#define CONFIG_ENV_OVERWRITE
	283
	284	#if defined(CONFIG_TSEC_ENET)
	285	#define CONFIG_HAS_ETH0
	286	#define CONFIG_HAS_ETH1
	287	#endif
	288
	289	#define CONFIG_HOSTNAME "VME8349"
	290	#define CONFIG_ROOTPATH "/tftpboot/rootfs"
	291	#define CONFIG_BOOTFILE "uImage"
	292
	293	#define CONFIG_LOADADDR 800000 /* def location for tftp and bootm */
	294
	295	#define CONFIG_EXTRA_ENV_SETTINGS \
	296	"netdev=eth0\0" \
	297	"hostname=vme8349\0" \
	298	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	299	"nfsroot=${serverip}:${rootpath}\0" \
	300	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	301	"addip=setenv bootargs ${bootargs} " \
	302	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	303	":${hostname}:${netdev}:off panic=1\0" \
	304	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
	305	"flash_nfs=run nfsargs addip addtty;" \
	306	"bootm ${kernel_addr}\0" \
	307	"flash_self=run ramargs addip addtty;" \
	308	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
	309	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
	310	"bootm\0" \
	311	"load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \
	312	"update=protect off fff00000 fff3ffff; " \
	313	"era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
	314	"upd=run load update\0" \
	315	"fdtaddr=780000\0" \
	316	"fdtfile=vme8349.dtb\0" \
	317	""
	318
	319	#define CONFIG_NFSBOOTCOMMAND \
	320	"setenv bootargs root=/dev/nfs rw " \
	321	"nfsroot=$serverip:$rootpath " \
	322	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
	323	"$netdev:off " \
	324	"console=$consoledev,$baudrate $othbootargs;" \
	325	"tftp $loadaddr $bootfile;" \
	326	"tftp $fdtaddr $fdtfile;" \
	327	"bootm $loadaddr - $fdtaddr"
	328
	329	#define CONFIG_RAMBOOTCOMMAND \
	330	"setenv bootargs root=/dev/ram rw " \
	331	"console=$consoledev,$baudrate $othbootargs;" \
	332	"tftp $ramdiskaddr $ramdiskfile;" \
	333	"tftp $loadaddr $bootfile;" \
	334	"tftp $fdtaddr $fdtfile;" \
	335	"bootm $loadaddr $ramdiskaddr $fdtaddr"
	336
	337	#define CONFIG_BOOTCOMMAND "run flash_self"
	338
339	#ifndef __ASSEMBLY__
340	int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen,
341	unsigned char *buffer, int len);
342	#endif
343
344	#endif /* __CONFIG_H */