[u-boot.git] / include / configs / mcx.h

/*
 * Copyright (C) 2011 Ilya Yanok, Emcraft Systems
 *
 * Based on omap3_evm_config.h
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_OMAP			/* in a TI OMAP core */
#define CONFIG_OMAP3_MCX		/* working with mcx */
#define CONFIG_OMAP_GPIO
#define CONFIG_OMAP_COMMON
/* Common ARM Erratas */
#define CONFIG_ARM_ERRATA_454179
#define CONFIG_ARM_ERRATA_430973
#define CONFIG_ARM_ERRATA_621766

#define MACH_TYPE_MCX			3656
#define CONFIG_MACH_TYPE	MACH_TYPE_MCX
#define CONFIG_BOARD_LATE_INIT


#define CONFIG_SYS_CACHELINE_SIZE	64

#define CONFIG_EMIF4	/* The chip has EMIF4 controller */

#include <asm/arch/cpu.h>		/* get chip and board defs */
#include <asm/arch/omap.h>

/*
 * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader
 * and older u-boot.bin with the new U-Boot SPL.
 */
#define CONFIG_SYS_TEXT_BASE		0x80008000

/*
 * Display CPU and Board information
 */
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO

/* Clock Defines */
#define V_OSCK			26000000	/* Clock output from T2 */
#define V_SCLK			(V_OSCK >> 1)

#define CONFIG_MISC_INIT_R

#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG

/*
 * Size of malloc() pool
 */
#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB sector */
#define CONFIG_SYS_MALLOC_LEN		(1024 << 10)
/*
 * DDR related
 */
#define CONFIG_SYS_CS0_SIZE		(256 * 1024 * 1024)

/*
 * Hardware drivers
 */

/*
 * NS16550 Configuration
 */
#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */

#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK

/*
 * select serial console configuration
 */
#define CONFIG_CONS_INDEX		3
#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
#define CONFIG_SERIAL3			3	/* UART3 */

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
					115200}
#define CONFIG_MMC
#define CONFIG_OMAP_HSMMC
#define CONFIG_GENERIC_MMC
#define CONFIG_DOS_PARTITION

/* EHCI */
#define CONFIG_USB_STORAGE
#define CONFIG_OMAP3_GPIO_2
#define CONFIG_OMAP3_GPIO_5
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_OMAP
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO	57
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
#define	CONFIG_USB_HOST_ETHER
#define	CONFIG_USB_ETHER_ASIX
#define CONFIG_USB_ETHER_MCS7830

/* commands to include */
#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
#define CONFIG_CMD_FAT		/* FAT support			*/
#define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/

#define CONFIG_CMD_DATE
#define CONFIG_CMD_MMC		/* MMC support			*/
#define CONFIG_CMD_FAT		/* FAT support			*/
#define CONFIG_CMD_NAND		/* NAND support			*/
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#define CONFIG_RBTREE
#define CONFIG_LZO
#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTD_DEVICE
#define CONFIG_CMD_MTDPARTS

#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_I2C
#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
#define CONFIG_SYS_I2C_OMAP34XX

/* RTC */
#define CONFIG_RTC_DS1337
#define CONFIG_SYS_I2C_RTC_ADDR		0x68

#define CONFIG_CMD_MII
/*
 * Board NAND Info.
 */
#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
							/* to access nand */
#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
							/* to access */
							/* nand at CS0 */

#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
							/* NAND devices */
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV		"nand0"
/* start of jffs2 partition */
#define CONFIG_JFFS2_PART_OFFSET	0x680000
#define CONFIG_JFFS2_PART_SIZE		0xf980000	/* sz of jffs2 part */

/* Environment information */
#define CONFIG_BOOTDELAY	3

#define CONFIG_BOOTFILE		"uImage"

/* Setup MTD for NAND on the SOM */
#define MTDIDS_DEFAULT		"nand0=omap2-nand.0"
#define MTDPARTS_DEFAULT	"mtdparts=omap2-nand.0:512k(MLO),"	\
				"1m(u-boot),256k(env1),"		\
				"256k(env2),6m(kernel),6m(k_recovery),"	\
				"8m(fs_recovery),-(common_data)"

#define CONFIG_HOSTNAME mcx
#define CONFIG_EXTRA_ENV_SETTINGS \
	"adddbg=setenv bootargs ${bootargs} trace_buf_size=64M\0"	\
	"adddebug=setenv bootargs ${bootargs} earlyprintk=serial\0"	\
	"addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0"	\
	"addfb=setenv bootargs ${bootargs} vram=6M "			\
		"omapfb.vram=1:2M,2:2M,3:2M omapdss.def_disp=lcd\0"	\
	"addip_sta=setenv bootargs ${bootargs} "			\
		"ip=${ipaddr}:${serverip}:${gatewayip}:"		\
		"${netmask}:${hostname}:eth0:off\0"			\
	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0"		\
	"addip=if test -n ${ipdyn};then run addip_dyn;"			\
		"else run addip_sta;fi\0"				\
	"addmisc=setenv bootargs ${bootargs} ${misc}\0"			\
	"addtty=setenv bootargs ${bootargs} "				\
		"console=${consoledev},${baudrate}\0"			\
	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
	"baudrate=115200\0"						\
	"consoledev=ttyO2\0"						\
	"hostname=" __stringify(CONFIG_HOSTNAME) "\0"			\
	"loadaddr=0x82000000\0"						\
	"load=tftp ${loadaddr} ${u-boot}\0"				\
	"load_k=tftp ${loadaddr} ${bootfile}\0"				\
	"loaduimage=fatload mmc 0 ${loadaddr} uImage\0"			\
	"loadmlo=tftp ${loadaddr} ${mlo}\0"				\
	"mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0"			\
	"mmcargs=root=/dev/mmcblk0p2 rw "				\
		"rootfstype=ext3 rootwait\0"				\
	"mmcboot=echo Booting from mmc ...; "				\
		"run mmcargs; "						\
		"run addip addtty addmtd addfb addeth addmisc;"		\
		"run loaduimage; "					\
		"bootm ${loadaddr}\0"					\
	"net_nfs=run load_k; "						\
		"run nfsargs; "						\
		"run addip addtty addmtd addfb addeth addmisc;"		\
		"bootm ${loadaddr}\0"					\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0"		\
	"uboot_addr=0x80000\0"						\
	"update=nandecc sw;nand erase ${uboot_addr} 100000;"		\
		"nand write ${loadaddr} ${uboot_addr} 80000\0"		\
	"updatemlo=nandecc hw;nand erase 0 20000;"			\
		"nand write ${loadaddr} 0 20000\0"			\
	"upd=if run load;then echo Updating u-boot;if run update;"	\
		"then echo U-Boot updated;"				\
			"else echo Error updating u-boot !;"		\
			"echo Board without bootloader !!;"		\
		"fi;"							\
		"else echo U-Boot not downloaded..exiting;fi\0"		\
	"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0"		\
	"bootscript=echo Running bootscript from mmc ...; "		\
		"source ${loadaddr}\0"					\
	"nandargs=setenv bootargs ubi.mtd=7 "				\
		"root=ubi0:rootfs rootfstype=ubifs\0"			\
	"nandboot=echo Booting from nand ...; "				\
		"run nandargs; "					\
		"ubi part nand0,4;"					\
		"ubi readvol ${loadaddr} kernel;"			\
		"run addtty addmtd addfb addeth addmisc;"		\
		"bootm ${loadaddr}\0"					\
	"preboot=ubi part nand0,7;"					\
		"ubi readvol ${loadaddr} splash;"			\
		"bmp display ${loadaddr};"				\
		"gpio set 55\0"						\
	"swupdate_args=setenv bootargs root=/dev/ram "			\
		"quiet loglevel=1 "					\
		"consoleblank=0 ${swupdate_misc}\0"			\
	"swupdate=echo Running Sw-Update...;"				\
		"if printenv mtdparts;then echo Starting SwUpdate...; "	\
		"else mtdparts default;fi; "				\
		"ubi part nand0,5;"					\
		"ubi readvol 0x82000000 kernel_recovery;"		\
		"ubi part nand0,6;"					\
		"ubi readvol 0x84000000 fs_recovery;"			\
		"run swupdate_args; "					\
		"setenv bootargs ${bootargs} "				\
			"${mtdparts} "					\
			"vram=6M omapfb.vram=1:2M,2:2M,3:2M "		\
			"omapdss.def_disp=lcd;"				\
		"bootm 0x82000000 0x84000000\0"				\
	"bootcmd=mmc rescan;if fatload mmc 0 82000000 loadbootscr.scr;"	\
		"then source 82000000;else run nandboot;fi\0"

#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_CBSIZE		1024/* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		16	/* max number of command */
						/* args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
/* memtest works on */
#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
					0x01F00000) /* 31MB */

#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
								/* address */
#define CONFIG_PREBOOT

/*
 * AM3517 has 12 GP timers, they can be driven by the system clock
 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 * This rate is divided by a local divisor.
 */
#define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */

/*
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1

/*
 * FLASH and environment organization
 */

/* **** PISMO SUPPORT *** */
#define CONFIG_NAND
#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_NAND_OMAP_GPMC_PREFETCH
#define CONFIG_ENV_IS_IN_NAND
#define SMNAND_ENV_OFFSET		0x180000 /* environment starts here */

/* Redundant Environment */
#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
						2 * CONFIG_SYS_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE

/* Flash banks JFFS2 should use */
#define CONFIG_SYS_MAX_MTD_BANKS	(CONFIG_SYS_MAX_FLASH_BANKS + \
					CONFIG_SYS_MAX_NAND_DEVICE)
#define CONFIG_SYS_JFFS2_MEM_NAND
/* use flash_info[2] */
#define CONFIG_SYS_JFFS2_FIRST_BANK	CONFIG_SYS_MAX_FLASH_BANKS
#define CONFIG_SYS_JFFS2_NUM_BANKS	1

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE	0x800
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - \
					 GENERATED_GBL_DATA_SIZE)

/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_NAND_SIMPLE

#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBDISK_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_POWER_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"

#define CONFIG_SPL_TEXT_BASE		0x40200000 /*CONFIG_SYS_SRAM_START*/
#define CONFIG_SPL_MAX_SIZE		(54 * 1024)	/* 8 KB for stack */
#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK

/* move malloc and bss high to prevent clashing with the main image */
#define CONFIG_SYS_SPL_MALLOC_START	0x8f000000
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
#define CONFIG_SPL_BSS_START_ADDR	0x8f080000 /* end of RAM */
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000

#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"

/* NAND boot config */
#define CONFIG_SYS_NAND_PAGE_COUNT	64
#define CONFIG_SYS_NAND_PAGE_SIZE	2048
#define CONFIG_SYS_NAND_OOBSIZE		64
#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
#define CONFIG_SYS_NAND_ECCPOS		{40, 41, 42, 43, 44, 45, 46, 47,\
					 48, 49, 50, 51, 52, 53, 54, 55,\
					 56, 57, 58, 59, 60, 61, 62, 63}
#define CONFIG_SYS_NAND_ECCSIZE		256
#define CONFIG_SYS_NAND_ECCBYTES	3
#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_SW
#define CONFIG_SPL_NAND_SOFTECC

#define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_TEXT_BASE

#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000

/*
 * ethernet support
 *
 */
#if defined(CONFIG_CMD_NET)
#define CONFIG_DRIVER_TI_EMAC
#define CONFIG_DRIVER_TI_EMAC_USE_RMII
#define CONFIG_MII
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT 10
#endif

#define CONFIG_VIDEO
#define CONFIG_CFB_CONSOLE
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_SPLASH_SCREEN
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_CMD_BMP
#define CONFIG_VIDEO_OMAP3
#define CONFIG_SYS_CONSOLE_IS_IN_ENV

#endif /* __CONFIG_H */
Commit	Line	Data
4ab779cb IY	1	/*
	2	* Copyright (C) 2011 Ilya Yanok, Emcraft Systems
	3	*
	4	* Based on omap3_evm_config.h
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
4ab779cb IY	7	*/
	8
	9	#ifndef __CONFIG_H
	10	#define __CONFIG_H
	11
	12	/*
	13	* High Level Configuration Options
	14	*/
	15	#define CONFIG_OMAP /* in a TI OMAP core */
4ab779cb	16	#define CONFIG_OMAP3_MCX /* working with mcx */
308252ad	17	#define CONFIG_OMAP_GPIO
806d2792	18	#define CONFIG_OMAP_COMMON
c6f90e14 NM	19	/* Common ARM Erratas */
	20	#define CONFIG_ARM_ERRATA_454179
	21	#define CONFIG_ARM_ERRATA_430973
	22	#define CONFIG_ARM_ERRATA_621766
4ab779cb IY	23
	24	#define MACH_TYPE_MCX 3656
	25	#define CONFIG_MACH_TYPE MACH_TYPE_MCX
3ae6abb6	26	#define CONFIG_BOARD_LATE_INIT
4ab779cb	27
eb5e129a	28
4ab779cb IY	29	#define CONFIG_SYS_CACHELINE_SIZE 64
	30
	31	#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
	32
	33	#include <asm/arch/cpu.h> /* get chip and board defs */
987ec585	34	#include <asm/arch/omap.h>
4ab779cb	35
4ab779cb IY	36	/*
	37	* Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader
	38	* and older u-boot.bin with the new U-Boot SPL.
	39	*/
	40	#define CONFIG_SYS_TEXT_BASE 0x80008000
	41
	42	/*
	43	* Display CPU and Board information
	44	*/
	45	#define CONFIG_DISPLAY_CPUINFO
	46	#define CONFIG_DISPLAY_BOARDINFO
	47
	48	/* Clock Defines */
	49	#define V_OSCK 26000000 /* Clock output from T2 */
	50	#define V_SCLK (V_OSCK >> 1)
	51
	52	#define CONFIG_MISC_INIT_R
	53
	54	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
	55	#define CONFIG_SETUP_MEMORY_TAGS
	56	#define CONFIG_INITRD_TAG
	57	#define CONFIG_REVISION_TAG
	58
	59	/*
	60	* Size of malloc() pool
	61	*/
	62	#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
	63	#define CONFIG_SYS_MALLOC_LEN (1024 << 10)
	64	/*
	65	* DDR related
	66	*/
	67	#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
	68
	69	/*
	70	* Hardware drivers
	71	*/
	72
	73	/*
	74	* NS16550 Configuration
	75	*/
	76	#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
	77
4ab779cb IY	78	#define CONFIG_SYS_NS16550_SERIAL
	79	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	80	#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
	81
	82	/*
	83	* select serial console configuration
	84	*/
	85	#define CONFIG_CONS_INDEX 3
	86	#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
	87	#define CONFIG_SERIAL3 3 /* UART3 */
	88
	89	/* allow to overwrite serial and ethaddr */
	90	#define CONFIG_ENV_OVERWRITE
	91	#define CONFIG_BAUDRATE 115200
	92	#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
	93	115200}
	94	#define CONFIG_MMC
	95	#define CONFIG_OMAP_HSMMC
	96	#define CONFIG_GENERIC_MMC
	97	#define CONFIG_DOS_PARTITION
	98
	99	/* EHCI */
	100	#define CONFIG_USB_STORAGE
92671102	101	#define CONFIG_OMAP3_GPIO_2
4ab779cb IY	102	#define CONFIG_OMAP3_GPIO_5
	103	#define CONFIG_USB_EHCI
	104	#define CONFIG_USB_EHCI_OMAP
8c735b99	105	#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57
4ab779cb	106	#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
01d10aa1 SB	107	#define CONFIG_USB_HOST_ETHER
	108	#define CONFIG_USB_ETHER_ASIX
	109	#define CONFIG_USB_ETHER_MCS7830
4ab779cb IY	110
4ab779cb IY	111	/* commands to include */
4ab779cb IY	112	#define CONFIG_CMD_EXT2 /* EXT2 Support */
	113	#define CONFIG_CMD_FAT /* FAT support */
	114	#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
	115
	116	#define CONFIG_CMD_DATE
4ab779cb IY	117	#define CONFIG_CMD_MMC /* MMC support */
4ab779cb IY	118	#define CONFIG_CMD_FAT /* FAT support */
4ab779cb	119	#define CONFIG_CMD_NAND /* NAND support */
4ab779cb IY	120	#define CONFIG_CMD_CACHE
	121	#define CONFIG_CMD_UBI
	122	#define CONFIG_CMD_UBIFS
	123	#define CONFIG_RBTREE
	124	#define CONFIG_LZO
	125	#define CONFIG_MTD_PARTITIONS
	126	#define CONFIG_MTD_DEVICE
	127	#define CONFIG_CMD_MTDPARTS
	128
4ab779cb	129	#define CONFIG_SYS_NO_FLASH
6789e84e HS	130	#define CONFIG_SYS_I2C
	131	#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
	132	#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
	133	#define CONFIG_SYS_I2C_OMAP34XX
4ab779cb IY	134
	135	/* RTC */
	136	#define CONFIG_RTC_DS1337
	137	#define CONFIG_SYS_I2C_RTC_ADDR 0x68
	138
4ab779cb	139	#define CONFIG_CMD_MII
4ab779cb IY	140	/*
	141	* Board NAND Info.
	142	*/
	143	#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
	144	/* to access nand */
	145	#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
	146	/* to access */
	147	/* nand at CS0 */
	148
	149	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
	150	/* NAND devices */
4ab779cb IY	151	#define CONFIG_JFFS2_NAND
	152	/* nand device jffs2 lives on */
	153	#define CONFIG_JFFS2_DEV "nand0"
	154	/* start of jffs2 partition */
	155	#define CONFIG_JFFS2_PART_OFFSET 0x680000
	156	#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */
	157
	158	/* Environment information */
8f1fae26	159	#define CONFIG_BOOTDELAY 3
4ab779cb IY	160
	161	#define CONFIG_BOOTFILE "uImage"
	162
f89a8b6a SB	163	/* Setup MTD for NAND on the SOM */
	164	#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
	165	#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \
	166	"1m(u-boot),256k(env1)," \
	167	"256k(env2),6m(kernel),6m(k_recovery)," \
	168	"8m(fs_recovery),-(common_data)"
	169
	170	#define CONFIG_HOSTNAME mcx
4ab779cb	171	#define CONFIG_EXTRA_ENV_SETTINGS \
f89a8b6a SB	172	"adddbg=setenv bootargs ${bootargs} trace_buf_size=64M\0" \
	173	"adddebug=setenv bootargs ${bootargs} earlyprintk=serial\0" \
	174	"addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \
	175	"addfb=setenv bootargs ${bootargs} vram=6M " \
	176	"omapfb.vram=1:2M,2:2M,3:2M omapdss.def_disp=lcd\0" \
	177	"addip_sta=setenv bootargs ${bootargs} " \
	178	"ip=${ipaddr}:${serverip}:${gatewayip}:" \
	179	"${netmask}:${hostname}:eth0:off\0" \
	180	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
	181	"addip=if test -n ${ipdyn};then run addip_dyn;" \
	182	"else run addip_sta;fi\0" \
	183	"addmisc=setenv bootargs ${bootargs} ${misc}\0" \
	184	"addtty=setenv bootargs ${bootargs} " \
	185	"console=${consoledev},${baudrate}\0" \
	186	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
	187	"baudrate=115200\0" \
	188	"consoledev=ttyO2\0" \
4a8c3f69	189	"hostname=" __stringify(CONFIG_HOSTNAME) "\0" \
f89a8b6a SB	190	"loadaddr=0x82000000\0" \
	191	"load=tftp ${loadaddr} ${u-boot}\0" \
	192	"load_k=tftp ${loadaddr} ${bootfile}\0" \
	193	"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
	194	"loadmlo=tftp ${loadaddr} ${mlo}\0" \
4a8c3f69	195	"mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \
f89a8b6a SB	196	"mmcargs=root=/dev/mmcblk0p2 rw " \
	197	"rootfstype=ext3 rootwait\0" \
	198	"mmcboot=echo Booting from mmc ...; " \
	199	"run mmcargs; " \
	200	"run addip addtty addmtd addfb addeth addmisc;" \
	201	"run loaduimage; " \
	202	"bootm ${loadaddr}\0" \
	203	"net_nfs=run load_k; " \
	204	"run nfsargs; " \
	205	"run addip addtty addmtd addfb addeth addmisc;" \
	206	"bootm ${loadaddr}\0" \
	207	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	208	"nfsroot=${serverip}:${rootpath}\0" \
4a8c3f69	209	"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \
f89a8b6a SB	210	"uboot_addr=0x80000\0" \
	211	"update=nandecc sw;nand erase ${uboot_addr} 100000;" \
	212	"nand write ${loadaddr} ${uboot_addr} 80000\0" \
	213	"updatemlo=nandecc hw;nand erase 0 20000;" \
	214	"nand write ${loadaddr} 0 20000\0" \
	215	"upd=if run load;then echo Updating u-boot;if run update;" \
	216	"then echo U-Boot updated;" \
	217	"else echo Error updating u-boot !;" \
	218	"echo Board without bootloader !!;" \
	219	"fi;" \
	220	"else echo U-Boot not downloaded..exiting;fi\0" \
	221	"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
	222	"bootscript=echo Running bootscript from mmc ...; " \
	223	"source ${loadaddr}\0" \
	224	"nandargs=setenv bootargs ubi.mtd=7 " \
	225	"root=ubi0:rootfs rootfstype=ubifs\0" \
	226	"nandboot=echo Booting from nand ...; " \
	227	"run nandargs; " \
	228	"ubi part nand0,4;" \
	229	"ubi readvol ${loadaddr} kernel;" \
e47c9e86	230	"run addtty addmtd addfb addeth addmisc;" \
f89a8b6a	231	"bootm ${loadaddr}\0" \
8f1fae26 SB	232	"preboot=ubi part nand0,7;" \
	233	"ubi readvol ${loadaddr} splash;" \
	234	"bmp display ${loadaddr};" \
	235	"gpio set 55\0" \
e47c9e86 SB	236	"swupdate_args=setenv bootargs root=/dev/ram " \
	237	"quiet loglevel=1 " \
	238	"consoleblank=0 ${swupdate_misc}\0" \
f89a8b6a SB	239	"swupdate=echo Running Sw-Update...;" \
	240	"if printenv mtdparts;then echo Starting SwUpdate...; " \
	241	"else mtdparts default;fi; " \
	242	"ubi part nand0,5;" \
	243	"ubi readvol 0x82000000 kernel_recovery;" \
e47c9e86 SB	244	"ubi part nand0,6;" \
e47c9e86 SB	245	"ubi readvol 0x84000000 fs_recovery;" \
f89a8b6a SB	246	"run swupdate_args; " \
	247	"setenv bootargs ${bootargs} " \
	248	"${mtdparts} " \
	249	"vram=6M omapfb.vram=1:2M,2:2M,3:2M " \
	250	"omapdss.def_disp=lcd;" \
a5d64dbf SB	251	"bootm 0x82000000 0x84000000\0" \
	252	"bootcmd=mmc rescan;if fatload mmc 0 82000000 loadbootscr.scr;" \
	253	"then source 82000000;else run nandboot;fi\0"
4ab779cb IY	254
4ab779cb IY	255	#define CONFIG_AUTO_COMPLETE
48a4ee50 DZ	256	#define CONFIG_CMDLINE_EDITING
48a4ee50 DZ	257
4ab779cb IY	258	/*
	259	* Miscellaneous configurable options
	260	*/
4ab779cb	261	#define CONFIG_SYS_LONGHELP /* undef to save memory */
992a27d5	262	#define CONFIG_SYS_CBSIZE 1024/* Console I/O Buffer Size */
4ab779cb IY	263	/* Print Buffer Size */
	264	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	265	sizeof(CONFIG_SYS_PROMPT) + 16)
	266	#define CONFIG_SYS_MAXARGS 16 /* max number of command */
	267	/* args */
	268	/* Boot Argument Buffer Size */
	269	#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
	270	/* memtest works on */
	271	#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
	272	#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
	273	0x01F00000) /* 31MB */
	274
	275	#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
	276	/* address */
8f1fae26	277	#define CONFIG_PREBOOT
4ab779cb IY	278
	279	/*
	280	* AM3517 has 12 GP timers, they can be driven by the system clock
	281	* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
	282	* This rate is divided by a local divisor.
	283	*/
	284	#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
	285	#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
4ab779cb	286
4ab779cb IY	287	/*
	288	* Physical Memory Map
	289	*/
	290	#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
	291	#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
4ab779cb IY	292	#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
	293
	294	/*
	295	* FLASH and environment organization
	296	*/
	297
	298	/* ** PISMO SUPPORT * */
62321e2f SB	299	#define CONFIG_NAND
62321e2f SB	300	#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
4ab779cb	301	#define CONFIG_NAND_OMAP_GPMC
62321e2f	302	#define CONFIG_NAND_OMAP_GPMC_PREFETCH
4ab779cb	303	#define CONFIG_ENV_IS_IN_NAND
f89a8b6a	304	#define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */
4ab779cb	305
f89a8b6a	306	/* Redundant Environment */
4ab779cb IY	307	#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
	308	#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
	309	#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
f89a8b6a SB	310	#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
	311	2 * CONFIG_SYS_ENV_SECT_SIZE)
	312	#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
4ab779cb IY	313
	314	/* Flash banks JFFS2 should use */
	315	#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
	316	CONFIG_SYS_MAX_NAND_DEVICE)
	317	#define CONFIG_SYS_JFFS2_MEM_NAND
	318	/* use flash_info[2] */
	319	#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
	320	#define CONFIG_SYS_JFFS2_NUM_BANKS 1
	321
	322	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	323	#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
	324	#define CONFIG_SYS_INIT_RAM_SIZE 0x800
	325	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	326	CONFIG_SYS_INIT_RAM_SIZE - \
	327	GENERATED_GBL_DATA_SIZE)
	328
	329	/* Defines for SPL */
47f7bcae	330	#define CONFIG_SPL_FRAMEWORK
d7cb93b2	331	#define CONFIG_SPL_BOARD_INIT
4ab779cb	332	#define CONFIG_SPL_NAND_SIMPLE
4ab779cb IY	333
	334	#define CONFIG_SPL_LIBCOMMON_SUPPORT
	335	#define CONFIG_SPL_LIBDISK_SUPPORT
	336	#define CONFIG_SPL_I2C_SUPPORT
	337	#define CONFIG_SPL_MMC_SUPPORT
	338	#define CONFIG_SPL_FAT_SUPPORT
	339	#define CONFIG_SPL_LIBGENERIC_SUPPORT
	340	#define CONFIG_SPL_SERIAL_SUPPORT
	341	#define CONFIG_SPL_POWER_SUPPORT
	342	#define CONFIG_SPL_NAND_SUPPORT
6f2f01b9 SW	343	#define CONFIG_SPL_NAND_BASE
	344	#define CONFIG_SPL_NAND_DRIVERS
	345	#define CONFIG_SPL_NAND_ECC
4ab779cb IY	346	#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
	347
	348	#define CONFIG_SPL_TEXT_BASE 0x40200000 /CONFIG_SYS_SRAM_START/
e0820ccc	349	#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
4ab779cb IY	350	#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
	351
	352	/* move malloc and bss high to prevent clashing with the main image */
	353	#define CONFIG_SYS_SPL_MALLOC_START 0x8f000000
	354	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
	355	#define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */
	356	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
	357
	358	#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
e2ccdf89	359	#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
205b4f33	360	#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
4ab779cb IY	361
	362	/* NAND boot config */
	363	#define CONFIG_SYS_NAND_PAGE_COUNT 64
	364	#define CONFIG_SYS_NAND_PAGE_SIZE 2048
	365	#define CONFIG_SYS_NAND_OOBSIZE 64
	366	#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
	367	#define CONFIG_SYS_NAND_5_ADDR_CYCLE
	368	#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
	369	#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\
	370	48, 49, 50, 51, 52, 53, 54, 55,\
	371	56, 57, 58, 59, 60, 61, 62, 63}
	372	#define CONFIG_SYS_NAND_ECCSIZE 256
	373	#define CONFIG_SYS_NAND_ECCBYTES 3
3f719069	374	#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW
92671102	375	#define CONFIG_SPL_NAND_SOFTECC
4ab779cb	376
4ab779cb IY	377	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
	378
	379	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
	380
	381	/*
	382	* ethernet support
	383	*
	384	*/
	385	#if defined(CONFIG_CMD_NET)
	386	#define CONFIG_DRIVER_TI_EMAC
	387	#define CONFIG_DRIVER_TI_EMAC_USE_RMII
	388	#define CONFIG_MII
4ab779cb IY	389	#define CONFIG_BOOTP_DNS
	390	#define CONFIG_BOOTP_DNS2
	391	#define CONFIG_BOOTP_SEND_HOSTNAME
	392	#define CONFIG_NET_RETRY_COUNT 10
	393	#endif
	394
8f1fae26 SB	395	#define CONFIG_VIDEO
	396	#define CONFIG_CFB_CONSOLE
	397	#define CONFIG_VGA_AS_SINGLE_DEVICE
	398	#define CONFIG_SPLASH_SCREEN
	399	#define CONFIG_VIDEO_BMP_RLE8
	400	#define CONFIG_CMD_BMP
	401	#define CONFIG_VIDEO_OMAP3
	402	#define CONFIG_SYS_CONSOLE_IS_IN_ENV
	403
4ab779cb	404	#endif /* __CONFIG_H */