[u-boot.git] / include / tsi108.h

/*****************************************************************************
 * (C) Copyright 2003;  Tundra Semiconductor Corp.
 * (C) Copyright 2006;  Freescale Semiconductor Corp.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 *****************************************************************************/

/*
 * FILENAME: tsi108.h
 *
 * Originator: Alex Bounine
 *
 * DESCRIPTION:
 * Common definitions for the Tundra Tsi108 bridge chip
 *
 */

#ifndef _TSI108_H_
#define _TSI108_H_

#define TSI108_HLP_REG_OFFSET	(0x0000)
#define TSI108_PCI_REG_OFFSET	(0x1000)
#define TSI108_CLK_REG_OFFSET	(0x2000)
#define TSI108_PB_REG_OFFSET	(0x3000)
#define TSI108_SD_REG_OFFSET	(0x4000)
#define TSI108_MPIC_REG_OFFSET	(0x7400)

#define PB_ID			(0x000)
#define PB_RSR			(0x004)
#define PB_BUS_MS_SELECT	(0x008)
#define PB_ISR			(0x00C)
#define PB_ARB_CTRL		(0x018)
#define PB_PVT_CTRL2		(0x034)
#define PB_SCR			(0x400)
#define PB_ERRCS		(0x404)
#define PB_AERR			(0x408)
#define PB_REG_BAR		(0x410)
#define PB_OCN_BAR1		(0x414)
#define PB_OCN_BAR2		(0x418)
#define PB_SDRAM_BAR1		(0x41C)
#define PB_SDRAM_BAR2		(0x420)
#define PB_MCR			(0xC00)
#define PB_MCMD			(0xC04)

#define HLP_B0_ADDR		(0x000)
#define HLP_B1_ADDR		(0x010)
#define HLP_B2_ADDR		(0x020)
#define HLP_B3_ADDR		(0x030)

#define HLP_B0_MASK		(0x004)
#define HLP_B1_MASK		(0x014)
#define HLP_B2_MASK		(0x024)
#define HLP_B3_MASK		(0x034)

#define HLP_B0_CTRL0		(0x008)
#define HLP_B1_CTRL0		(0x018)
#define HLP_B2_CTRL0		(0x028)
#define HLP_B3_CTRL0		(0x038)

#define HLP_B0_CTRL1		(0x00C)
#define HLP_B1_CTRL1		(0x01C)
#define HLP_B2_CTRL1		(0x02C)
#define HLP_B3_CTRL1		(0x03C)

#define PCI_CSR			(0x004)
#define PCI_P2O_BAR0		(0x010)
#define PCI_P2O_BAR0_UPPER	(0x014)
#define PCI_P2O_BAR2		(0x018)
#define PCI_P2O_BAR2_UPPER	(0x01C)
#define PCI_P2O_BAR3		(0x020)
#define PCI_P2O_BAR3_UPPER	(0x024)

#define PCI_MISC_CSR		(0x040)
#define PCI_P2O_PAGE_SIZES	(0x04C)

#define PCI_PCIX_STAT		(0x0F4)

#define PCI_IRP_STAT		(0x184)

#define PCI_PFAB_BAR0		(0x204)
#define PCI_PFAB_BAR0_UPPER	(0x208)
#define PCI_PFAB_IO		(0x20C)
#define PCI_PFAB_IO_UPPER	(0x210)

#define PCI_PFAB_MEM32		(0x214)
#define PCI_PFAB_MEM32_REMAP	(0x218)
#define PCI_PFAB_MEM32_MASK	(0x21C)

#define CG_PLL0_CTRL0		(0x210)
#define CG_PLL0_CTRL1		(0x214)
#define CG_PLL1_CTRL0		(0x220)
#define CG_PLL1_CTRL1		(0x224)
#define CG_PWRUP_STATUS		(0x234)

#define MPIC_CSR(n) (0x30C + (n * 0x40))

#define SD_CTRL			(0x000)
#define SD_STATUS		(0x004)
#define SD_TIMING		(0x008)
#define SD_REFRESH		(0x00C)
#define SD_INT_STATUS		(0x010)
#define SD_INT_ENABLE		(0x014)
#define SD_INT_SET		(0x018)
#define SD_D0_CTRL		(0x020)
#define SD_D1_CTRL		(0x024)
#define SD_D0_BAR		(0x028)
#define SD_D1_BAR		(0x02C)
#define SD_ECC_CTRL		(0x040)
#define SD_DLL_STATUS		(0x250)

#define TS_SD_CTRL_ENABLE	(1 << 31)

#define PB_ERRCS_ES		(1 << 1)
#define PB_ISR_PBS_RD_ERR	(1 << 8)
#define PCI_IRP_STAT_P_CSR	(1 << 23)

/*
 * I2C : Register address offset definitions
 */
#define I2C_CNTRL1		(0x00000000)
#define I2C_CNTRL2		(0x00000004)
#define I2C_RD_DATA		(0x00000008)
#define I2C_TX_DATA		(0x0000000c)

/*
 * I2C : Register Bit Masks and Reset Values
 * definitions for every register
 */

/* I2C_CNTRL1 : Reset Value */
#define I2C_CNTRL1_RESET_VALUE				(0x0000000a)

/* I2C_CNTRL1 : Register Bits Masks Definitions */
#define I2C_CNTRL1_DEVCODE				(0x0000000f)
#define I2C_CNTRL1_PAGE					(0x00000700)
#define I2C_CNTRL1_BYTADDR				(0x00ff0000)
#define I2C_CNTRL1_I2CWRITE				(0x01000000)

/* I2C_CNTRL1 : Read/Write Bit Mask Definition */
#define I2C_CNTRL1_RWMASK				(0x01ff070f)

/* I2C_CNTRL1 : Unused/Reserved bits Definition */
#define I2C_CNTRL1_RESERVED				(0xfe00f8f0)

/* I2C_CNTRL2 : Reset Value */
#define I2C_CNTRL2_RESET_VALUE				(0x00000000)

/* I2C_CNTRL2 : Register Bits Masks Definitions */
#define I2C_CNTRL2_SIZE					(0x00000003)
#define I2C_CNTRL2_LANE					(0x0000000c)
#define I2C_CNTRL2_MULTIBYTE				(0x00000010)
#define I2C_CNTRL2_START				(0x00000100)
#define I2C_CNTRL2_WR_STATUS				(0x00010000)
#define I2C_CNTRL2_RD_STATUS				(0x00020000)
#define I2C_CNTRL2_I2C_TO_ERR				(0x04000000)
#define I2C_CNTRL2_I2C_CFGERR				(0x08000000)
#define I2C_CNTRL2_I2C_CMPLT				(0x10000000)

/* I2C_CNTRL2 : Read/Write Bit Mask Definition */
#define I2C_CNTRL2_RWMASK				(0x0000011f)

/* I2C_CNTRL2 : Unused/Reserved bits Definition */
#define I2C_CNTRL2_RESERVED				(0xe3fcfee0)

/* I2C_RD_DATA : Reset Value */
#define I2C_RD_DATA_RESET_VALUE				(0x00000000)

/* I2C_RD_DATA : Register Bits Masks Definitions */
#define I2C_RD_DATA_RBYTE0				(0x000000ff)
#define I2C_RD_DATA_RBYTE1				(0x0000ff00)
#define I2C_RD_DATA_RBYTE2				(0x00ff0000)
#define I2C_RD_DATA_RBYTE3				(0xff000000)

/* I2C_RD_DATA : Read/Write Bit Mask Definition */
#define I2C_RD_DATA_RWMASK				(0x00000000)

/* I2C_RD_DATA : Unused/Reserved bits Definition */
#define I2C_RD_DATA_RESERVED				(0x00000000)

/* I2C_TX_DATA : Reset Value */
#define I2C_TX_DATA_RESET_VALUE				(0x00000000)

/* I2C_TX_DATA : Register Bits Masks Definitions */
#define I2C_TX_DATA_TBYTE0				(0x000000ff)
#define I2C_TX_DATA_TBYTE1				(0x0000ff00)
#define I2C_TX_DATA_TBYTE2				(0x00ff0000)
#define I2C_TX_DATA_TBYTE3				(0xff000000)

/* I2C_TX_DATA : Read/Write Bit Mask Definition */
#define I2C_TX_DATA_RWMASK				(0xffffffff)

/* I2C_TX_DATA : Unused/Reserved bits Definition */
#define I2C_TX_DATA_RESERVED				(0x00000000)

#define TSI108_I2C_OFFSET	0x7000	/* offset for general use I2C channel */
#define TSI108_I2C_SDRAM_OFFSET	0x4400	/* offset for SPD I2C channel */

#define I2C_EEPROM_DEVCODE	0xA	/* standard I2C EEPROM device code */

/* I2C status codes */

#define TSI108_I2C_SUCCESS	0
#define TSI108_I2C_PARAM_ERR	1
#define TSI108_I2C_TIMEOUT_ERR	2
#define TSI108_I2C_IF_BUSY	3
#define TSI108_I2C_IF_ERROR	4

#endif		/* _TSI108_H_ */
Commit	Line	Data
78aa0c34	1	/*****************************************************************************
	2	* (C) Copyright 2003; Tundra Semiconductor Corp.
	3	* (C) Copyright 2006; Freescale Semiconductor Corp.
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
78aa0c34	6	*****************************************************************************/
	7
	8	/*
	9	* FILENAME: tsi108.h
	10	*
	11	* Originator: Alex Bounine
	12	*
	13	* DESCRIPTION:
	14	* Common definitions for the Tundra Tsi108 bridge chip
	15	*
	16	*/
	17
	18	#ifndef _TSI108_H_
	19	#define _TSI108_H_
	20
ee311214	21	#define TSI108_HLP_REG_OFFSET (0x0000)
	22	#define TSI108_PCI_REG_OFFSET (0x1000)
	23	#define TSI108_CLK_REG_OFFSET (0x2000)
	24	#define TSI108_PB_REG_OFFSET (0x3000)
	25	#define TSI108_SD_REG_OFFSET (0x4000)
	26	#define TSI108_MPIC_REG_OFFSET (0x7400)
	27
	28	#define PB_ID (0x000)
	29	#define PB_RSR (0x004)
	30	#define PB_BUS_MS_SELECT (0x008)
	31	#define PB_ISR (0x00C)
	32	#define PB_ARB_CTRL (0x018)
	33	#define PB_PVT_CTRL2 (0x034)
	34	#define PB_SCR (0x400)
	35	#define PB_ERRCS (0x404)
	36	#define PB_AERR (0x408)
	37	#define PB_REG_BAR (0x410)
	38	#define PB_OCN_BAR1 (0x414)
	39	#define PB_OCN_BAR2 (0x418)
	40	#define PB_SDRAM_BAR1 (0x41C)
	41	#define PB_SDRAM_BAR2 (0x420)
	42	#define PB_MCR (0xC00)
	43	#define PB_MCMD (0xC04)
	44
	45	#define HLP_B0_ADDR (0x000)
	46	#define HLP_B1_ADDR (0x010)
	47	#define HLP_B2_ADDR (0x020)
	48	#define HLP_B3_ADDR (0x030)
	49
	50	#define HLP_B0_MASK (0x004)
	51	#define HLP_B1_MASK (0x014)
	52	#define HLP_B2_MASK (0x024)
	53	#define HLP_B3_MASK (0x034)
	54
	55	#define HLP_B0_CTRL0 (0x008)
	56	#define HLP_B1_CTRL0 (0x018)
	57	#define HLP_B2_CTRL0 (0x028)
	58	#define HLP_B3_CTRL0 (0x038)
	59
	60	#define HLP_B0_CTRL1 (0x00C)
	61	#define HLP_B1_CTRL1 (0x01C)
	62	#define HLP_B2_CTRL1 (0x02C)
	63	#define HLP_B3_CTRL1 (0x03C)
	64
	65	#define PCI_CSR (0x004)
	66	#define PCI_P2O_BAR0 (0x010)
	67	#define PCI_P2O_BAR0_UPPER (0x014)
	68	#define PCI_P2O_BAR2 (0x018)
	69	#define PCI_P2O_BAR2_UPPER (0x01C)
	70	#define PCI_P2O_BAR3 (0x020)
	71	#define PCI_P2O_BAR3_UPPER (0x024)
	72
	73	#define PCI_MISC_CSR (0x040)
	74	#define PCI_P2O_PAGE_SIZES (0x04C)
	75
	76	#define PCI_PCIX_STAT (0x0F4)
	77
	78	#define PCI_IRP_STAT (0x184)
	79
	80	#define PCI_PFAB_BAR0 (0x204)
	81	#define PCI_PFAB_BAR0_UPPER (0x208)
	82	#define PCI_PFAB_IO (0x20C)
	83	#define PCI_PFAB_IO_UPPER (0x210)
	84
85	#define PCI_PFAB_MEM32 (0x214)
86	#define PCI_PFAB_MEM32_REMAP (0x218)
87	#define PCI_PFAB_MEM32_MASK (0x21C)
88
89	#define CG_PLL0_CTRL0 (0x210)
90	#define CG_PLL0_CTRL1 (0x214)
91	#define CG_PLL1_CTRL0 (0x220)
92	#define CG_PLL1_CTRL1 (0x224)
93	#define CG_PWRUP_STATUS (0x234)
78aa0c34	94
	95	#define MPIC_CSR(n) (0x30C + (n * 0x40))
	96
ee311214	97	#define SD_CTRL (0x000)
	98	#define SD_STATUS (0x004)
	99	#define SD_TIMING (0x008)
	100	#define SD_REFRESH (0x00C)
	101	#define SD_INT_STATUS (0x010)
	102	#define SD_INT_ENABLE (0x014)
	103	#define SD_INT_SET (0x018)
	104	#define SD_D0_CTRL (0x020)
	105	#define SD_D1_CTRL (0x024)
	106	#define SD_D0_BAR (0x028)
	107	#define SD_D1_BAR (0x02C)
	108	#define SD_ECC_CTRL (0x040)
	109	#define SD_DLL_STATUS (0x250)
	110
	111	#define TS_SD_CTRL_ENABLE (1 << 31)
	112
	113	#define PB_ERRCS_ES (1 << 1)
	114	#define PB_ISR_PBS_RD_ERR (1 << 8)
	115	#define PCI_IRP_STAT_P_CSR (1 << 23)
	116
	117	/*
78aa0c34	118	* I2C : Register address offset definitions
78aa0c34	119	*/
ee311214	120	#define I2C_CNTRL1 (0x00000000)
	121	#define I2C_CNTRL2 (0x00000004)
	122	#define I2C_RD_DATA (0x00000008)
	123	#define I2C_TX_DATA (0x0000000c)
78aa0c34	124
	125	/*
	126	* I2C : Register Bit Masks and Reset Values
ee311214	127	* definitions for every register
78aa0c34	128	*/
	129
	130	/* I2C_CNTRL1 : Reset Value */
ee311214	131	#define I2C_CNTRL1_RESET_VALUE (0x0000000a)
78aa0c34	132
78aa0c34	133	/* I2C_CNTRL1 : Register Bits Masks Definitions */
ee311214	134	#define I2C_CNTRL1_DEVCODE (0x0000000f)
	135	#define I2C_CNTRL1_PAGE (0x00000700)
	136	#define I2C_CNTRL1_BYTADDR (0x00ff0000)
	137	#define I2C_CNTRL1_I2CWRITE (0x01000000)
78aa0c34	138
78aa0c34	139	/* I2C_CNTRL1 : Read/Write Bit Mask Definition */
ee311214	140	#define I2C_CNTRL1_RWMASK (0x01ff070f)
78aa0c34	141
78aa0c34	142	/* I2C_CNTRL1 : Unused/Reserved bits Definition */
ee311214	143	#define I2C_CNTRL1_RESERVED (0xfe00f8f0)
78aa0c34	144
78aa0c34	145	/* I2C_CNTRL2 : Reset Value */
ee311214	146	#define I2C_CNTRL2_RESET_VALUE (0x00000000)
78aa0c34	147
78aa0c34	148	/* I2C_CNTRL2 : Register Bits Masks Definitions */
ee311214	149	#define I2C_CNTRL2_SIZE (0x00000003)
	150	#define I2C_CNTRL2_LANE (0x0000000c)
	151	#define I2C_CNTRL2_MULTIBYTE (0x00000010)
	152	#define I2C_CNTRL2_START (0x00000100)
	153	#define I2C_CNTRL2_WR_STATUS (0x00010000)
	154	#define I2C_CNTRL2_RD_STATUS (0x00020000)
	155	#define I2C_CNTRL2_I2C_TO_ERR (0x04000000)
	156	#define I2C_CNTRL2_I2C_CFGERR (0x08000000)
	157	#define I2C_CNTRL2_I2C_CMPLT (0x10000000)
78aa0c34	158
78aa0c34	159	/* I2C_CNTRL2 : Read/Write Bit Mask Definition */
ee311214	160	#define I2C_CNTRL2_RWMASK (0x0000011f)
78aa0c34	161
78aa0c34	162	/* I2C_CNTRL2 : Unused/Reserved bits Definition */
ee311214	163	#define I2C_CNTRL2_RESERVED (0xe3fcfee0)
78aa0c34	164
78aa0c34	165	/* I2C_RD_DATA : Reset Value */
ee311214	166	#define I2C_RD_DATA_RESET_VALUE (0x00000000)
78aa0c34	167
78aa0c34	168	/* I2C_RD_DATA : Register Bits Masks Definitions */
ee311214	169	#define I2C_RD_DATA_RBYTE0 (0x000000ff)
	170	#define I2C_RD_DATA_RBYTE1 (0x0000ff00)
	171	#define I2C_RD_DATA_RBYTE2 (0x00ff0000)
	172	#define I2C_RD_DATA_RBYTE3 (0xff000000)
78aa0c34	173
78aa0c34	174	/* I2C_RD_DATA : Read/Write Bit Mask Definition */
ee311214	175	#define I2C_RD_DATA_RWMASK (0x00000000)
78aa0c34	176
78aa0c34	177	/* I2C_RD_DATA : Unused/Reserved bits Definition */
ee311214	178	#define I2C_RD_DATA_RESERVED (0x00000000)
78aa0c34	179
78aa0c34	180	/* I2C_TX_DATA : Reset Value */
ee311214	181	#define I2C_TX_DATA_RESET_VALUE (0x00000000)
78aa0c34	182
78aa0c34	183	/* I2C_TX_DATA : Register Bits Masks Definitions */
ee311214	184	#define I2C_TX_DATA_TBYTE0 (0x000000ff)
	185	#define I2C_TX_DATA_TBYTE1 (0x0000ff00)
	186	#define I2C_TX_DATA_TBYTE2 (0x00ff0000)
	187	#define I2C_TX_DATA_TBYTE3 (0xff000000)
78aa0c34	188
78aa0c34	189	/* I2C_TX_DATA : Read/Write Bit Mask Definition */
ee311214	190	#define I2C_TX_DATA_RWMASK (0xffffffff)
78aa0c34	191
78aa0c34	192	/* I2C_TX_DATA : Unused/Reserved bits Definition */
ee311214	193	#define I2C_TX_DATA_RESERVED (0x00000000)
78aa0c34	194
ee311214	195	#define TSI108_I2C_OFFSET 0x7000 /* offset for general use I2C channel */
ee311214	196	#define TSI108_I2C_SDRAM_OFFSET 0x4400 /* offset for SPD I2C channel */
78aa0c34	197
ee311214	198	#define I2C_EEPROM_DEVCODE 0xA /* standard I2C EEPROM device code */
78aa0c34	199
	200	/* I2C status codes */
	201
ee311214	202	#define TSI108_I2C_SUCCESS 0
	203	#define TSI108_I2C_PARAM_ERR 1
	204	#define TSI108_I2C_TIMEOUT_ERR 2
	205	#define TSI108_I2C_IF_BUSY 3
	206	#define TSI108_I2C_IF_ERROR 4
78aa0c34	207
78aa0c34	208	#endif /* _TSI108_H_ */