[u-boot.git] / drivers / timer / altera_timer.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2000-2002
 * Wolfgang Denk, DENX Software Engineering, [email protected].
 *
 * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
 * Scott McNutt <[email protected]>
 */

#include <common.h>
#include <dm.h>
#include <errno.h>
#include <timer.h>
#include <asm/io.h>
#include <linux/bitops.h>

/* control register */
#define ALTERA_TIMER_CONT	BIT(1)	/* Continuous mode */
#define ALTERA_TIMER_START	BIT(2)	/* Start timer */
#define ALTERA_TIMER_STOP	BIT(3)	/* Stop timer */

struct altera_timer_regs {
	u32	status;		/* Timer status reg */
	u32	control;	/* Timer control reg */
	u32	periodl;	/* Timeout period low */
	u32	periodh;	/* Timeout period high */
	u32	snapl;		/* Snapshot low */
	u32	snaph;		/* Snapshot high */
};

struct altera_timer_platdata {
	struct altera_timer_regs *regs;
};

static u64 altera_timer_get_count(struct udevice *dev)
{
	struct altera_timer_platdata *plat = dev->platdata;
	struct altera_timer_regs *const regs = plat->regs;
	u32 val;

	/* Trigger update */
	writel(0x0, &regs->snapl);

	/* Read timer value */
	val = readl(&regs->snapl) & 0xffff;
	val |= (readl(&regs->snaph) & 0xffff) << 16;
	return timer_conv_64(~val);
}

static int altera_timer_probe(struct udevice *dev)
{
	struct altera_timer_platdata *plat = dev->platdata;
	struct altera_timer_regs *const regs = plat->regs;

	writel(0, &regs->status);
	writel(0, &regs->control);
	writel(ALTERA_TIMER_STOP, &regs->control);

	writel(0xffff, &regs->periodl);
	writel(0xffff, &regs->periodh);
	writel(ALTERA_TIMER_CONT | ALTERA_TIMER_START, &regs->control);

	return 0;
}

static int altera_timer_ofdata_to_platdata(struct udevice *dev)
{
	struct altera_timer_platdata *plat = dev_get_platdata(dev);

	plat->regs = map_physmem(dev_read_addr(dev),
				 sizeof(struct altera_timer_regs),
				 MAP_NOCACHE);

	return 0;
}

static const struct timer_ops altera_timer_ops = {
	.get_count = altera_timer_get_count,
};

static const struct udevice_id altera_timer_ids[] = {
	{ .compatible = "altr,timer-1.0" },
	{}
};

U_BOOT_DRIVER(altera_timer) = {
	.name	= "altera_timer",
	.id	= UCLASS_TIMER,
	.of_match = altera_timer_ids,
	.ofdata_to_platdata = altera_timer_ofdata_to_platdata,
	.platdata_auto_alloc_size = sizeof(struct altera_timer_platdata),
	.probe = altera_timer_probe,
	.ops	= &altera_timer_ops,
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
a54915d8 TC	2	/*
	3	* (C) Copyright 2000-2002
	4	* Wolfgang Denk, DENX Software Engineering, [email protected].
	5	*
	6	* (C) Copyright 2004, Psyent Corporation <www.psyent.com>
	7	* Scott McNutt <[email protected]>
a54915d8 TC	8	*/
	9
	10	#include <common.h>
	11	#include <dm.h>
	12	#include <errno.h>
	13	#include <timer.h>
	14	#include <asm/io.h>
cd93d625	15	#include <linux/bitops.h>
a54915d8	16
1235e5a5 TC	17	/* control register */
	18	#define ALTERA_TIMER_CONT BIT(1) /* Continuous mode */
	19	#define ALTERA_TIMER_START BIT(2) /* Start timer */
	20	#define ALTERA_TIMER_STOP BIT(3) /* Stop timer */
	21
a54915d8 TC	22	struct altera_timer_regs {
	23	u32 status; /* Timer status reg */
	24	u32 control; /* Timer control reg */
	25	u32 periodl; /* Timeout period low */
	26	u32 periodh; /* Timeout period high */
	27	u32 snapl; /* Snapshot low */
	28	u32 snaph; /* Snapshot high */
	29	};
	30
	31	struct altera_timer_platdata {
	32	struct altera_timer_regs *regs;
a54915d8 TC	33	};
a54915d8 TC	34
8af7bb91	35	static u64 altera_timer_get_count(struct udevice *dev)
a54915d8 TC	36	{
	37	struct altera_timer_platdata *plat = dev->platdata;
	38	struct altera_timer_regs *const regs = plat->regs;
	39	u32 val;
	40
	41	/* Trigger update */
	42	writel(0x0, &regs->snapl);
	43
	44	/* Read timer value */
	45	val = readl(&regs->snapl) & 0xffff;
	46	val \|= (readl(&regs->snaph) & 0xffff) << 16;
8af7bb91	47	return timer_conv_64(~val);
a54915d8 TC	48	}
	49
	50	static int altera_timer_probe(struct udevice *dev)
	51	{
a54915d8 TC	52	struct altera_timer_platdata *plat = dev->platdata;
	53	struct altera_timer_regs *const regs = plat->regs;
	54
a54915d8 TC	55	writel(0, &regs->status);
	56	writel(0, &regs->control);
	57	writel(ALTERA_TIMER_STOP, &regs->control);
	58
	59	writel(0xffff, &regs->periodl);
	60	writel(0xffff, &regs->periodh);
	61	writel(ALTERA_TIMER_CONT \| ALTERA_TIMER_START, &regs->control);
	62
	63	return 0;
	64	}
	65
	66	static int altera_timer_ofdata_to_platdata(struct udevice *dev)
	67	{
	68	struct altera_timer_platdata *plat = dev_get_platdata(dev);
	69
2548493a	70	plat->regs = map_physmem(dev_read_addr(dev),
4c26ec17 TC	71	sizeof(struct altera_timer_regs),
4c26ec17 TC	72	MAP_NOCACHE);
a54915d8 TC	73
	74	return 0;
	75	}
	76
	77	static const struct timer_ops altera_timer_ops = {
	78	.get_count = altera_timer_get_count,
	79	};
	80
	81	static const struct udevice_id altera_timer_ids[] = {
1235e5a5 TC	82	{ .compatible = "altr,timer-1.0" },
1235e5a5 TC	83	{}
a54915d8 TC	84	};
	85
	86	U_BOOT_DRIVER(altera_timer) = {
	87	.name = "altera_timer",
	88	.id = UCLASS_TIMER,
	89	.of_match = altera_timer_ids,
	90	.ofdata_to_platdata = altera_timer_ofdata_to_platdata,
	91	.platdata_auto_alloc_size = sizeof(struct altera_timer_platdata),
	92	.probe = altera_timer_probe,
	93	.ops = &altera_timer_ops,
a54915d8	94	};