[u-boot.git] / drivers / net / sunxi_emac.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * sunxi_emac.c -- Allwinner A10 ethernet driver
 *
 * (C) Copyright 2012, Stefan Roese <[email protected]>
 */

#include <common.h>
#include <clk.h>
#include <dm.h>
#include <log.h>
#include <dm/device_compat.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <malloc.h>
#include <miiphy.h>
#include <net.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>

/* EMAC register  */
struct emac_regs {
	u32 ctl;	/* 0x00 */
	u32 tx_mode;	/* 0x04 */
	u32 tx_flow;	/* 0x08 */
	u32 tx_ctl0;	/* 0x0c */
	u32 tx_ctl1;	/* 0x10 */
	u32 tx_ins;	/* 0x14 */
	u32 tx_pl0;	/* 0x18 */
	u32 tx_pl1;	/* 0x1c */
	u32 tx_sta;	/* 0x20 */
	u32 tx_io_data;	/* 0x24 */
	u32 tx_io_data1;/* 0x28 */
	u32 tx_tsvl0;	/* 0x2c */
	u32 tx_tsvh0;	/* 0x30 */
	u32 tx_tsvl1;	/* 0x34 */
	u32 tx_tsvh1;	/* 0x38 */
	u32 rx_ctl;	/* 0x3c */
	u32 rx_hash0;	/* 0x40 */
	u32 rx_hash1;	/* 0x44 */
	u32 rx_sta;	/* 0x48 */
	u32 rx_io_data;	/* 0x4c */
	u32 rx_fbc;	/* 0x50 */
	u32 int_ctl;	/* 0x54 */
	u32 int_sta;	/* 0x58 */
	u32 mac_ctl0;	/* 0x5c */
	u32 mac_ctl1;	/* 0x60 */
	u32 mac_ipgt;	/* 0x64 */
	u32 mac_ipgr;	/* 0x68 */
	u32 mac_clrt;	/* 0x6c */
	u32 mac_maxf;	/* 0x70 */
	u32 mac_supp;	/* 0x74 */
	u32 mac_test;	/* 0x78 */
	u32 mac_mcfg;	/* 0x7c */
	u32 mac_mcmd;	/* 0x80 */
	u32 mac_madr;	/* 0x84 */
	u32 mac_mwtd;	/* 0x88 */
	u32 mac_mrdd;	/* 0x8c */
	u32 mac_mind;	/* 0x90 */
	u32 mac_ssrr;	/* 0x94 */
	u32 mac_a0;	/* 0x98 */
	u32 mac_a1;	/* 0x9c */
};

/* SRAMC register  */
struct sunxi_sramc_regs {
	u32 ctrl0;
	u32 ctrl1;
};

/* 0: Disable       1: Aborted frame enable(default) */
#define EMAC_TX_AB_M		(0x1 << 0)
/* 0: CPU           1: DMA(default) */
#define EMAC_TX_TM		(0x1 << 1)

#define EMAC_TX_SETUP		(0)

/* 0: DRQ asserted  1: DRQ automatically(default) */
#define EMAC_RX_DRQ_MODE	(0x1 << 1)
/* 0: CPU           1: DMA(default) */
#define EMAC_RX_TM		(0x1 << 2)
/* 0: Normal(default)        1: Pass all Frames */
#define EMAC_RX_PA		(0x1 << 4)
/* 0: Normal(default)        1: Pass Control Frames */
#define EMAC_RX_PCF		(0x1 << 5)
/* 0: Normal(default)        1: Pass Frames with CRC Error */
#define EMAC_RX_PCRCE		(0x1 << 6)
/* 0: Normal(default)        1: Pass Frames with Length Error */
#define EMAC_RX_PLE		(0x1 << 7)
/* 0: Normal                 1: Pass Frames length out of range(default) */
#define EMAC_RX_POR		(0x1 << 8)
/* 0: Not accept             1: Accept unicast Packets(default) */
#define EMAC_RX_UCAD		(0x1 << 16)
/* 0: Normal(default)        1: DA Filtering */
#define EMAC_RX_DAF		(0x1 << 17)
/* 0: Not accept             1: Accept multicast Packets(default) */
#define EMAC_RX_MCO		(0x1 << 20)
/* 0: Disable(default)       1: Enable Hash filter */
#define EMAC_RX_MHF		(0x1 << 21)
/* 0: Not accept             1: Accept Broadcast Packets(default) */
#define EMAC_RX_BCO		(0x1 << 22)
/* 0: Disable(default)       1: Enable SA Filtering */
#define EMAC_RX_SAF		(0x1 << 24)
/* 0: Normal(default)        1: Inverse Filtering */
#define EMAC_RX_SAIF		(0x1 << 25)

#define EMAC_RX_SETUP		(EMAC_RX_POR | EMAC_RX_UCAD | EMAC_RX_DAF | \
				 EMAC_RX_MCO | EMAC_RX_BCO)

/* 0: Disable                1: Enable Receive Flow Control(default) */
#define EMAC_MAC_CTL0_RFC	(0x1 << 2)
/* 0: Disable                1: Enable Transmit Flow Control(default) */
#define EMAC_MAC_CTL0_TFC	(0x1 << 3)

#define EMAC_MAC_CTL0_SETUP	(EMAC_MAC_CTL0_RFC | EMAC_MAC_CTL0_TFC)

/* 0: Disable                1: Enable MAC Frame Length Checking(default) */
#define EMAC_MAC_CTL1_FLC	(0x1 << 1)
/* 0: Disable(default)       1: Enable Huge Frame */
#define EMAC_MAC_CTL1_HF	(0x1 << 2)
/* 0: Disable(default)       1: Enable MAC Delayed CRC */
#define EMAC_MAC_CTL1_DCRC	(0x1 << 3)
/* 0: Disable                1: Enable MAC CRC(default) */
#define EMAC_MAC_CTL1_CRC	(0x1 << 4)
/* 0: Disable                1: Enable MAC PAD Short frames(default) */
#define EMAC_MAC_CTL1_PC	(0x1 << 5)
/* 0: Disable(default)       1: Enable MAC PAD Short frames and append CRC */
#define EMAC_MAC_CTL1_VC	(0x1 << 6)
/* 0: Disable(default)       1: Enable MAC auto detect Short frames */
#define EMAC_MAC_CTL1_ADP	(0x1 << 7)
/* 0: Disable(default)       1: Enable */
#define EMAC_MAC_CTL1_PRE	(0x1 << 8)
/* 0: Disable(default)       1: Enable */
#define EMAC_MAC_CTL1_LPE	(0x1 << 9)
/* 0: Disable(default)       1: Enable no back off */
#define EMAC_MAC_CTL1_NB	(0x1 << 12)
/* 0: Disable(default)       1: Enable */
#define EMAC_MAC_CTL1_BNB	(0x1 << 13)
/* 0: Disable(default)       1: Enable */
#define EMAC_MAC_CTL1_ED	(0x1 << 14)

#define EMAC_MAC_CTL1_SETUP	(EMAC_MAC_CTL1_FLC | EMAC_MAC_CTL1_CRC | \
				 EMAC_MAC_CTL1_PC)

#define EMAC_MAC_IPGT		0x15

#define EMAC_MAC_NBTB_IPG1	0xc
#define EMAC_MAC_NBTB_IPG2	0x12

#define EMAC_MAC_CW		0x37
#define EMAC_MAC_RM		0xf

#define EMAC_MAC_MFL		0x0600

/* Receive status */
#define EMAC_CRCERR		(0x1 << 4)
#define EMAC_LENERR		(0x3 << 5)

#define EMAC_RX_BUFSIZE		2000

struct emac_eth_dev {
	struct emac_regs *regs;
	struct clk clk;
	struct mii_dev *bus;
	struct phy_device *phydev;
	int link_printed;
#ifdef CONFIG_DM_ETH
	uchar rx_buf[EMAC_RX_BUFSIZE];
#endif
};

struct emac_rxhdr {
	s16 rx_len;
	u16 rx_status;
};

static void emac_inblk_32bit(void *reg, void *data, int count)
{
	int cnt = (count + 3) >> 2;

	if (cnt) {
		u32 *buf = data;

		do {
			u32 x = readl(reg);
			*buf++ = x;
		} while (--cnt);
	}
}

static void emac_outblk_32bit(void *reg, void *data, int count)
{
	int cnt = (count + 3) >> 2;

	if (cnt) {
		const u32 *buf = data;

		do {
			writel(*buf++, reg);
		} while (--cnt);
	}
}

/* Read a word from phyxcer */
static int emac_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
{
	struct emac_eth_dev *priv = bus->priv;
	struct emac_regs *regs = priv->regs;

	/* issue the phy address and reg */
	writel(addr << 8 | reg, &regs->mac_madr);

	/* pull up the phy io line */
	writel(0x1, &regs->mac_mcmd);

	/* Wait read complete */
	mdelay(1);

	/* push down the phy io line */
	writel(0x0, &regs->mac_mcmd);

	/* And read data */
	return readl(&regs->mac_mrdd);
}

/* Write a word to phyxcer */
static int emac_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
			  u16 value)
{
	struct emac_eth_dev *priv = bus->priv;
	struct emac_regs *regs = priv->regs;

	/* issue the phy address and reg */
	writel(addr << 8 | reg, &regs->mac_madr);

	/* pull up the phy io line */
	writel(0x1, &regs->mac_mcmd);

	/* Wait write complete */
	mdelay(1);

	/* push down the phy io line */
	writel(0x0, &regs->mac_mcmd);

	/* and write data */
	writel(value, &regs->mac_mwtd);

	return 0;
}

static int sunxi_emac_init_phy(struct emac_eth_dev *priv, void *dev)
{
	int ret, mask = 0xffffffff;

#ifdef CONFIG_PHY_ADDR
	mask = 1 << CONFIG_PHY_ADDR;
#endif

	priv->bus = mdio_alloc();
	if (!priv->bus) {
		printf("Failed to allocate MDIO bus\n");
		return -ENOMEM;
	}

	priv->bus->read = emac_mdio_read;
	priv->bus->write = emac_mdio_write;
	priv->bus->priv = priv;
	strcpy(priv->bus->name, "emac");

	ret = mdio_register(priv->bus);
	if (ret)
		return ret;

	priv->phydev = phy_find_by_mask(priv->bus, mask,
					PHY_INTERFACE_MODE_MII);
	if (!priv->phydev)
		return -ENODEV;

	phy_connect_dev(priv->phydev, dev);
	phy_config(priv->phydev);

	return 0;
}

static void emac_setup(struct emac_eth_dev *priv)
{
	struct emac_regs *regs = priv->regs;
	u32 reg_val;

	/* Set up TX */
	writel(EMAC_TX_SETUP, &regs->tx_mode);

	/* Set up RX */
	writel(EMAC_RX_SETUP, &regs->rx_ctl);

	/* Set MAC */
	/* Set MAC CTL0 */
	writel(EMAC_MAC_CTL0_SETUP, &regs->mac_ctl0);

	/* Set MAC CTL1 */
	reg_val = 0;
	if (priv->phydev->duplex == DUPLEX_FULL)
		reg_val = (0x1 << 0);
	writel(EMAC_MAC_CTL1_SETUP | reg_val, &regs->mac_ctl1);

	/* Set up IPGT */
	writel(EMAC_MAC_IPGT, &regs->mac_ipgt);

	/* Set up IPGR */
	writel(EMAC_MAC_NBTB_IPG2 | (EMAC_MAC_NBTB_IPG1 << 8), &regs->mac_ipgr);

	/* Set up Collison window */
	writel(EMAC_MAC_RM | (EMAC_MAC_CW << 8), &regs->mac_clrt);

	/* Set up Max Frame Length */
	writel(EMAC_MAC_MFL, &regs->mac_maxf);
}

static void emac_reset(struct emac_eth_dev *priv)
{
	struct emac_regs *regs = priv->regs;

	debug("resetting device\n");

	/* RESET device */
	writel(0, &regs->ctl);
	udelay(200);

	writel(1, &regs->ctl);
	udelay(200);
}

static int _sunxi_write_hwaddr(struct emac_eth_dev *priv, u8 *enetaddr)
{
	struct emac_regs *regs = priv->regs;
	u32 enetaddr_lo, enetaddr_hi;

	enetaddr_lo = enetaddr[2] | (enetaddr[1] << 8) | (enetaddr[0] << 16);
	enetaddr_hi = enetaddr[5] | (enetaddr[4] << 8) | (enetaddr[3] << 16);

	writel(enetaddr_hi, &regs->mac_a0);
	writel(enetaddr_lo, &regs->mac_a1);

	return 0;
}

static int _sunxi_emac_eth_init(struct emac_eth_dev *priv, u8 *enetaddr)
{
	struct emac_regs *regs = priv->regs;
	int ret;

	/* Init EMAC */

	/* Flush RX FIFO */
	setbits_le32(&regs->rx_ctl, 0x8);
	udelay(1);

	/* Init MAC */

	/* Soft reset MAC */
	clrbits_le32(&regs->mac_ctl0, 0x1 << 15);

	/* Clear RX counter */
	writel(0x0, &regs->rx_fbc);
	udelay(1);

	/* Set up EMAC */
	emac_setup(priv);

	_sunxi_write_hwaddr(priv, enetaddr);

	mdelay(1);

	emac_reset(priv);

	/* PHY POWER UP */
	ret = phy_startup(priv->phydev);
	if (ret) {
		printf("Could not initialize PHY %s\n",
		       priv->phydev->dev->name);
		return ret;
	}

	/* Print link status only once */
	if (!priv->link_printed) {
		printf("ENET Speed is %d Mbps - %s duplex connection\n",
		       priv->phydev->speed,
		       priv->phydev->duplex ? "FULL" : "HALF");
		priv->link_printed = 1;
	}

	/* Set EMAC SPEED depend on PHY */
	if (priv->phydev->speed == SPEED_100)
		setbits_le32(&regs->mac_supp, 1 << 8);
	else
		clrbits_le32(&regs->mac_supp, 1 << 8);

	/* Set duplex depend on phy */
	if (priv->phydev->duplex == DUPLEX_FULL)
		setbits_le32(&regs->mac_ctl1, 1 << 0);
	else
		clrbits_le32(&regs->mac_ctl1, 1 << 0);

	/* Enable RX/TX */
	setbits_le32(&regs->ctl, 0x7);

	return 0;
}

static int _sunxi_emac_eth_recv(struct emac_eth_dev *priv, void *packet)
{
	struct emac_regs *regs = priv->regs;
	struct emac_rxhdr rxhdr;
	u32 rxcount;
	u32 reg_val;
	int rx_len;
	int rx_status;
	int good_packet;

	/* Check packet ready or not */

	/* Race warning: The first packet might arrive with
	 * the interrupts disabled, but the second will fix
	 */
	rxcount = readl(&regs->rx_fbc);
	if (!rxcount) {
		/* Had one stuck? */
		rxcount = readl(&regs->rx_fbc);
		if (!rxcount)
			return -EAGAIN;
	}

	reg_val = readl(&regs->rx_io_data);
	if (reg_val != 0x0143414d) {
		/* Disable RX */
		clrbits_le32(&regs->ctl, 0x1 << 2);

		/* Flush RX FIFO */
		setbits_le32(&regs->rx_ctl, 0x1 << 3);
		while (readl(&regs->rx_ctl) & (0x1 << 3))
			;

		/* Enable RX */
		setbits_le32(&regs->ctl, 0x1 << 2);

		return -EAGAIN;
	}

	/* A packet ready now
	 * Get status/length
	 */
	good_packet = 1;

	emac_inblk_32bit(&regs->rx_io_data, &rxhdr, sizeof(rxhdr));

	rx_len = rxhdr.rx_len;
	rx_status = rxhdr.rx_status;

	/* Packet Status check */
	if (rx_len < 0x40) {
		good_packet = 0;
		debug("RX: Bad Packet (runt)\n");
	}

	/* rx_status is identical to RSR register. */
	if (0 & rx_status & (EMAC_CRCERR | EMAC_LENERR)) {
		good_packet = 0;
		if (rx_status & EMAC_CRCERR)
			printf("crc error\n");
		if (rx_status & EMAC_LENERR)
			printf("length error\n");
	}

	/* Move data from EMAC */
	if (good_packet) {
		if (rx_len > EMAC_RX_BUFSIZE) {
			printf("Received packet is too big (len=%d)\n", rx_len);
			return -EMSGSIZE;
		}
		emac_inblk_32bit((void *)&regs->rx_io_data, packet, rx_len);
		return rx_len;
	}

	return -EIO; /* Bad packet */
}

static int _sunxi_emac_eth_send(struct emac_eth_dev *priv, void *packet,
				int len)
{
	struct emac_regs *regs = priv->regs;

	/* Select channel 0 */
	writel(0, &regs->tx_ins);

	/* Write packet */
	emac_outblk_32bit((void *)&regs->tx_io_data, packet, len);

	/* Set TX len */
	writel(len, &regs->tx_pl0);

	/* Start translate from fifo to phy */
	setbits_le32(&regs->tx_ctl0, 1);

	return 0;
}

static int sunxi_emac_board_setup(struct udevice *dev,
				  struct emac_eth_dev *priv)
{
	struct sunxi_sramc_regs *sram =
		(struct sunxi_sramc_regs *)SUNXI_SRAMC_BASE;
	struct emac_regs *regs = priv->regs;
	int pin, ret;

	/* Map SRAM to EMAC */
	setbits_le32(&sram->ctrl1, 0x5 << 2);

	/* Configure pin mux settings for MII Ethernet */
	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++)
		sunxi_gpio_set_cfgpin(pin, SUNXI_GPA_EMAC);

	/* Set up clock gating */
	ret = clk_enable(&priv->clk);
	if (ret) {
		dev_err(dev, "failed to enable emac clock\n");
		return ret;
	}

	/* Set MII clock */
	clrsetbits_le32(&regs->mac_mcfg, 0xf << 2, 0xd << 2);

	return 0;
}

static int sunxi_emac_eth_start(struct udevice *dev)
{
	struct eth_pdata *pdata = dev_get_platdata(dev);

	return _sunxi_emac_eth_init(dev->priv, pdata->enetaddr);
}

static int sunxi_emac_eth_send(struct udevice *dev, void *packet, int length)
{
	struct emac_eth_dev *priv = dev_get_priv(dev);

	return _sunxi_emac_eth_send(priv, packet, length);
}

static int sunxi_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp)
{
	struct emac_eth_dev *priv = dev_get_priv(dev);
	int rx_len;

	rx_len = _sunxi_emac_eth_recv(priv, priv->rx_buf);
	*packetp = priv->rx_buf;

	return rx_len;
}

static void sunxi_emac_eth_stop(struct udevice *dev)
{
	/* Nothing to do here */
}

static int sunxi_emac_eth_probe(struct udevice *dev)
{
	struct eth_pdata *pdata = dev_get_platdata(dev);
	struct emac_eth_dev *priv = dev_get_priv(dev);
	int ret;

	priv->regs = (struct emac_regs *)pdata->iobase;

	ret = clk_get_by_index(dev, 0, &priv->clk);
	if (ret) {
		dev_err(dev, "failed to get emac clock\n");
		return ret;
	}

	ret = sunxi_emac_board_setup(dev, priv);
	if (ret)
		return ret;

	return sunxi_emac_init_phy(priv, dev);
}

static const struct eth_ops sunxi_emac_eth_ops = {
	.start			= sunxi_emac_eth_start,
	.send			= sunxi_emac_eth_send,
	.recv			= sunxi_emac_eth_recv,
	.stop			= sunxi_emac_eth_stop,
};

static int sunxi_emac_eth_ofdata_to_platdata(struct udevice *dev)
{
	struct eth_pdata *pdata = dev_get_platdata(dev);

	pdata->iobase = dev_read_addr(dev);

	return 0;
}

static const struct udevice_id sunxi_emac_eth_ids[] = {
	{ .compatible = "allwinner,sun4i-a10-emac" },
	{ }
};

U_BOOT_DRIVER(eth_sunxi_emac) = {
	.name	= "eth_sunxi_emac",
	.id	= UCLASS_ETH,
	.of_match = sunxi_emac_eth_ids,
	.ofdata_to_platdata = sunxi_emac_eth_ofdata_to_platdata,
	.probe	= sunxi_emac_eth_probe,
	.ops	= &sunxi_emac_eth_ops,
	.priv_auto_alloc_size = sizeof(struct emac_eth_dev),
	.platdata_auto_alloc_size = sizeof(struct eth_pdata),
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
518ce472	2	/*
b70ed300	3	* sunxi_emac.c -- Allwinner A10 ethernet driver
518ce472 HN	4	*
518ce472 HN	5	* (C) Copyright 2012, Stefan Roese <[email protected]>
518ce472 HN	6	*/
	7
	8	#include <common.h>
0ed8eaf1	9	#include <clk.h>
939ed1cb	10	#include <dm.h>
f7ae49fc	11	#include <log.h>
336d4615	12	#include <dm/device_compat.h>
c05ed00a	13	#include <linux/delay.h>
b70ed300	14	#include <linux/err.h>
518ce472	15	#include <malloc.h>
518ce472	16	#include <miiphy.h>
b70ed300	17	#include <net.h>
518ce472 HN	18	#include <asm/io.h>
	19	#include <asm/arch/clock.h>
	20	#include <asm/arch/gpio.h>
	21
	22	/* EMAC register */
b70ed300	23	struct emac_regs {
518ce472 HN	24	u32 ctl; /* 0x00 */
	25	u32 tx_mode; /* 0x04 */
	26	u32 tx_flow; /* 0x08 */
	27	u32 tx_ctl0; /* 0x0c */
	28	u32 tx_ctl1; /* 0x10 */
	29	u32 tx_ins; /* 0x14 */
	30	u32 tx_pl0; /* 0x18 */
	31	u32 tx_pl1; /* 0x1c */
	32	u32 tx_sta; /* 0x20 */
	33	u32 tx_io_data; /* 0x24 */
b70ed300	34	u32 tx_io_data1;/* 0x28 */
518ce472 HN	35	u32 tx_tsvl0; /* 0x2c */
	36	u32 tx_tsvh0; /* 0x30 */
	37	u32 tx_tsvl1; /* 0x34 */
	38	u32 tx_tsvh1; /* 0x38 */
	39	u32 rx_ctl; /* 0x3c */
	40	u32 rx_hash0; /* 0x40 */
	41	u32 rx_hash1; /* 0x44 */
	42	u32 rx_sta; /* 0x48 */
	43	u32 rx_io_data; /* 0x4c */
	44	u32 rx_fbc; /* 0x50 */
	45	u32 int_ctl; /* 0x54 */
	46	u32 int_sta; /* 0x58 */
	47	u32 mac_ctl0; /* 0x5c */
	48	u32 mac_ctl1; /* 0x60 */
	49	u32 mac_ipgt; /* 0x64 */
	50	u32 mac_ipgr; /* 0x68 */
	51	u32 mac_clrt; /* 0x6c */
	52	u32 mac_maxf; /* 0x70 */
	53	u32 mac_supp; /* 0x74 */
	54	u32 mac_test; /* 0x78 */
	55	u32 mac_mcfg; /* 0x7c */
	56	u32 mac_mcmd; /* 0x80 */
	57	u32 mac_madr; /* 0x84 */
	58	u32 mac_mwtd; /* 0x88 */
	59	u32 mac_mrdd; /* 0x8c */
	60	u32 mac_mind; /* 0x90 */
	61	u32 mac_ssrr; /* 0x94 */
	62	u32 mac_a0; /* 0x98 */
	63	u32 mac_a1; /* 0x9c */
	64	};
	65
	66	/* SRAMC register */
	67	struct sunxi_sramc_regs {
	68	u32 ctrl0;
	69	u32 ctrl1;
	70	};
	71
	72	/* 0: Disable 1: Aborted frame enable(default) */
	73	#define EMAC_TX_AB_M (0x1 << 0)
	74	/* 0: CPU 1: DMA(default) */
	75	#define EMAC_TX_TM (0x1 << 1)
	76
	77	#define EMAC_TX_SETUP (0)
	78
	79	/* 0: DRQ asserted 1: DRQ automatically(default) */
	80	#define EMAC_RX_DRQ_MODE (0x1 << 1)
	81	/* 0: CPU 1: DMA(default) */
	82	#define EMAC_RX_TM (0x1 << 2)
	83	/* 0: Normal(default) 1: Pass all Frames */
	84	#define EMAC_RX_PA (0x1 << 4)
	85	/* 0: Normal(default) 1: Pass Control Frames */
	86	#define EMAC_RX_PCF (0x1 << 5)
	87	/* 0: Normal(default) 1: Pass Frames with CRC Error */
	88	#define EMAC_RX_PCRCE (0x1 << 6)
	89	/* 0: Normal(default) 1: Pass Frames with Length Error */
	90	#define EMAC_RX_PLE (0x1 << 7)
	91	/* 0: Normal 1: Pass Frames length out of range(default) */
	92	#define EMAC_RX_POR (0x1 << 8)
	93	/* 0: Not accept 1: Accept unicast Packets(default) */
	94	#define EMAC_RX_UCAD (0x1 << 16)
	95	/* 0: Normal(default) 1: DA Filtering */
	96	#define EMAC_RX_DAF (0x1 << 17)
	97	/* 0: Not accept 1: Accept multicast Packets(default) */
	98	#define EMAC_RX_MCO (0x1 << 20)
99	/* 0: Disable(default) 1: Enable Hash filter */
100	#define EMAC_RX_MHF (0x1 << 21)
101	/* 0: Not accept 1: Accept Broadcast Packets(default) */
102	#define EMAC_RX_BCO (0x1 << 22)
103	/* 0: Disable(default) 1: Enable SA Filtering */
104	#define EMAC_RX_SAF (0x1 << 24)
105	/* 0: Normal(default) 1: Inverse Filtering */
106	#define EMAC_RX_SAIF (0x1 << 25)
107
108	#define EMAC_RX_SETUP (EMAC_RX_POR \| EMAC_RX_UCAD \| EMAC_RX_DAF \| \
109	EMAC_RX_MCO \| EMAC_RX_BCO)
110
111	/* 0: Disable 1: Enable Receive Flow Control(default) */
112	#define EMAC_MAC_CTL0_RFC (0x1 << 2)
113	/* 0: Disable 1: Enable Transmit Flow Control(default) */
114	#define EMAC_MAC_CTL0_TFC (0x1 << 3)
115
116	#define EMAC_MAC_CTL0_SETUP (EMAC_MAC_CTL0_RFC \| EMAC_MAC_CTL0_TFC)
117
118	/* 0: Disable 1: Enable MAC Frame Length Checking(default) */
119	#define EMAC_MAC_CTL1_FLC (0x1 << 1)
120	/* 0: Disable(default) 1: Enable Huge Frame */
121	#define EMAC_MAC_CTL1_HF (0x1 << 2)
122	/* 0: Disable(default) 1: Enable MAC Delayed CRC */
123	#define EMAC_MAC_CTL1_DCRC (0x1 << 3)
124	/* 0: Disable 1: Enable MAC CRC(default) */
125	#define EMAC_MAC_CTL1_CRC (0x1 << 4)
126	/* 0: Disable 1: Enable MAC PAD Short frames(default) */
127	#define EMAC_MAC_CTL1_PC (0x1 << 5)
128	/* 0: Disable(default) 1: Enable MAC PAD Short frames and append CRC */
129	#define EMAC_MAC_CTL1_VC (0x1 << 6)
130	/* 0: Disable(default) 1: Enable MAC auto detect Short frames */
131	#define EMAC_MAC_CTL1_ADP (0x1 << 7)
132	/* 0: Disable(default) 1: Enable */
133	#define EMAC_MAC_CTL1_PRE (0x1 << 8)
134	/* 0: Disable(default) 1: Enable */
135	#define EMAC_MAC_CTL1_LPE (0x1 << 9)
136	/* 0: Disable(default) 1: Enable no back off */
137	#define EMAC_MAC_CTL1_NB (0x1 << 12)
138	/* 0: Disable(default) 1: Enable */
139	#define EMAC_MAC_CTL1_BNB (0x1 << 13)
140	/* 0: Disable(default) 1: Enable */
141	#define EMAC_MAC_CTL1_ED (0x1 << 14)
142
143	#define EMAC_MAC_CTL1_SETUP (EMAC_MAC_CTL1_FLC \| EMAC_MAC_CTL1_CRC \| \
144	EMAC_MAC_CTL1_PC)
145
146	#define EMAC_MAC_IPGT 0x15
147
b70ed300	148	#define EMAC_MAC_NBTB_IPG1 0xc
518ce472 HN	149	#define EMAC_MAC_NBTB_IPG2 0x12
	150
	151	#define EMAC_MAC_CW 0x37
b70ed300	152	#define EMAC_MAC_RM 0xf
518ce472 HN	153
	154	#define EMAC_MAC_MFL 0x0600
	155
	156	/* Receive status */
b70ed300 SR	157	#define EMAC_CRCERR (0x1 << 4)
b70ed300 SR	158	#define EMAC_LENERR (0x3 << 5)
518ce472	159
d88c2f11	160	#define EMAC_RX_BUFSIZE 2000
518ce472	161
b70ed300	162	struct emac_eth_dev {
8145dea4	163	struct emac_regs *regs;
0ed8eaf1	164	struct clk clk;
8145dea4 HG	165	struct mii_dev *bus;
8145dea4 HG	166	struct phy_device *phydev;
518ce472	167	int link_printed;
939ed1cb HG	168	#ifdef CONFIG_DM_ETH
	169	uchar rx_buf[EMAC_RX_BUFSIZE];
	170	#endif
518ce472 HN	171	};
518ce472 HN	172
b70ed300	173	struct emac_rxhdr {
518ce472 HN	174	s16 rx_len;
	175	u16 rx_status;
	176	};
	177
b70ed300	178	static void emac_inblk_32bit(void reg, void data, int count)
518ce472 HN	179	{
	180	int cnt = (count + 3) >> 2;
	181
	182	if (cnt) {
	183	u32 *buf = data;
	184
	185	do {
	186	u32 x = readl(reg);
	187	*buf++ = x;
	188	} while (--cnt);
	189	}
	190	}
	191
b70ed300	192	static void emac_outblk_32bit(void reg, void data, int count)
518ce472 HN	193	{
	194	int cnt = (count + 3) >> 2;
	195
	196	if (cnt) {
	197	const u32 *buf = data;
	198
	199	do {
	200	writel(*buf++, reg);
	201	} while (--cnt);
	202	}
	203	}
	204
b70ed300	205	/* Read a word from phyxcer */
8145dea4	206	static int emac_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
518ce472	207	{
8145dea4 HG	208	struct emac_eth_dev *priv = bus->priv;
8145dea4 HG	209	struct emac_regs *regs = priv->regs;
518ce472 HN	210
	211	/* issue the phy address and reg */
	212	writel(addr << 8 \| reg, &regs->mac_madr);
	213
	214	/* pull up the phy io line */
	215	writel(0x1, &regs->mac_mcmd);
	216
	217	/* Wait read complete */
	218	mdelay(1);
	219
	220	/* push down the phy io line */
	221	writel(0x0, &regs->mac_mcmd);
	222
8145dea4 HG	223	/* And read data */
8145dea4 HG	224	return readl(&regs->mac_mrdd);
518ce472 HN	225	}
518ce472 HN	226
b70ed300	227	/* Write a word to phyxcer */
8145dea4 HG	228	static int emac_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
8145dea4 HG	229	u16 value)
518ce472	230	{
8145dea4 HG	231	struct emac_eth_dev *priv = bus->priv;
8145dea4 HG	232	struct emac_regs *regs = priv->regs;
518ce472 HN	233
	234	/* issue the phy address and reg */
	235	writel(addr << 8 \| reg, &regs->mac_madr);
	236
	237	/* pull up the phy io line */
	238	writel(0x1, &regs->mac_mcmd);
	239
	240	/* Wait write complete */
	241	mdelay(1);
	242
	243	/* push down the phy io line */
	244	writel(0x0, &regs->mac_mcmd);
	245
	246	/* and write data */
	247	writel(value, &regs->mac_mwtd);
	248
	249	return 0;
	250	}
	251
8145dea4	252	static int sunxi_emac_init_phy(struct emac_eth_dev priv, void dev)
518ce472	253	{
8145dea4 HG	254	int ret, mask = 0xffffffff;
	255
	256	#ifdef CONFIG_PHY_ADDR
	257	mask = 1 << CONFIG_PHY_ADDR;
	258	#endif
	259
	260	priv->bus = mdio_alloc();
	261	if (!priv->bus) {
	262	printf("Failed to allocate MDIO bus\n");
	263	return -ENOMEM;
	264	}
	265
	266	priv->bus->read = emac_mdio_read;
	267	priv->bus->write = emac_mdio_write;
	268	priv->bus->priv = priv;
	269	strcpy(priv->bus->name, "emac");
	270
	271	ret = mdio_register(priv->bus);
	272	if (ret)
	273	return ret;
	274
	275	priv->phydev = phy_find_by_mask(priv->bus, mask,
	276	PHY_INTERFACE_MODE_MII);
	277	if (!priv->phydev)
	278	return -ENODEV;
	279
	280	phy_connect_dev(priv->phydev, dev);
	281	phy_config(priv->phydev);
	282
	283	return 0;
	284	}
	285
	286	static void emac_setup(struct emac_eth_dev *priv)
	287	{
	288	struct emac_regs *regs = priv->regs;
518ce472	289	u32 reg_val;
518ce472 HN	290
	291	/* Set up TX */
	292	writel(EMAC_TX_SETUP, &regs->tx_mode);
	293
	294	/* Set up RX */
	295	writel(EMAC_RX_SETUP, &regs->rx_ctl);
	296
	297	/* Set MAC */
	298	/* Set MAC CTL0 */
	299	writel(EMAC_MAC_CTL0_SETUP, &regs->mac_ctl0);
	300
	301	/* Set MAC CTL1 */
518ce472	302	reg_val = 0;
8145dea4	303	if (priv->phydev->duplex == DUPLEX_FULL)
518ce472 HN	304	reg_val = (0x1 << 0);
	305	writel(EMAC_MAC_CTL1_SETUP \| reg_val, &regs->mac_ctl1);
	306
	307	/* Set up IPGT */
	308	writel(EMAC_MAC_IPGT, &regs->mac_ipgt);
	309
	310	/* Set up IPGR */
	311	writel(EMAC_MAC_NBTB_IPG2 \| (EMAC_MAC_NBTB_IPG1 << 8), &regs->mac_ipgr);
	312
	313	/* Set up Collison window */
	314	writel(EMAC_MAC_RM \| (EMAC_MAC_CW << 8), &regs->mac_clrt);
	315
	316	/* Set up Max Frame Length */
	317	writel(EMAC_MAC_MFL, &regs->mac_maxf);
	318	}
	319
f9f62d2d	320	static void emac_reset(struct emac_eth_dev *priv)
518ce472	321	{
f9f62d2d	322	struct emac_regs *regs = priv->regs;
518ce472 HN	323
	324	debug("resetting device\n");
	325
	326	/* RESET device */
	327	writel(0, &regs->ctl);
	328	udelay(200);
	329
	330	writel(1, &regs->ctl);
	331	udelay(200);
	332	}
	333
ace1520c	334	static int _sunxi_write_hwaddr(struct emac_eth_dev priv, u8 enetaddr)
	335	{
	336	struct emac_regs *regs = priv->regs;
	337	u32 enetaddr_lo, enetaddr_hi;
	338
	339	enetaddr_lo = enetaddr[2] \| (enetaddr[1] << 8) \| (enetaddr[0] << 16);
	340	enetaddr_hi = enetaddr[5] \| (enetaddr[4] << 8) \| (enetaddr[3] << 16);
	341
6e35686d JH	342	writel(enetaddr_hi, &regs->mac_a0);
6e35686d JH	343	writel(enetaddr_lo, &regs->mac_a1);
ace1520c	344
	345	return 0;
	346	}
	347
f9f62d2d	348	static int _sunxi_emac_eth_init(struct emac_eth_dev priv, u8 enetaddr)
518ce472	349	{
f9f62d2d	350	struct emac_regs *regs = priv->regs;
8145dea4	351	int ret;
518ce472 HN	352
	353	/* Init EMAC */
	354
	355	/* Flush RX FIFO */
	356	setbits_le32(&regs->rx_ctl, 0x8);
	357	udelay(1);
	358
	359	/* Init MAC */
	360
	361	/* Soft reset MAC */
b70ed300	362	clrbits_le32(&regs->mac_ctl0, 0x1 << 15);
518ce472 HN	363
	364	/* Clear RX counter */
	365	writel(0x0, &regs->rx_fbc);
	366	udelay(1);
	367
	368	/* Set up EMAC */
8145dea4	369	emac_setup(priv);
518ce472	370
ace1520c	371	_sunxi_write_hwaddr(priv, enetaddr);
518ce472 HN	372
	373	mdelay(1);
	374
f9f62d2d	375	emac_reset(priv);
518ce472 HN	376
518ce472 HN	377	/* PHY POWER UP */
8145dea4 HG	378	ret = phy_startup(priv->phydev);
	379	if (ret) {
	380	printf("Could not initialize PHY %s\n",
	381	priv->phydev->dev->name);
	382	return ret;
	383	}
518ce472 HN	384
	385	/* Print link status only once */
	386	if (!priv->link_printed) {
	387	printf("ENET Speed is %d Mbps - %s duplex connection\n",
8145dea4 HG	388	priv->phydev->speed,
8145dea4 HG	389	priv->phydev->duplex ? "FULL" : "HALF");
518ce472 HN	390	priv->link_printed = 1;
	391	}
	392
	393	/* Set EMAC SPEED depend on PHY */
8145dea4 HG	394	if (priv->phydev->speed == SPEED_100)
	395	setbits_le32(&regs->mac_supp, 1 << 8);
	396	else
	397	clrbits_le32(&regs->mac_supp, 1 << 8);
518ce472 HN	398
518ce472 HN	399	/* Set duplex depend on phy */
8145dea4 HG	400	if (priv->phydev->duplex == DUPLEX_FULL)
	401	setbits_le32(&regs->mac_ctl1, 1 << 0);
	402	else
	403	clrbits_le32(&regs->mac_ctl1, 1 << 0);
518ce472 HN	404
	405	/* Enable RX/TX */
	406	setbits_le32(&regs->ctl, 0x7);
	407
	408	return 0;
	409	}
	410
f9f62d2d	411	static int _sunxi_emac_eth_recv(struct emac_eth_dev priv, void packet)
518ce472	412	{
f9f62d2d	413	struct emac_regs *regs = priv->regs;
b70ed300	414	struct emac_rxhdr rxhdr;
518ce472 HN	415	u32 rxcount;
	416	u32 reg_val;
	417	int rx_len;
	418	int rx_status;
	419	int good_packet;
	420
	421	/* Check packet ready or not */
	422
b70ed300	423	/* Race warning: The first packet might arrive with
518ce472 HN	424	* the interrupts disabled, but the second will fix
	425	*/
	426	rxcount = readl(&regs->rx_fbc);
	427	if (!rxcount) {
	428	/* Had one stuck? */
	429	rxcount = readl(&regs->rx_fbc);
	430	if (!rxcount)
f9f62d2d	431	return -EAGAIN;
518ce472 HN	432	}
	433
	434	reg_val = readl(&regs->rx_io_data);
	435	if (reg_val != 0x0143414d) {
	436	/* Disable RX */
b70ed300	437	clrbits_le32(&regs->ctl, 0x1 << 2);
518ce472 HN	438
518ce472 HN	439	/* Flush RX FIFO */
b70ed300 SR	440	setbits_le32(&regs->rx_ctl, 0x1 << 3);
b70ed300 SR	441	while (readl(&regs->rx_ctl) & (0x1 << 3))
518ce472 HN	442	;
	443
	444	/* Enable RX */
b70ed300	445	setbits_le32(&regs->ctl, 0x1 << 2);
518ce472	446
f9f62d2d	447	return -EAGAIN;
518ce472 HN	448	}
518ce472 HN	449
b70ed300	450	/* A packet ready now
518ce472 HN	451	* Get status/length
	452	*/
	453	good_packet = 1;
	454
b70ed300	455	emac_inblk_32bit(&regs->rx_io_data, &rxhdr, sizeof(rxhdr));
518ce472 HN	456
	457	rx_len = rxhdr.rx_len;
	458	rx_status = rxhdr.rx_status;
	459
	460	/* Packet Status check */
	461	if (rx_len < 0x40) {
	462	good_packet = 0;
	463	debug("RX: Bad Packet (runt)\n");
	464	}
	465
	466	/* rx_status is identical to RSR register. */
	467	if (0 & rx_status & (EMAC_CRCERR \| EMAC_LENERR)) {
	468	good_packet = 0;
	469	if (rx_status & EMAC_CRCERR)
	470	printf("crc error\n");
	471	if (rx_status & EMAC_LENERR)
	472	printf("length error\n");
	473	}
	474
b70ed300	475	/* Move data from EMAC */
518ce472	476	if (good_packet) {
d88c2f11	477	if (rx_len > EMAC_RX_BUFSIZE) {
518ce472	478	printf("Received packet is too big (len=%d)\n", rx_len);
f9f62d2d	479	return -EMSGSIZE;
518ce472	480	}
f9f62d2d HG	481	emac_inblk_32bit((void *)&regs->rx_io_data, packet, rx_len);
f9f62d2d HG	482	return rx_len;
518ce472 HN	483	}
518ce472 HN	484
f9f62d2d	485	return -EIO; /* Bad packet */
518ce472 HN	486	}
518ce472 HN	487
f9f62d2d HG	488	static int _sunxi_emac_eth_send(struct emac_eth_dev priv, void packet,
f9f62d2d HG	489	int len)
518ce472	490	{
f9f62d2d	491	struct emac_regs *regs = priv->regs;
518ce472 HN	492
	493	/* Select channel 0 */
	494	writel(0, &regs->tx_ins);
	495
	496	/* Write packet */
b70ed300	497	emac_outblk_32bit((void *)&regs->tx_io_data, packet, len);
518ce472 HN	498
	499	/* Set TX len */
	500	writel(len, &regs->tx_pl0);
	501
	502	/* Start translate from fifo to phy */
	503	setbits_le32(&regs->tx_ctl0, 1);
	504
	505	return 0;
	506	}
	507
e2f74215 SA	508	static int sunxi_emac_board_setup(struct udevice *dev,
e2f74215 SA	509	struct emac_eth_dev *priv)
518ce472	510	{
518ce472 HN	511	struct sunxi_sramc_regs *sram =
518ce472 HN	512	(struct sunxi_sramc_regs *)SUNXI_SRAMC_BASE;
f9f62d2d	513	struct emac_regs *regs = priv->regs;
0ed8eaf1	514	int pin, ret;
f9f62d2d HG	515
	516	/* Map SRAM to EMAC */
	517	setbits_le32(&sram->ctrl1, 0x5 << 2);
	518
	519	/* Configure pin mux settings for MII Ethernet */
	520	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++)
	521	sunxi_gpio_set_cfgpin(pin, SUNXI_GPA_EMAC);
	522
	523	/* Set up clock gating */
0ed8eaf1 JT	524	ret = clk_enable(&priv->clk);
	525	if (ret) {
	526	dev_err(dev, "failed to enable emac clock\n");
	527	return ret;
	528	}
f9f62d2d HG	529
	530	/* Set MII clock */
	531	clrsetbits_le32(&regs->mac_mcfg, 0xf << 2, 0xd << 2);
0ed8eaf1 JT	532
0ed8eaf1 JT	533	return 0;
f9f62d2d HG	534	}
f9f62d2d HG	535
939ed1cb HG	536	static int sunxi_emac_eth_start(struct udevice *dev)
	537	{
	538	struct eth_pdata *pdata = dev_get_platdata(dev);
	539
	540	return _sunxi_emac_eth_init(dev->priv, pdata->enetaddr);
	541	}
	542
	543	static int sunxi_emac_eth_send(struct udevice dev, void packet, int length)
	544	{
	545	struct emac_eth_dev *priv = dev_get_priv(dev);
	546
	547	return _sunxi_emac_eth_send(priv, packet, length);
	548	}
	549
a1ca92ea	550	static int sunxi_emac_eth_recv(struct udevice dev, int flags, uchar *packetp)
939ed1cb HG	551	{
	552	struct emac_eth_dev *priv = dev_get_priv(dev);
	553	int rx_len;
	554
	555	rx_len = _sunxi_emac_eth_recv(priv, priv->rx_buf);
	556	*packetp = priv->rx_buf;
	557
	558	return rx_len;
	559	}
	560
	561	static void sunxi_emac_eth_stop(struct udevice *dev)
	562	{
	563	/* Nothing to do here */
	564	}
	565
	566	static int sunxi_emac_eth_probe(struct udevice *dev)
	567	{
	568	struct eth_pdata *pdata = dev_get_platdata(dev);
	569	struct emac_eth_dev *priv = dev_get_priv(dev);
0ed8eaf1	570	int ret;
939ed1cb HG	571
939ed1cb HG	572	priv->regs = (struct emac_regs *)pdata->iobase;
0ed8eaf1 JT	573
	574	ret = clk_get_by_index(dev, 0, &priv->clk);
	575	if (ret) {
	576	dev_err(dev, "failed to get emac clock\n");
	577	return ret;
	578	}
	579
e2f74215	580	ret = sunxi_emac_board_setup(dev, priv);
0ed8eaf1 JT	581	if (ret)
0ed8eaf1 JT	582	return ret;
939ed1cb HG	583
	584	return sunxi_emac_init_phy(priv, dev);
	585	}
	586
	587	static const struct eth_ops sunxi_emac_eth_ops = {
	588	.start = sunxi_emac_eth_start,
	589	.send = sunxi_emac_eth_send,
	590	.recv = sunxi_emac_eth_recv,
	591	.stop = sunxi_emac_eth_stop,
	592	};
	593
	594	static int sunxi_emac_eth_ofdata_to_platdata(struct udevice *dev)
	595	{
	596	struct eth_pdata *pdata = dev_get_platdata(dev);
	597
2548493a	598	pdata->iobase = dev_read_addr(dev);
939ed1cb HG	599
	600	return 0;
	601	}
	602
	603	static const struct udevice_id sunxi_emac_eth_ids[] = {
	604	{ .compatible = "allwinner,sun4i-a10-emac" },
	605	{ }
	606	};
	607
	608	U_BOOT_DRIVER(eth_sunxi_emac) = {
	609	.name = "eth_sunxi_emac",
	610	.id = UCLASS_ETH,
	611	.of_match = sunxi_emac_eth_ids,
	612	.ofdata_to_platdata = sunxi_emac_eth_ofdata_to_platdata,
	613	.probe = sunxi_emac_eth_probe,
	614	.ops = &sunxi_emac_eth_ops,
	615	.priv_auto_alloc_size = sizeof(struct emac_eth_dev),
	616	.platdata_auto_alloc_size = sizeof(struct eth_pdata),
	617	};