[u-boot.git] / drivers / crypto / ace_sha.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Advanced Crypto Engine - SHA Firmware
 * Copyright (c) 2012  Samsung Electronics
 */
#include <common.h>
#include "ace_sha.h"
#include <log.h>
#include <rand.h>

#ifdef CONFIG_SHA_HW_ACCEL
#include <u-boot/sha256.h>
#include <u-boot/sha1.h>
#include <linux/errno.h>

/* SHA1 value for the message of zero length */
static const unsigned char sha1_digest_emptymsg[SHA1_SUM_LEN] = {
	0xDA, 0x39, 0xA3, 0xEE, 0x5E, 0x6B, 0x4B, 0x0D,
	0x32, 0x55, 0xBF, 0xFF, 0x95, 0x60, 0x18, 0x90,
	0xAF, 0xD8, 0x07, 0x09};

/* SHA256 value for the message of zero length */
static const unsigned char sha256_digest_emptymsg[SHA256_SUM_LEN] = {
	0xE3, 0xB0, 0xC4, 0x42, 0x98, 0xFC, 0x1C, 0x14,
	0x9A, 0xFB, 0xF4, 0xC8, 0x99, 0x6F, 0xB9, 0x24,
	0x27, 0xAE, 0x41, 0xE4, 0x64, 0x9B, 0x93, 0x4C,
	0xA4, 0x95, 0x99, 0x1B, 0x78, 0x52, 0xB8, 0x55};

int ace_sha_hash_digest(const unsigned char *pbuf, unsigned int buf_len,
			unsigned char *pout, unsigned int hash_type)
{
	unsigned int i, reg, len;
	unsigned int *pdigest;
	struct exynos_ace_sfr *ace_sha_reg =
		(struct exynos_ace_sfr *)samsung_get_base_ace_sfr();

	if (buf_len == 0) {
		/* ACE H/W cannot compute hash value for empty string */
		if (hash_type == ACE_SHA_TYPE_SHA1)
			memcpy(pout, sha1_digest_emptymsg, SHA1_SUM_LEN);
		else
			memcpy(pout, sha256_digest_emptymsg, SHA256_SUM_LEN);
		return 0;
	}

	/* Flush HRDMA */
	writel(ACE_FC_HRDMACFLUSH_ON, &ace_sha_reg->fc_hrdmac);
	writel(ACE_FC_HRDMACFLUSH_OFF, &ace_sha_reg->fc_hrdmac);

	/* Set byte swap of data in */
	writel(ACE_HASH_SWAPDI_ON | ACE_HASH_SWAPDO_ON | ACE_HASH_SWAPIV_ON,
	       &ace_sha_reg->hash_byteswap);

	/* Select Hash input mux as external source */
	reg = readl(&ace_sha_reg->fc_fifoctrl);
	reg = (reg & ~ACE_FC_SELHASH_MASK) | ACE_FC_SELHASH_EXOUT;
	writel(reg, &ace_sha_reg->fc_fifoctrl);

	/* Set Hash as SHA1 or SHA256 and start Hash engine */
	reg = (hash_type == ACE_SHA_TYPE_SHA1) ?
		ACE_HASH_ENGSEL_SHA1HASH : ACE_HASH_ENGSEL_SHA256HASH;
	reg |= ACE_HASH_STARTBIT_ON;
	writel(reg, &ace_sha_reg->hash_control);

	/* Enable FIFO mode */
	writel(ACE_HASH_FIFO_ON, &ace_sha_reg->hash_fifo_mode);

	/* Set message length */
	writel(buf_len, &ace_sha_reg->hash_msgsize_low);
	writel(0, &ace_sha_reg->hash_msgsize_high);

	/* Set HRDMA */
	writel((unsigned int)pbuf, &ace_sha_reg->fc_hrdmas);
	writel(buf_len, &ace_sha_reg->fc_hrdmal);

	while ((readl(&ace_sha_reg->hash_status) & ACE_HASH_MSGDONE_MASK) ==
		ACE_HASH_MSGDONE_OFF) {
		/*
		 * PRNG error bit goes HIGH if a PRNG request occurs without
		 * a complete seed setup. We are using this bit to check h/w
		 * fault because proper setup is not expected in that case.
		 */
		if ((readl(&ace_sha_reg->hash_status)
			& ACE_HASH_PRNGERROR_MASK) == ACE_HASH_PRNGERROR_ON)
			return -EBUSY;
	}

	/* Clear MSG_DONE bit */
	writel(ACE_HASH_MSGDONE_ON, &ace_sha_reg->hash_status);

	/* Read hash result */
	pdigest = (unsigned int *)pout;
	len = (hash_type == ACE_SHA_TYPE_SHA1) ? SHA1_SUM_LEN : SHA256_SUM_LEN;

	for (i = 0; i < len / 4; i++)
		pdigest[i] = readl(&ace_sha_reg->hash_result[i]);

	/* Clear HRDMA pending bit */
	writel(ACE_FC_HRDMA, &ace_sha_reg->fc_intpend);

	return 0;
}

void hw_sha256(const unsigned char *pbuf, unsigned int buf_len,
			unsigned char *pout, unsigned int chunk_size)
{
	if (ace_sha_hash_digest(pbuf, buf_len, pout, ACE_SHA_TYPE_SHA256))
		debug("ACE was not setup properly or it is faulty\n");
}

void hw_sha1(const unsigned char *pbuf, unsigned int buf_len,
			unsigned char *pout, unsigned int chunk_size)
{
	if (ace_sha_hash_digest(pbuf, buf_len, pout, ACE_SHA_TYPE_SHA1))
		debug("ACE was not setup properly or it is faulty\n");
}
#endif /* CONFIG_SHA_HW_ACCEL */

#ifdef CONFIG_LIB_HW_RAND
static unsigned int seed_done;

void srand(unsigned int seed)
{
	struct exynos_ace_sfr *reg =
		(struct exynos_ace_sfr *)samsung_get_base_ace_sfr();
	int i, status;

	/* Seed data */
	for (i = 0; i < ACE_HASH_PRNG_REG_NUM; i++)
		writel(seed << i, &reg->hash_seed[i]);

	/* Wait for seed setup done */
	while (1) {
		status = readl(&reg->hash_status);
		if ((status & ACE_HASH_SEEDSETTING_MASK) ||
		    (status & ACE_HASH_PRNGERROR_MASK))
			break;
	}

	seed_done = 1;
}

unsigned int rand(void)
{
	struct exynos_ace_sfr *reg =
		(struct exynos_ace_sfr *)samsung_get_base_ace_sfr();
	int i, status;
	unsigned int seed = (unsigned int)&status;
	unsigned int ret = 0;

	if (!seed_done)
		srand(seed);

	/* Start PRNG */
	writel(ACE_HASH_ENGSEL_PRNG | ACE_HASH_STARTBIT_ON, &reg->hash_control);

	/* Wait for PRNG done */
	while (1) {
		status = readl(&reg->hash_status);
		if (status & ACE_HASH_PRNGDONE_MASK)
			break;
		if (status & ACE_HASH_PRNGERROR_MASK) {
			seed_done = 0;
			return 0;
		}
	}

	/* Clear Done IRQ */
	writel(ACE_HASH_PRNGDONE_MASK, &reg->hash_status);

	/* Read a PRNG result */
	for (i = 0; i < ACE_HASH_PRNG_REG_NUM; i++)
		ret += readl(&reg->hash_prng[i]);

	seed_done = 0;
	return ret;
}

unsigned int rand_r(unsigned int *seedp)
{
	srand(*seedp);

	return rand();
}
#endif /* CONFIG_LIB_HW_RAND */
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
acbb1eb7 AS	2	/*
	3	* Advanced Crypto Engine - SHA Firmware
	4	* Copyright (c) 2012 Samsung Electronics
acbb1eb7 AS	5	*/
acbb1eb7 AS	6	#include <common.h>
0bd93724	7	#include "ace_sha.h"
f7ae49fc	8	#include <log.h>
90526e9f	9	#include <rand.h>
0bd93724 PM	10
0bd93724 PM	11	#ifdef CONFIG_SHA_HW_ACCEL
2b9912e6 JH	12	#include <u-boot/sha256.h>
2b9912e6 JH	13	#include <u-boot/sha1.h>
1221ce45	14	#include <linux/errno.h>
acbb1eb7 AS	15
	16	/* SHA1 value for the message of zero length */
	17	static const unsigned char sha1_digest_emptymsg[SHA1_SUM_LEN] = {
	18	0xDA, 0x39, 0xA3, 0xEE, 0x5E, 0x6B, 0x4B, 0x0D,
	19	0x32, 0x55, 0xBF, 0xFF, 0x95, 0x60, 0x18, 0x90,
	20	0xAF, 0xD8, 0x07, 0x09};
	21
	22	/* SHA256 value for the message of zero length */
	23	static const unsigned char sha256_digest_emptymsg[SHA256_SUM_LEN] = {
	24	0xE3, 0xB0, 0xC4, 0x42, 0x98, 0xFC, 0x1C, 0x14,
	25	0x9A, 0xFB, 0xF4, 0xC8, 0x99, 0x6F, 0xB9, 0x24,
	26	0x27, 0xAE, 0x41, 0xE4, 0x64, 0x9B, 0x93, 0x4C,
	27	0xA4, 0x95, 0x99, 0x1B, 0x78, 0x52, 0xB8, 0x55};
	28
	29	int ace_sha_hash_digest(const unsigned char *pbuf, unsigned int buf_len,
	30	unsigned char *pout, unsigned int hash_type)
	31	{
	32	unsigned int i, reg, len;
	33	unsigned int *pdigest;
	34	struct exynos_ace_sfr *ace_sha_reg =
	35	(struct exynos_ace_sfr *)samsung_get_base_ace_sfr();
	36
	37	if (buf_len == 0) {
	38	/* ACE H/W cannot compute hash value for empty string */
	39	if (hash_type == ACE_SHA_TYPE_SHA1)
	40	memcpy(pout, sha1_digest_emptymsg, SHA1_SUM_LEN);
	41	else
	42	memcpy(pout, sha256_digest_emptymsg, SHA256_SUM_LEN);
	43	return 0;
	44	}
	45
	46	/* Flush HRDMA */
	47	writel(ACE_FC_HRDMACFLUSH_ON, &ace_sha_reg->fc_hrdmac);
	48	writel(ACE_FC_HRDMACFLUSH_OFF, &ace_sha_reg->fc_hrdmac);
	49
	50	/* Set byte swap of data in */
	51	writel(ACE_HASH_SWAPDI_ON \| ACE_HASH_SWAPDO_ON \| ACE_HASH_SWAPIV_ON,
	52	&ace_sha_reg->hash_byteswap);
	53
	54	/* Select Hash input mux as external source */
	55	reg = readl(&ace_sha_reg->fc_fifoctrl);
	56	reg = (reg & ~ACE_FC_SELHASH_MASK) \| ACE_FC_SELHASH_EXOUT;
	57	writel(reg, &ace_sha_reg->fc_fifoctrl);
	58
	59	/* Set Hash as SHA1 or SHA256 and start Hash engine */
	60	reg = (hash_type == ACE_SHA_TYPE_SHA1) ?
	61	ACE_HASH_ENGSEL_SHA1HASH : ACE_HASH_ENGSEL_SHA256HASH;
	62	reg \|= ACE_HASH_STARTBIT_ON;
	63	writel(reg, &ace_sha_reg->hash_control);
	64
	65	/* Enable FIFO mode */
	66	writel(ACE_HASH_FIFO_ON, &ace_sha_reg->hash_fifo_mode);
	67
	68	/* Set message length */
	69	writel(buf_len, &ace_sha_reg->hash_msgsize_low);
	70	writel(0, &ace_sha_reg->hash_msgsize_high);
	71
	72	/* Set HRDMA */
	73	writel((unsigned int)pbuf, &ace_sha_reg->fc_hrdmas);
	74	writel(buf_len, &ace_sha_reg->fc_hrdmal);
	75
	76	while ((readl(&ace_sha_reg->hash_status) & ACE_HASH_MSGDONE_MASK) ==
	77	ACE_HASH_MSGDONE_OFF) {
	78	/*
79	* PRNG error bit goes HIGH if a PRNG request occurs without
80	* a complete seed setup. We are using this bit to check h/w
81	* fault because proper setup is not expected in that case.
82	*/
83	if ((readl(&ace_sha_reg->hash_status)
84	& ACE_HASH_PRNGERROR_MASK) == ACE_HASH_PRNGERROR_ON)
85	return -EBUSY;
86	}
87
88	/* Clear MSG_DONE bit */
89	writel(ACE_HASH_MSGDONE_ON, &ace_sha_reg->hash_status);
90
91	/* Read hash result */
92	pdigest = (unsigned int *)pout;
93	len = (hash_type == ACE_SHA_TYPE_SHA1) ? SHA1_SUM_LEN : SHA256_SUM_LEN;
94
95	for (i = 0; i < len / 4; i++)
96	pdigest[i] = readl(&ace_sha_reg->hash_result[i]);
97
98	/* Clear HRDMA pending bit */
99	writel(ACE_FC_HRDMA, &ace_sha_reg->fc_intpend);
100
101	return 0;
102	}
103
104	void hw_sha256(const unsigned char *pbuf, unsigned int buf_len,
105	unsigned char *pout, unsigned int chunk_size)
106	{
107	if (ace_sha_hash_digest(pbuf, buf_len, pout, ACE_SHA_TYPE_SHA256))
108	debug("ACE was not setup properly or it is faulty\n");
109	}
110
111	void hw_sha1(const unsigned char *pbuf, unsigned int buf_len,
112	unsigned char *pout, unsigned int chunk_size)
113	{
114	if (ace_sha_hash_digest(pbuf, buf_len, pout, ACE_SHA_TYPE_SHA1))
115	debug("ACE was not setup properly or it is faulty\n");
116	}
0bd93724 PM	117	#endif /* CONFIG_SHA_HW_ACCEL */
	118
	119	#ifdef CONFIG_LIB_HW_RAND
	120	static unsigned int seed_done;
	121
	122	void srand(unsigned int seed)
	123	{
	124	struct exynos_ace_sfr *reg =
	125	(struct exynos_ace_sfr *)samsung_get_base_ace_sfr();
	126	int i, status;
	127
	128	/* Seed data */
	129	for (i = 0; i < ACE_HASH_PRNG_REG_NUM; i++)
	130	writel(seed << i, &reg->hash_seed[i]);
	131
	132	/* Wait for seed setup done */
	133	while (1) {
	134	status = readl(&reg->hash_status);
	135	if ((status & ACE_HASH_SEEDSETTING_MASK) \|\|
	136	(status & ACE_HASH_PRNGERROR_MASK))
	137	break;
	138	}
	139
	140	seed_done = 1;
	141	}
	142
	143	unsigned int rand(void)
	144	{
	145	struct exynos_ace_sfr *reg =
	146	(struct exynos_ace_sfr *)samsung_get_base_ace_sfr();
	147	int i, status;
	148	unsigned int seed = (unsigned int)&status;
	149	unsigned int ret = 0;
	150
	151	if (!seed_done)
	152	srand(seed);
	153
	154	/* Start PRNG */
	155	writel(ACE_HASH_ENGSEL_PRNG \| ACE_HASH_STARTBIT_ON, &reg->hash_control);
	156
	157	/* Wait for PRNG done */
	158	while (1) {
	159	status = readl(&reg->hash_status);
	160	if (status & ACE_HASH_PRNGDONE_MASK)
	161	break;
	162	if (status & ACE_HASH_PRNGERROR_MASK) {
	163	seed_done = 0;
	164	return 0;
	165	}
	166	}
	167
	168	/* Clear Done IRQ */
	169	writel(ACE_HASH_PRNGDONE_MASK, &reg->hash_status);
	170
	171	/* Read a PRNG result */
	172	for (i = 0; i < ACE_HASH_PRNG_REG_NUM; i++)
	173	ret += readl(&reg->hash_prng[i]);
	174
	175	seed_done = 0;
	176	return ret;
	177	}
	178
	179	unsigned int rand_r(unsigned int *seedp)
	180	{
181	srand(*seedp);
182
183	return rand();
184	}
185	#endif /* CONFIG_LIB_HW_RAND */