[u-boot.git] / arch / arm / cpu / sa1100 / start.S

/*
 *  armboot - Startup Code for SA1100 CPU
 *
 *  Copyright (C) 1998	Dan Malek <[email protected]>
 *  Copyright (C) 1999	Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
 *  Copyright (C) 2000	Wolfgang Denk <[email protected]>
 *  Copyright (c) 2001	Alex Züpke <[email protected]>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <asm-offsets.h>
#include <config.h>

/*
 *************************************************************************
 *
 * Startup Code (reset vector)
 *
 * do important init only if we don't start from memory!
 * relocate armboot to ram
 * setup stack
 * jump to second stage
 *
 *************************************************************************
 */

	.globl	reset

reset:
	/*
	 * set the cpu to SVC32 mode
	 */
	mrs	r0,cpsr
	bic	r0,r0,#0x1f
	orr	r0,r0,#0xd3
	msr	cpsr,r0

	/*
	 * we do sys-critical inits only at reboot,
	 * not when booting from ram!
	 */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
	bl	cpu_init_crit
#endif

	bl	_main

/*------------------------------------------------------------------------------*/

	.globl	c_runtime_cpu_setup
c_runtime_cpu_setup:

	mov	pc, lr

/*
 *************************************************************************
 *
 * CPU_init_critical registers
 *
 * setup important registers
 * setup memory timing
 *
 *************************************************************************
 */


/* Interrupt-Controller base address */
IC_BASE:	.word	0x90050000
#define ICMR	0x04


/* Reset-Controller */
RST_BASE:		.word   0x90030000
#define RSRR	0x00
#define RCSR	0x04


/* PWR */
PWR_BASE:		.word   0x90020000
#define PSPR    0x08
#define PPCR    0x14
cpuspeed:		.word   CONFIG_SYS_CPUSPEED


cpu_init_crit:
	/*
	 * mask all IRQs
	 */
	ldr	r0, IC_BASE
	mov	r1, #0x00
	str	r1, [r0, #ICMR]

	/* set clock speed */
	ldr	r0, PWR_BASE
	ldr	r1, cpuspeed
	str	r1, [r0, #PPCR]

	/*
	 * before relocating, we have to setup RAM timing
	 * because memory timing is board-dependend, you will
	 * find a lowlevel_init.S in your board directory.
	 */
	mov	ip,	lr
	bl	lowlevel_init
	mov	lr,	ip

	/*
	 * disable MMU stuff and enable I-cache
	 */
	mrc	p15,0,r0,c1,c0
	bic	r0, r0, #0x00002000	@ clear bit 13 (X)
	bic	r0, r0, #0x0000000f	@ clear bits 3-0 (WCAM)
	orr	r0, r0, #0x00001000	@ set bit 12 (I) Icache
	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
	mcr	p15,0,r0,c1,c0

	/*
	 * flush v4 I/D caches
	 */
	mov	r0, #0
	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */

	mov	pc, lr
Commit	Line	Data
fe8c2806 WD	1	/*
	2	* armboot - Startup Code for SA1100 CPU
	3	*
	4	* Copyright (C) 1998 Dan Malek <[email protected]>
	5	* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
	6	* Copyright (C) 2000 Wolfgang Denk <[email protected]>
fa82f871	7	* Copyright (c) 2001 Alex Züpke <[email protected]>
fe8c2806	8	*
1a459660	9	* SPDX-License-Identifier: GPL-2.0+
fe8c2806 WD	10	*/
fe8c2806 WD	11
25ddd1fb	12	#include <asm-offsets.h>
fe8c2806	13	#include <config.h>
fe8c2806	14
fe8c2806 WD	15	/*
	16	*************************************************************************
	17	*
	18	* Startup Code (reset vector)
	19	*
	20	* do important init only if we don't start from memory!
	21	* relocate armboot to ram
	22	* setup stack
	23	* jump to second stage
	24	*
	25	*************************************************************************
	26	*/
	27
41623c91	28	.globl reset
e30ceca2 HS	29
	30	reset:
	31	/*
	32	* set the cpu to SVC32 mode
	33	*/
	34	mrs r0,cpsr
	35	bic r0,r0,#0x1f
	36	orr r0,r0,#0xd3
	37	msr cpsr,r0
	38
	39	/*
	40	* we do sys-critical inits only at reboot,
	41	* not when booting from ram!
	42	*/
	43	#ifndef CONFIG_SKIP_LOWLEVEL_INIT
	44	bl cpu_init_crit
	45	#endif
	46
e05e5de7	47	bl _main
e30ceca2 HS	48
	49	/------------------------------------------------------------------------------/
	50
e05e5de7 AA	51	.globl c_runtime_cpu_setup
	52	c_runtime_cpu_setup:
	53
	54	mov pc, lr
	55
fe8c2806 WD	56	/*
	57	*************************************************************************
	58	*
	59	* CPU_init_critical registers
	60	*
	61	* setup important registers
	62	* setup memory timing
	63	*
	64	*************************************************************************
	65	*/
	66
	67
16263087	68	/* Interrupt-Controller base address */
fe8c2806 WD	69	IC_BASE: .word 0x90050000
	70	#define ICMR 0x04
	71
	72
	73	/* Reset-Controller */
	74	RST_BASE: .word 0x90030000
	75	#define RSRR 0x00
	76	#define RCSR 0x04
	77
	78
	79	/* PWR */
	80	PWR_BASE: .word 0x90020000
	81	#define PSPR 0x08
	82	#define PPCR 0x14
6d0f6bcf	83	cpuspeed: .word CONFIG_SYS_CPUSPEED
fe8c2806 WD	84
	85
	86	cpu_init_crit:
	87	/*
	88	* mask all IRQs
	89	*/
	90	ldr r0, IC_BASE
	91	mov r1, #0x00
	92	str r1, [r0, #ICMR]
	93
	94	/* set clock speed */
	95	ldr r0, PWR_BASE
	96	ldr r1, cpuspeed
	97	str r1, [r0, #PPCR]
	98
	99	/*
	100	* before relocating, we have to setup RAM timing
	101	* because memory timing is board-dependend, you will
400558b5	102	* find a lowlevel_init.S in your board directory.
fe8c2806 WD	103	*/
fe8c2806 WD	104	mov ip, lr
400558b5	105	bl lowlevel_init
fe8c2806 WD	106	mov lr, ip
	107
	108	/*
	109	* disable MMU stuff and enable I-cache
	110	*/
	111	mrc p15,0,r0,c1,c0
	112	bic r0, r0, #0x00002000 @ clear bit 13 (X)
	113	bic r0, r0, #0x0000000f @ clear bits 3-0 (WCAM)
	114	orr r0, r0, #0x00001000 @ set bit 12 (I) Icache
	115	orr r0, r0, #0x00000002 @ set bit 2 (A) Align
	116	mcr p15,0,r0,c1,c0
	117
	118	/*
	119	* flush v4 I/D caches
	120	*/
	121	mov r0, #0
	122	mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
	123	mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
	124
	125	mov pc, lr