[u-boot.git] / arch / arm / cpu / armv7 / start.S

/*
 * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
 *
 * Copyright (c) 2004	Texas Instruments <[email protected]>
 *
 * Copyright (c) 2001	Marius Gröger <[email protected]>
 * Copyright (c) 2002	Alex Züpke <[email protected]>
 * Copyright (c) 2002	Gary Jennejohn <[email protected]>
 * Copyright (c) 2003	Richard Woodruff <[email protected]>
 * Copyright (c) 2003	Kshitij <[email protected]>
 * Copyright (c) 2006-2008 Syed Mohammed Khasim <[email protected]>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <asm-offsets.h>
#include <config.h>
#include <asm/system.h>
#include <linux/linkage.h>

/*************************************************************************
 *
 * Startup Code (reset vector)
 *
 * do important init only if we don't start from memory!
 * setup Memory and board specific bits prior to relocation.
 * relocate armboot to ram
 * setup stack
 *
 *************************************************************************/

	.globl	reset
	.globl	save_boot_params_ret

reset:
	/* Allow the board to save important registers */
	b	save_boot_params
save_boot_params_ret:
	/*
	 * disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode,
	 * except if in HYP mode already
	 */
	mrs	r0, cpsr
	and	r1, r0, #0x1f		@ mask mode bits
	teq	r1, #0x1a		@ test for HYP mode
	bicne	r0, r0, #0x1f		@ clear all mode bits
	orrne	r0, r0, #0x13		@ set SVC mode
	orr	r0, r0, #0xc0		@ disable FIQ and IRQ
	msr	cpsr,r0

/*
 * Setup vector:
 * (OMAP4 spl TEXT_BASE is not 32 byte aligned.
 * Continue to use ROM code vector only in OMAP4 spl)
 */
#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
	/* Set V=0 in CP15 SCTLR register - for VBAR to point to vector */
	mrc	p15, 0, r0, c1, c0, 0	@ Read CP15 SCTLR Register
	bic	r0, #CR_V		@ V = 0
	mcr	p15, 0, r0, c1, c0, 0	@ Write CP15 SCTLR Register

	/* Set vector address in CP15 VBAR register */
	ldr	r0, =_start
	mcr	p15, 0, r0, c12, c0, 0	@Set VBAR
#endif

	/* the mask ROM code should have PLL and others stable */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
	bl	cpu_init_cp15
	bl	cpu_init_crit
#endif

	bl	_main

/*------------------------------------------------------------------------------*/

ENTRY(c_runtime_cpu_setup)
/*
 * If I-cache is enabled invalidate it
 */
#ifndef CONFIG_SYS_ICACHE_OFF
	mcr	p15, 0, r0, c7, c5, 0	@ invalidate icache
	mcr     p15, 0, r0, c7, c10, 4	@ DSB
	mcr     p15, 0, r0, c7, c5, 4	@ ISB
#endif

	bx	lr

ENDPROC(c_runtime_cpu_setup)

/*************************************************************************
 *
 * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
 *	__attribute__((weak));
 *
 * Stack pointer is not yet initialized at this moment
 * Don't save anything to stack even if compiled with -O0
 *
 *************************************************************************/
ENTRY(save_boot_params)
	b	save_boot_params_ret		@ back to my caller
ENDPROC(save_boot_params)
	.weak	save_boot_params

/*************************************************************************
 *
 * cpu_init_cp15
 *
 * Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless
 * CONFIG_SYS_ICACHE_OFF is defined.
 *
 *************************************************************************/
ENTRY(cpu_init_cp15)
	/*
	 * Invalidate L1 I/D
	 */
	mov	r0, #0			@ set up for MCR
	mcr	p15, 0, r0, c8, c7, 0	@ invalidate TLBs
	mcr	p15, 0, r0, c7, c5, 0	@ invalidate icache
	mcr	p15, 0, r0, c7, c5, 6	@ invalidate BP array
	mcr     p15, 0, r0, c7, c10, 4	@ DSB
	mcr     p15, 0, r0, c7, c5, 4	@ ISB

	/*
	 * disable MMU stuff and caches
	 */
	mrc	p15, 0, r0, c1, c0, 0
	bic	r0, r0, #0x00002000	@ clear bits 13 (--V-)
	bic	r0, r0, #0x00000007	@ clear bits 2:0 (-CAM)
	orr	r0, r0, #0x00000002	@ set bit 1 (--A-) Align
	orr	r0, r0, #0x00000800	@ set bit 11 (Z---) BTB
#ifdef CONFIG_SYS_ICACHE_OFF
	bic	r0, r0, #0x00001000	@ clear bit 12 (I) I-cache
#else
	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-cache
#endif
	mcr	p15, 0, r0, c1, c0, 0

#ifdef CONFIG_ARM_ERRATA_716044
	mrc	p15, 0, r0, c1, c0, 0	@ read system control register
	orr	r0, r0, #1 << 11	@ set bit #11
	mcr	p15, 0, r0, c1, c0, 0	@ write system control register
#endif

#if (defined(CONFIG_ARM_ERRATA_742230) || defined(CONFIG_ARM_ERRATA_794072))
	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
	orr	r0, r0, #1 << 4		@ set bit #4
	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
#endif

#ifdef CONFIG_ARM_ERRATA_743622
	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
	orr	r0, r0, #1 << 6		@ set bit #6
	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
#endif

#ifdef CONFIG_ARM_ERRATA_751472
	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
	orr	r0, r0, #1 << 11	@ set bit #11
	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
#endif
#ifdef CONFIG_ARM_ERRATA_761320
	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
	orr	r0, r0, #1 << 21	@ set bit #21
	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
#endif

	mov	r5, lr			@ Store my Caller
	mrc	p15, 0, r1, c0, c0, 0	@ r1 has Read Main ID Register (MIDR)
	mov	r3, r1, lsr #20		@ get variant field
	and	r3, r3, #0xf		@ r3 has CPU variant
	and	r4, r1, #0xf		@ r4 has CPU revision
	mov	r2, r3, lsl #4		@ shift variant field for combined value
	orr	r2, r4, r2		@ r2 has combined CPU variant + revision

#ifdef CONFIG_ARM_ERRATA_798870
	cmp	r2, #0x30		@ Applies to lower than R3p0
	bge	skip_errata_798870      @ skip if not affected rev
	cmp	r2, #0x20		@ Applies to including and above R2p0
	blt	skip_errata_798870      @ skip if not affected rev

	mrc	p15, 1, r0, c15, c0, 0  @ read l2 aux ctrl reg
	orr	r0, r0, #1 << 7         @ Enable hazard-detect timeout
	push	{r1-r5}			@ Save the cpu info registers
	bl	v7_arch_cp15_set_l2aux_ctrl
	isb				@ Recommended ISB after l2actlr update
	pop	{r1-r5}			@ Restore the cpu info - fall through
skip_errata_798870:
#endif

#ifdef CONFIG_ARM_ERRATA_454179
	cmp	r2, #0x21		@ Only on < r2p1
	bge	skip_errata_454179

	mrc	p15, 0, r0, c1, c0, 1	@ Read ACR
	orr	r0, r0, #(0x3 << 6)	@ Set DBSM(BIT7) and IBE(BIT6) bits
	push	{r1-r5}			@ Save the cpu info registers
	bl	v7_arch_cp15_set_acr
	pop	{r1-r5}			@ Restore the cpu info - fall through

skip_errata_454179:
#endif

#ifdef CONFIG_ARM_ERRATA_430973
	cmp	r2, #0x21		@ Only on < r2p1
	bge	skip_errata_430973

	mrc	p15, 0, r0, c1, c0, 1	@ Read ACR
	orr	r0, r0, #(0x1 << 6)	@ Set IBE bit
	push	{r1-r5}			@ Save the cpu info registers
	bl	v7_arch_cp15_set_acr
	pop	{r1-r5}			@ Restore the cpu info - fall through

skip_errata_430973:
#endif

#ifdef CONFIG_ARM_ERRATA_621766
	cmp	r2, #0x21		@ Only on < r2p1
	bge	skip_errata_621766

	mrc	p15, 0, r0, c1, c0, 1	@ Read ACR
	orr	r0, r0, #(0x1 << 5)	@ Set L1NEON bit
	push	{r1-r5}			@ Save the cpu info registers
	bl	v7_arch_cp15_set_acr
	pop	{r1-r5}			@ Restore the cpu info - fall through

skip_errata_621766:
#endif

	mov	pc, r5			@ back to my caller
ENDPROC(cpu_init_cp15)

#ifndef CONFIG_SKIP_LOWLEVEL_INIT
/*************************************************************************
 *
 * CPU_init_critical registers
 *
 * setup important registers
 * setup memory timing
 *
 *************************************************************************/
ENTRY(cpu_init_crit)
	/*
	 * Jump to board specific initialization...
	 * The Mask ROM will have already initialized
	 * basic memory. Go here to bump up clock rate and handle
	 * wake up conditions.
	 */
	b	lowlevel_init		@ go setup pll,mux,memory
ENDPROC(cpu_init_crit)
#endif
Commit	Line	Data
0b02b184 DB	1	/*
	2	* armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
	3	*
	4	* Copyright (c) 2004 Texas Instruments <[email protected]>
	5	*
	6	* Copyright (c) 2001 Marius Gröger <[email protected]>
	7	* Copyright (c) 2002 Alex Züpke <[email protected]>
792a09eb	8	* Copyright (c) 2002 Gary Jennejohn <[email protected]>
0b02b184 DB	9	* Copyright (c) 2003 Richard Woodruff <[email protected]>
	10	* Copyright (c) 2003 Kshitij <[email protected]>
	11	* Copyright (c) 2006-2008 Syed Mohammed Khasim <[email protected]>
	12	*
3765b3e7	13	* SPDX-License-Identifier: GPL-2.0+
0b02b184 DB	14	*/
0b02b184 DB	15
25ddd1fb	16	#include <asm-offsets.h>
0b02b184	17	#include <config.h>
a8c68639	18	#include <asm/system.h>
74236aca	19	#include <linux/linkage.h>
0b02b184	20
0b02b184 DB	21	/*************************************************************************
	22	*
	23	* Startup Code (reset vector)
	24	*
	25	* do important init only if we don't start from memory!
	26	* setup Memory and board specific bits prior to relocation.
	27	* relocate armboot to ram
	28	* setup stack
	29	*
	30	*************************************************************************/
	31
41623c91	32	.globl reset
e11c6c27	33	.globl save_boot_params_ret
561142af HS	34
561142af HS	35	reset:
e11c6c27 SG	36	/* Allow the board to save important registers */
	37	b save_boot_params
	38	save_boot_params_ret:
561142af	39	/*
c4a4e2e2 AP	40	* disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode,
c4a4e2e2 AP	41	* except if in HYP mode already
561142af HS	42	*/
561142af HS	43	mrs r0, cpsr
c4a4e2e2 AP	44	and r1, r0, #0x1f @ mask mode bits
	45	teq r1, #0x1a @ test for HYP mode
	46	bicne r0, r0, #0x1f @ clear all mode bits
	47	orrne r0, r0, #0x13 @ set SVC mode
	48	orr r0, r0, #0xc0 @ disable FIQ and IRQ
561142af HS	49	msr cpsr,r0
561142af HS	50
a8c68639 A	51	/*
	52	* Setup vector:
	53	* (OMAP4 spl TEXT_BASE is not 32 byte aligned.
	54	* Continue to use ROM code vector only in OMAP4 spl)
	55	*/
840fe95c	56	#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
0f274f53 PF	57	/* Set V=0 in CP15 SCTLR register - for VBAR to point to vector */
0f274f53 PF	58	mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTLR Register
a8c68639	59	bic r0, #CR_V @ V = 0
0f274f53	60	mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTLR Register
a8c68639 A	61
	62	/* Set vector address in CP15 VBAR register */
	63	ldr r0, =_start
	64	mcr p15, 0, r0, c12, c0, 0 @Set VBAR
	65	#endif
	66
561142af HS	67	/* the mask ROM code should have PLL and others stable */
561142af HS	68	#ifndef CONFIG_SKIP_LOWLEVEL_INIT
80433c9a	69	bl cpu_init_cp15
561142af HS	70	bl cpu_init_crit
	71	#endif
	72
e05e5de7	73	bl _main
561142af HS	74
	75	/------------------------------------------------------------------------------/
	76
e05e5de7	77	ENTRY(c_runtime_cpu_setup)
c2dd0d45 A	78	/*
	79	* If I-cache is enabled invalidate it
	80	*/
	81	#ifndef CONFIG_SYS_ICACHE_OFF
	82	mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
	83	mcr p15, 0, r0, c7, c10, 4 @ DSB
	84	mcr p15, 0, r0, c7, c5, 4 @ ISB
	85	#endif
f8b9d1d3	86
e05e5de7 AA	87	bx lr
	88
	89	ENDPROC(c_runtime_cpu_setup)
c3d3a541	90
6f0dba85 TK	91	/*************************************************************************
	92	*
	93	* void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
	94	* __attribute__((weak));
	95	*
	96	* Stack pointer is not yet initialized at this moment
	97	* Don't save anything to stack even if compiled with -O0
	98	*
	99	*************************************************************************/
	100	ENTRY(save_boot_params)
e11c6c27	101	b save_boot_params_ret @ back to my caller
6f0dba85 TK	102	ENDPROC(save_boot_params)
	103	.weak save_boot_params
	104
0b02b184 DB	105	/*************************************************************************
0b02b184 DB	106	*
80433c9a	107	* cpu_init_cp15
0b02b184	108	*
80433c9a SG	109	* Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless
80433c9a SG	110	* CONFIG_SYS_ICACHE_OFF is defined.
0b02b184 DB	111	*
0b02b184 DB	112	*************************************************************************/
74236aca	113	ENTRY(cpu_init_cp15)
0b02b184 DB	114	/*
	115	* Invalidate L1 I/D
	116	*/
	117	mov r0, #0 @ set up for MCR
	118	mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
	119	mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
c2dd0d45 A	120	mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array
	121	mcr p15, 0, r0, c7, c10, 4 @ DSB
	122	mcr p15, 0, r0, c7, c5, 4 @ ISB
0b02b184 DB	123
	124	/*
	125	* disable MMU stuff and caches
	126	*/
	127	mrc p15, 0, r0, c1, c0, 0
	128	bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
	129	bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
	130	orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
c2dd0d45 A	131	orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB
	132	#ifdef CONFIG_SYS_ICACHE_OFF
	133	bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache
	134	#else
	135	orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache
	136	#endif
0b02b184	137	mcr p15, 0, r0, c1, c0, 0
0678587f	138
c5d4752c SW	139	#ifdef CONFIG_ARM_ERRATA_716044
	140	mrc p15, 0, r0, c1, c0, 0 @ read system control register
	141	orr r0, r0, #1 << 11 @ set bit #11
	142	mcr p15, 0, r0, c1, c0, 0 @ write system control register
	143	#endif
	144
f71cbfe3	145	#if (defined(CONFIG_ARM_ERRATA_742230) \|\| defined(CONFIG_ARM_ERRATA_794072))
0678587f SW	146	mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
	147	orr r0, r0, #1 << 4 @ set bit #4
	148	mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
	149	#endif
	150
	151	#ifdef CONFIG_ARM_ERRATA_743622
	152	mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
	153	orr r0, r0, #1 << 6 @ set bit #6
	154	mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
	155	#endif
	156
	157	#ifdef CONFIG_ARM_ERRATA_751472
	158	mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
	159	orr r0, r0, #1 << 11 @ set bit #11
	160	mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
	161	#endif
b7588e3b NG	162	#ifdef CONFIG_ARM_ERRATA_761320
	163	mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
	164	orr r0, r0, #1 << 21 @ set bit #21
	165	mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
	166	#endif
0678587f	167
c616a0df NM	168	mov r5, lr @ Store my Caller
	169	mrc p15, 0, r1, c0, c0, 0 @ r1 has Read Main ID Register (MIDR)
	170	mov r3, r1, lsr #20 @ get variant field
	171	and r3, r3, #0xf @ r3 has CPU variant
	172	and r4, r1, #0xf @ r4 has CPU revision
	173	mov r2, r3, lsl #4 @ shift variant field for combined value
	174	orr r2, r4, r2 @ r2 has combined CPU variant + revision
	175
	176	#ifdef CONFIG_ARM_ERRATA_798870
	177	cmp r2, #0x30 @ Applies to lower than R3p0
	178	bge skip_errata_798870 @ skip if not affected rev
	179	cmp r2, #0x20 @ Applies to including and above R2p0
	180	blt skip_errata_798870 @ skip if not affected rev
	181
	182	mrc p15, 1, r0, c15, c0, 0 @ read l2 aux ctrl reg
	183	orr r0, r0, #1 << 7 @ Enable hazard-detect timeout
	184	push {r1-r5} @ Save the cpu info registers
	185	bl v7_arch_cp15_set_l2aux_ctrl
	186	isb @ Recommended ISB after l2actlr update
	187	pop {r1-r5} @ Restore the cpu info - fall through
	188	skip_errata_798870:
b45c48a7 NM	189	#endif
	190
	191	#ifdef CONFIG_ARM_ERRATA_454179
	192	cmp r2, #0x21 @ Only on < r2p1
	193	bge skip_errata_454179
	194
	195	mrc p15, 0, r0, c1, c0, 1 @ Read ACR
	196	orr r0, r0, #(0x3 << 6) @ Set DBSM(BIT7) and IBE(BIT6) bits
	197	push {r1-r5} @ Save the cpu info registers
	198	bl v7_arch_cp15_set_acr
	199	pop {r1-r5} @ Restore the cpu info - fall through
	200
	201	skip_errata_454179:
5902f4ce NM	202	#endif
	203
	204	#ifdef CONFIG_ARM_ERRATA_430973
	205	cmp r2, #0x21 @ Only on < r2p1
	206	bge skip_errata_430973
	207
	208	mrc p15, 0, r0, c1, c0, 1 @ Read ACR
	209	orr r0, r0, #(0x1 << 6) @ Set IBE bit
	210	push {r1-r5} @ Save the cpu info registers
	211	bl v7_arch_cp15_set_acr
	212	pop {r1-r5} @ Restore the cpu info - fall through
	213
	214	skip_errata_430973:
9b4d65f9 NM	215	#endif
	216
	217	#ifdef CONFIG_ARM_ERRATA_621766
	218	cmp r2, #0x21 @ Only on < r2p1
	219	bge skip_errata_621766
	220
	221	mrc p15, 0, r0, c1, c0, 1 @ Read ACR
	222	orr r0, r0, #(0x1 << 5) @ Set L1NEON bit
	223	push {r1-r5} @ Save the cpu info registers
	224	bl v7_arch_cp15_set_acr
	225	pop {r1-r5} @ Restore the cpu info - fall through
	226
	227	skip_errata_621766:
c616a0df NM	228	#endif
	229
	230	mov pc, r5 @ back to my caller
74236aca	231	ENDPROC(cpu_init_cp15)
0b02b184	232
80433c9a SG	233	#ifndef CONFIG_SKIP_LOWLEVEL_INIT
	234	/*************************************************************************
	235	*
	236	* CPU_init_critical registers
	237	*
	238	* setup important registers
	239	* setup memory timing
	240	*
	241	*************************************************************************/
74236aca	242	ENTRY(cpu_init_crit)
0b02b184 DB	243	/*
	244	* Jump to board specific initialization...
	245	* The Mask ROM will have already initialized
	246	* basic memory. Go here to bump up clock rate and handle
	247	* wake up conditions.
	248	*/
63ee53a7	249	b lowlevel_init @ go setup pll,mux,memory
74236aca	250	ENDPROC(cpu_init_crit)
22193540	251	#endif