[u-boot.git] / arch / arm / cpu / arm926ejs / mxs / start.S

/*
 *  armboot - Startup Code for ARM926EJS CPU-core
 *
 *  Copyright (c) 2003  Texas Instruments
 *
 *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
 *
 *  Copyright (c) 2001	Marius Groger <[email protected]>
 *  Copyright (c) 2002	Alex Zupke <[email protected]>
 *  Copyright (c) 2002	Gary Jennejohn <[email protected]>
 *  Copyright (c) 2003	Richard Woodruff <[email protected]>
 *  Copyright (c) 2003	Kshitij <[email protected]>
 *  Copyright (c) 2010	Albert Aribaud <[email protected]>
 *
 * Change to support call back into iMX28 bootrom
 * Copyright (c) 2011 Marek Vasut <[email protected]>
 * on behalf of DENX Software Engineering GmbH
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <asm-offsets.h>
#include <config.h>
#include <common.h>

/*
 *************************************************************************
 *
 * Startup Code (reset vector)
 *
 * do important init only if we don't start from memory!
 * setup Memory and board specific bits prior to relocation.
 * relocate armboot to ram
 * setup stack
 *
 *************************************************************************
 */

	.globl	reset
reset:
	/*
	 * If the CPU is configured in "Wait JTAG connection mode", the stack
	 * pointer is not configured and is zero. This will cause crash when
	 * trying to push data onto stack right below here. Load the SP and make
	 * it point to the end of OCRAM if the SP is zero.
	 */
	cmp	sp, #0x00000000
	ldreq	sp, =CONFIG_SYS_INIT_SP_ADDR

	/*
	 * Store all registers on old stack pointer, this will allow us later to
	 * return to the BootROM and let the BootROM load U-Boot into RAM.
	 *
	 * WARNING: Register r0 and r1 are used by the BootROM to pass data
	 *          to the called code. Register r0 will contain arbitrary
	 *          data that are set in the BootStream. In case this code
	 *          was started with CALL instruction, register r1 will contain
	 *          pointer to the return value this function can then set.
	 *          The code below MUST NOT CHANGE register r0 and r1 !
	 */
	push	{r0-r12,r14}

	/* Save control register c1 */
	mrc	p15, 0, r2, c1, c0, 0
	push	{r2}

	/* Set the cpu to SVC32 mode and store old CPSR register content. */
	mrs	r2, cpsr
	push	{r2}
	bic	r2, r2, #0x1f
	orr	r2, r2, #0xd3
	msr	cpsr, r2

	bl	board_init_ll

	/* Restore BootROM's CPU mode (especially FIQ). */
	pop	{r2}
	msr	cpsr,r2

	/*
	 * Restore c1 register. Especially set exception vector location
	 * back to BootROM space which is required by bootrom for USB boot.
	 */
	pop	{r2}
	mcr	p15, 0, r2, c1, c0, 0

	pop	{r0-r12,r14}

	/*
	 * In case this code was started by the CALL instruction, the register
	 * r0 is examined by the BootROM after this code returns. The value in
	 * r0 must be set to 0 to indicate successful return.
	 */
	mov r0, #0

	bx	lr
Commit	Line	Data
04fe4273 MV	1	/*
	2	* armboot - Startup Code for ARM926EJS CPU-core
	3	*
	4	* Copyright (c) 2003 Texas Instruments
	5	*
	6	* ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
	7	*
	8	* Copyright (c) 2001 Marius Groger <[email protected]>
	9	* Copyright (c) 2002 Alex Zupke <[email protected]>
	10	* Copyright (c) 2002 Gary Jennejohn <[email protected]>
	11	* Copyright (c) 2003 Richard Woodruff <[email protected]>
	12	* Copyright (c) 2003 Kshitij <[email protected]>
	13	* Copyright (c) 2010 Albert Aribaud <[email protected]>
	14	*
	15	* Change to support call back into iMX28 bootrom
	16	* Copyright (c) 2011 Marek Vasut <[email protected]>
	17	* on behalf of DENX Software Engineering GmbH
	18	*
1a459660	19	* SPDX-License-Identifier: GPL-2.0+
04fe4273 MV	20	*/
	21
	22	#include <asm-offsets.h>
	23	#include <config.h>
	24	#include <common.h>
04fe4273	25
04fe4273 MV	26	/*
	27	*************************************************************************
	28	*
	29	* Startup Code (reset vector)
	30	*
	31	* do important init only if we don't start from memory!
	32	* setup Memory and board specific bits prior to relocation.
	33	* relocate armboot to ram
	34	* setup stack
	35	*
	36	*************************************************************************
	37	*/
	38
41623c91 AA	39	.globl reset
41623c91 AA	40	reset:
77b0e223 MV	41	/*
	42	* If the CPU is configured in "Wait JTAG connection mode", the stack
	43	* pointer is not configured and is zero. This will cause crash when
	44	* trying to push data onto stack right below here. Load the SP and make
	45	* it point to the end of OCRAM if the SP is zero.
	46	*/
	47	cmp sp, #0x00000000
	48	ldreq sp, =CONFIG_SYS_INIT_SP_ADDR
	49
04fe4273 MV	50	/*
	51	* Store all registers on old stack pointer, this will allow us later to
	52	* return to the BootROM and let the BootROM load U-Boot into RAM.
7b8657e2 MV	53	*
	54	* WARNING: Register r0 and r1 are used by the BootROM to pass data
	55	* to the called code. Register r0 will contain arbitrary
	56	* data that are set in the BootStream. In case this code
	57	* was started with CALL instruction, register r1 will contain
	58	* pointer to the return value this function can then set.
	59	* The code below MUST NOT CHANGE register r0 and r1 !
04fe4273 MV	60	*/
	61	push {r0-r12,r14}
	62
7b8657e2 MV	63	/* Save control register c1 */
	64	mrc p15, 0, r2, c1, c0, 0
	65	push {r2}
61698fd5	66
7b8657e2 MV	67	/* Set the cpu to SVC32 mode and store old CPSR register content. */
	68	mrs r2, cpsr
	69	push {r2}
	70	bic r2, r2, #0x1f
	71	orr r2, r2, #0xd3
	72	msr cpsr, r2
04fe4273	73
04fe4273 MV	74	bl board_init_ll
04fe4273 MV	75
7b8657e2 MV	76	/* Restore BootROM's CPU mode (especially FIQ). */
	77	pop {r2}
	78	msr cpsr,r2
	79
61698fd5	80	/*
7b8657e2 MV	81	* Restore c1 register. Especially set exception vector location
7b8657e2 MV	82	* back to BootROM space which is required by bootrom for USB boot.
61698fd5	83	*/
7b8657e2 MV	84	pop {r2}
	85	mcr p15, 0, r2, c1, c0, 0
	86
	87	pop {r0-r12,r14}
61698fd5 MF	88
61698fd5 MF	89	/*
7b8657e2 MV	90	* In case this code was started by the CALL instruction, the register
	91	* r0 is examined by the BootROM after this code returns. The value in
	92	* r0 must be set to 0 to indicate successful return.
61698fd5	93	*/
7b8657e2	94	mov r0, #0
61698fd5	95
04fe4273	96	bx lr