projects / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 8ed96046 WD |
1 | /* |
| 2 | * armboot - Startup Code for OMP2420/ARM1136 CPU-core | |
| 3 | * | |
| 082acfd4 | 4 | * Copyright (c) 2004 Texas Instruments <[email protected]> |
| 8ed96046 | 5 | * |
| fa82f871 AA |
6 | * Copyright (c) 2001 Marius Gröger <[email protected]> |
| 7 | * Copyright (c) 2002 Alex Züpke <[email protected]> | |
| 792a09eb | 8 | * Copyright (c) 2002 Gary Jennejohn <[email protected]> |
| 8ed96046 WD |
9 | * Copyright (c) 2003 Richard Woodruff <[email protected]> |
| 10 | * Copyright (c) 2003 Kshitij <[email protected]> | |
| 11 | * | |
| 3765b3e7 | 12 | * SPDX-License-Identifier: GPL-2.0+ |
| 8ed96046 WD |
13 | */ |
| 14 | ||
| 25ddd1fb | 15 | #include <asm-offsets.h> |
| 8ed96046 | 16 | #include <config.h> |
| 751b9b51 | 17 | |
| 8ed96046 WD |
18 | /* |
| 19 | ************************************************************************* | |
| 20 | * | |
| 21 | * Startup Code (reset vector) | |
| 22 | * | |
| 23 | * do important init only if we don't start from memory! | |
| 24 | * setup Memory and board specific bits prior to relocation. | |
| 25 | * relocate armboot to ram | |
| 26 | * setup stack | |
| 27 | * | |
| 28 | ************************************************************************* | |
| 29 | */ | |
| 30 | ||
| 41623c91 | 31 | .globl reset |
| e48b7c0a HS |
32 | |
| 33 | reset: | |
| 34 | /* | |
| 35 | * set the cpu to SVC32 mode | |
| 36 | */ | |
| 37 | mrs r0,cpsr | |
| 38 | bic r0,r0,#0x1f | |
| 39 | orr r0,r0,#0xd3 | |
| 40 | msr cpsr,r0 | |
| 41 | ||
| e48b7c0a HS |
42 | /* the mask ROM code should have PLL and others stable */ |
| 43 | #ifndef CONFIG_SKIP_LOWLEVEL_INIT | |
| 44 | bl cpu_init_crit | |
| 45 | #endif | |
| 46 | ||
| e05e5de7 | 47 | bl _main |
| e48b7c0a HS |
48 | |
| 49 | /*------------------------------------------------------------------------------*/ | |
| 50 | ||
| e05e5de7 AA |
51 | .globl c_runtime_cpu_setup |
| 52 | c_runtime_cpu_setup: | |
| e48b7c0a | 53 | |
| e05e5de7 | 54 | bx lr |
| bafe7437 | 55 | |
| 8ed96046 WD |
56 | /* |
| 57 | ************************************************************************* | |
| 58 | * | |
| 59 | * CPU_init_critical registers | |
| 60 | * | |
| 61 | * setup important registers | |
| 62 | * setup memory timing | |
| 63 | * | |
| 64 | ************************************************************************* | |
| 65 | */ | |
| 40c642bc | 66 | #ifndef CONFIG_SKIP_LOWLEVEL_INIT |
| 8ed96046 WD |
67 | cpu_init_crit: |
| 68 | /* | |
| 69 | * flush v4 I/D caches | |
| 70 | */ | |
| 71 | mov r0, #0 | |
| 409a07c9 GD |
72 | mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */ |
| 73 | mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */ | |
| 8ed96046 WD |
74 | |
| 75 | /* | |
| 76 | * disable MMU stuff and caches | |
| 77 | */ | |
| 78 | mrc p15, 0, r0, c1, c0, 0 | |
| 79 | bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) | |
| 80 | bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) | |
| 81 | orr r0, r0, #0x00000002 @ set bit 2 (A) Align | |
| 8ed96046 | 82 | orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache |
| 8ed96046 WD |
83 | mcr p15, 0, r0, c1, c0, 0 |
| 84 | ||
| 85 | /* | |
| 082acfd4 WD |
86 | * Jump to board specific initialization... The Mask ROM will have already initialized |
| 87 | * basic memory. Go here to bump up clock rate and handle wake up conditions. | |
| 8ed96046 | 88 | */ |
| 082acfd4 | 89 | mov ip, lr /* persevere link reg across call */ |
| 87cb6862 | 90 | bl lowlevel_init /* go setup pll,mux,memory */ |
| 082acfd4 WD |
91 | mov lr, ip /* restore link */ |
| 92 | mov pc, lr /* back to my caller */ | |
| 40c642bc | 93 | #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ |