projects / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 024a26bc WD |
1 | /* |
| 2 | * (C) Copyright 2002 | |
| 3 | * Rich Ireland, Enterasys Networks, [email protected]. | |
| 4 | * | |
| 5 | * See file CREDITS for list of people who contributed to this | |
| 6 | * project. | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or | |
| 9 | * modify it under the terms of the GNU General Public License as | |
| 10 | * published by the Free Software Foundation; either version 2 of | |
| 11 | * the License, or (at your option) any later version. | |
| 12 | * | |
| 13 | * This program is distributed in the hope that it will be useful, | |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | * GNU General Public License for more details. | |
| 17 | * | |
| 18 | * You should have received a copy of the GNU General Public License | |
| 19 | * along with this program; if not, write to the Free Software | |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 21 | * MA 02111-1307 USA | |
| 22 | * | |
| 23 | */ | |
| 24 | ||
| 53677ef1 | 25 | #include <linux/types.h> /* for ulong typedef */ |
| 024a26bc WD |
26 | |
| 27 | #ifndef _FPGA_H_ | |
| 28 | #define _FPGA_H_ | |
| 29 | ||
| 30 | #ifndef CONFIG_MAX_FPGA_DEVICES | |
| 31 | #define CONFIG_MAX_FPGA_DEVICES 5 | |
| 32 | #endif | |
| 33 | ||
| 34 | /* these probably belong somewhere else */ | |
| 35 | #ifndef FALSE | |
| 53677ef1 | 36 | #define FALSE (0) |
| 024a26bc WD |
37 | #endif |
| 38 | #ifndef TRUE | |
| 53677ef1 | 39 | #define TRUE (!FALSE) |
| 024a26bc WD |
40 | #endif |
| 41 | ||
| 42 | /* CONFIG_FPGA bit assignments */ | |
| 6d0f6bcf JCPV |
43 | #define CONFIG_SYS_FPGA_MAN(x) (x) |
| 44 | #define CONFIG_SYS_FPGA_DEV(x) ((x) << 8 ) | |
| 45 | #define CONFIG_SYS_FPGA_IF(x) ((x) << 16 ) | |
| 024a26bc WD |
46 | |
| 47 | /* FPGA Manufacturer bits in CONFIG_FPGA */ | |
| 6d0f6bcf JCPV |
48 | #define CONFIG_SYS_FPGA_XILINX CONFIG_SYS_FPGA_MAN( 0x1 ) |
| 49 | #define CONFIG_SYS_FPGA_ALTERA CONFIG_SYS_FPGA_MAN( 0x2 ) | |
| 024a26bc WD |
50 | |
| 51 | ||
| 52 | /* fpga_xxxx function return value definitions */ | |
| 53677ef1 WD |
53 | #define FPGA_SUCCESS 0 |
| 54 | #define FPGA_FAIL -1 | |
| 024a26bc WD |
55 | |
| 56 | /* device numbers must be non-negative */ | |
| 53677ef1 | 57 | #define FPGA_INVALID_DEVICE -1 |
| 024a26bc WD |
58 | |
| 59 | /* root data type defintions */ | |
| 53677ef1 WD |
60 | typedef enum { /* typedef fpga_type */ |
| 61 | fpga_min_type, /* range check value */ | |
| 62 | fpga_xilinx, /* Xilinx Family) */ | |
| 63 | fpga_altera, /* unimplemented */ | |
| 3b8ac464 | 64 | fpga_lattice, /* Lattice family */ |
| 53677ef1 WD |
65 | fpga_undefined /* invalid range check value */ |
| 66 | } fpga_type; /* end, typedef fpga_type */ | |
| 024a26bc | 67 | |
| 53677ef1 WD |
68 | typedef struct { /* typedef fpga_desc */ |
| 69 | fpga_type devtype; /* switch value to select sub-functions */ | |
| 70 | void *devdesc; /* real device descriptor */ | |
| 71 | } fpga_desc; /* end, typedef fpga_desc */ | |
| 024a26bc WD |
72 | |
| 73 | ||
| 74 | /* root function definitions */ | |
| e6a857da WD |
75 | extern void fpga_init(void); |
| 76 | extern int fpga_add(fpga_type devtype, void *desc); | |
| 77 | extern int fpga_count(void); | |
| 78 | extern int fpga_load(int devnum, const void *buf, size_t bsize); | |
| 79 | extern int fpga_dump(int devnum, const void *buf, size_t bsize); | |
| 80 | extern int fpga_info(int devnum); | |
| 024a26bc WD |
81 | |
| 82 | #endif /* _FPGA_H_ */ |