]>
Commit | Line | Data |
---|---|---|
73a8b27c WD |
1 | /* |
2 | * (C) Copyright 2000 | |
3 | * Wolfgang Denk, DENX Software Engineering, [email protected]. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | ||
25 | #include <common.h> | |
26 | #include <mpc8xx.h> | |
27 | ||
28 | /* ------------------------------------------------------------------------- */ | |
29 | ||
30 | static long int dram_size (long int, long int *, long int); | |
31 | ||
32 | /* ------------------------------------------------------------------------- */ | |
33 | ||
34 | #define _NOT_USED_ 0xFFFFCC25 | |
35 | ||
36 | const uint sdram_table[] = | |
37 | { | |
38 | /* | |
39 | * Single Read. (Offset 00h in UPMA RAM) | |
40 | */ | |
41 | 0x0F03CC04, 0x00ACCC24, 0x1FF74C20, _NOT_USED_, | |
42 | _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, | |
43 | ||
44 | /* | |
45 | * Burst Read. (Offset 08h in UPMA RAM) | |
46 | */ | |
47 | 0x0F03CC04, 0x00ACCC24, 0x00FFCC20, 0x00FFCC20, | |
48 | 0x01FFCC20, 0x1FF74C20, _NOT_USED_, _NOT_USED_, | |
49 | _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, | |
50 | _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, | |
51 | ||
52 | /* | |
53 | * Single Write. (Offset 18h in UPMA RAM) | |
54 | */ | |
55 | 0x0F03CC02, 0x00AC0C24, 0x1FF74C25, _NOT_USED_, | |
56 | _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, | |
57 | ||
58 | /* | |
59 | * Burst Write. (Offset 20h in UPMA RAM) | |
60 | */ | |
61 | 0x0F03CC00, 0x00AC0C20, 0x00FFFC20, 0x00FFFC22, | |
62 | 0x01FFFC24, 0x1FF74C25, _NOT_USED_, _NOT_USED_, | |
63 | _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, | |
64 | _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, | |
65 | ||
66 | /* | |
67 | * Refresh. (Offset 30h in UPMA RAM) | |
68 | * (Initialization code at 0x36) | |
69 | */ | |
70 | 0x0FF0CC24, 0xFFFFCC24, _NOT_USED_, _NOT_USED_, | |
71 | _NOT_USED_, _NOT_USED_, 0xEFFB8C34, 0x0FF74C34, | |
1eaeb58e | 72 | 0x0FFACCB4, 0x0FF5CC34, 0x0FFFCC34, 0x0FFFCCB4, |
73a8b27c WD |
73 | |
74 | /* | |
75 | * Exception. (Offset 3Ch in UPMA RAM) | |
76 | */ | |
77 | 0x0FEA8C34, 0x1FB54C34, 0xFFFFCC34, _NOT_USED_ | |
78 | }; | |
79 | ||
80 | /* ------------------------------------------------------------------------- */ | |
81 | ||
82 | ||
83 | /* | |
84 | * Check Board Identity: | |
85 | */ | |
86 | ||
87 | int checkboard (void) | |
88 | { | |
89 | puts ("Board: RMU\n") ; | |
90 | return (0) ; | |
91 | } | |
92 | ||
93 | /* ------------------------------------------------------------------------- */ | |
94 | ||
9973e3c6 | 95 | phys_size_t initdram (int board_type) |
73a8b27c | 96 | { |
6d0f6bcf | 97 | volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
5fa66df6 WD |
98 | volatile memctl8xx_t *memctl = &immap->im_memctl; |
99 | long int size9; | |
73a8b27c | 100 | |
5fa66df6 WD |
101 | upmconfig (UPMA, (uint *) sdram_table, |
102 | sizeof (sdram_table) / sizeof (uint)); | |
73a8b27c WD |
103 | |
104 | /* Refresh clock prescalar */ | |
6d0f6bcf | 105 | memctl->memc_mptpr = CONFIG_SYS_MPTPR; |
73a8b27c | 106 | |
5fa66df6 | 107 | memctl->memc_mar = 0x00000088; |
73a8b27c WD |
108 | |
109 | /* Map controller banks 1 to the SDRAM bank */ | |
6d0f6bcf JCPV |
110 | memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; |
111 | memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; | |
73a8b27c | 112 | |
6d0f6bcf | 113 | memctl->memc_mamr = CONFIG_SYS_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */ |
73a8b27c | 114 | |
5fa66df6 | 115 | udelay (200); |
73a8b27c | 116 | |
5fa66df6 | 117 | /* perform SDRAM initializsation sequence */ |
73a8b27c | 118 | |
5fa66df6 WD |
119 | memctl->memc_mcr = 0x80002136; /* SDRAM bank 0 */ |
120 | udelay (1); | |
73a8b27c | 121 | |
5fa66df6 | 122 | memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ |
73a8b27c | 123 | |
5fa66df6 | 124 | udelay (1000); |
73a8b27c | 125 | |
d94f92cb WD |
126 | /* Check Bank 0 Memory Size, |
127 | * 9 column mode | |
73a8b27c WD |
128 | */ |
129 | ||
6d0f6bcf | 130 | size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE_PRELIM, |
5fa66df6 | 131 | SDRAM_MAX_SIZE); |
73a8b27c | 132 | |
d94f92cb WD |
133 | /* |
134 | * Final mapping: | |
135 | */ | |
136 | ||
6d0f6bcf | 137 | memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; |
d94f92cb WD |
138 | udelay (1000); |
139 | ||
5fa66df6 | 140 | return (size9); |
73a8b27c WD |
141 | } |
142 | ||
143 | /* ------------------------------------------------------------------------- */ | |
144 | ||
145 | /* | |
146 | * Check memory range for valid RAM. A simple memory test determines | |
147 | * the actually available RAM size between addresses `base' and | |
148 | * `base + maxsize'. Some (not all) hardware errors are detected: | |
149 | * - short between address lines | |
150 | * - short between data lines | |
151 | */ | |
152 | ||
5fa66df6 WD |
153 | static long int dram_size (long int mamr_value, long int *base, |
154 | long int maxsize) | |
73a8b27c | 155 | { |
6d0f6bcf | 156 | volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
5fa66df6 | 157 | volatile memctl8xx_t *memctl = &immap->im_memctl; |
73a8b27c | 158 | |
5fa66df6 | 159 | memctl->memc_mamr = mamr_value; |
73a8b27c | 160 | |
c83bf6a2 | 161 | return (get_ram_size(base, maxsize)); |
73a8b27c | 162 | } |