[u-boot.git] / include / configs / ELPPC.h

/*
 * (C) Copyright 2002 ELTEC Elektronik AG
 * Frank Gottschling <[email protected]>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define GTREGREAD(x) 0xffffffff         /* needed for debug */

/*
 * High Level Configuration Options
 * (easy to change)
 */

/* these hardware addresses are pretty bogus, please change them to
   suit your needs */

/* first ethernet */
#define CONFIG_ETHADDR          00:00:5b:ee:de:ad

#define CONFIG_IPADDR           192.168.0.105
#define CONFIG_SERVERIP         192.168.0.100

#define CONFIG_ELPPC            1       /* this is an BAB740/BAB750 board */

#define CONFIG_BAUDRATE         9600    /* console baudrate */

#undef  CONFIG_WATCHDOG

#define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */

#define CONFIG_ZERO_BOOTDELAY_CHECK

#undef  CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND                                  \
    "bootp 1000000; "                                       \
    "setenv bootargs root=ramfs console=ttyS00,9600 "       \
    "ip=${ipaddr}:${serverip}:${rootpath}:${gatewayip}:"    \
    "${netmask}:${hostname}:eth0:none; "                    \
    "bootm"

#define CONFIG_LOADS_ECHO       0       /* echo off for serial download */
#define CFG_LOADS_BAUD_CHANGE           /* allow baudrate changes */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH

#define CONFIG_BOOTP_BOOTFILESIZE


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_PCI
#define CONFIG_CMD_JFFS2


/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP                    /* undef to save memory */
#define CFG_PROMPT              "=> "   /* Monitor Command Prompt */

/*
 * choose between COM1 and COM2 as serial console
 */
#define CONFIG_CONS_INDEX       1

#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE              1024        /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE              256         /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS             16          /* max number of command args    */
#define CFG_BARGSIZE            CFG_CBSIZE  /* Boot Argument Buffer Size    */

#define CFG_MEMTEST_START       0x00000000  /* memtest works on    */
#define CFG_MEMTEST_END         0x04000000  /* 0 ... 64 MB in DRAM    */

#define CFG_LOAD_ADDR           0x1000000   /* default load address    */

#define CFG_HZ                  1000        /* dec. freq: 1 ms ticks */

#define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
#define CFG_BOARD_ASM_INIT
#define CONFIG_MISC_INIT_R

/*
 * Address mapping scheme for the MPC107 mem controller is mapping B (CHRP)
 */
#undef  CFG_ADDRESS_MAP_A

#define CFG_PCI_MEMORY_BUS      0x00000000
#define CFG_PCI_MEMORY_PHYS     0x00000000
#define CFG_PCI_MEMORY_SIZE     0x40000000

#define CFG_PCI_MEM_BUS         0x80000000
#define CFG_PCI_MEM_PHYS        0x80000000
#define CFG_PCI_MEM_SIZE        0x7d000000

#define CFG_ISA_MEM_BUS         0x00000000
#define CFG_ISA_MEM_PHYS        0xfd000000
#define CFG_ISA_MEM_SIZE        0x01000000

#define CFG_PCI_IO_BUS          0x00800000
#define CFG_PCI_IO_PHYS         0xfe800000
#define CFG_PCI_IO_SIZE         0x00400000

#define CFG_ISA_IO_BUS          0x00000000
#define CFG_ISA_IO_PHYS         0xfe000000
#define CFG_ISA_IO_SIZE         0x00800000

/* driver defines FDC,IDE,... */
#define CFG_ISA_IO_BASE_ADDRESS CFG_ISA_IO_PHYS
#define CFG_ISA_IO              CFG_ISA_IO_PHYS
#define CFG_60X_PCI_IO_OFFSET   CFG_ISA_IO_PHYS

/*
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define CFG_SDRAM_BASE          0x00000000

#define CFG_USR_LED_BASE        0x78000000
#define CFG_NVRAM_BASE          0xff000000
#define CFG_UART_BASE           0xff400000
#define CFG_FLASH_BASE          0xfff00000

#define MPC107_EUMB_ADDR        0xfce00000
#define MPC107_EUMB_PI          0xfce41090
#define MPC107_EUMB_GCR         0xfce41020
#define MPC107_EUMB_IACKR       0xfce600a0
#define MPC107_I2C_ADDR         0xfce03000

/*
 * Definitions for initial stack pointer and data area
 */
#define CFG_INIT_RAM_ADDR       0x00fd0000  /* above the memtest region */
#define CFG_INIT_RAM_END        0x4000
#define CFG_GBL_DATA_SIZE       64          /* size in bytes reserved for init data */
#define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET

/*
 * Flash mapping/organization on the MPC10x.
 */
#define FLASH_BASE0_PRELIM      0xff800000
#define FLASH_BASE1_PRELIM      0xffc00000

#define CFG_MAX_FLASH_BANKS     2           /* max number of memory banks    */
#define CFG_MAX_FLASH_SECT      67          /* max number of sectors on one chip */

#define CFG_FLASH_ERASE_TOUT    120000      /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT    500         /* Timeout for Flash Write (in ms) */

/*
 * JFFS2 partitions
 *
 */
/* No command line, one static partition, whole device */
#undef CONFIG_JFFS2_CMDLINE
#define CONFIG_JFFS2_DEV		"nor0"
#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
#define CONFIG_JFFS2_PART_OFFSET	0x00000000

/* mtdparts command line support */
/* Note: fake mtd_id used, no linux mtd map file */
/*
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT		"nor0=elppc-0,nor1=elppc-1"
#define MTDPARTS_DEFAULT	"mtdparts=elppc-0:-(jffs2),elppc-1:-(user)"
*/

#define CFG_MONITOR_BASE        CFG_FLASH_BASE
#define CFG_MONITOR_LEN         0x40000     /* Reserve 256 kB for Monitor */
#define CFG_MALLOC_LEN          0x20000     /* Reserve 128 kB for malloc() */
#undef  CFG_MEMTEST

/*
 * Environment settings
 */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_ENV_IS_IN_NVRAM     1           /* use NVRAM for environment vars */
#define CFG_NVRAM_SIZE          0x800       /* NVRAM size (2kB) */
#define CONFIG_ENV_SIZE            0x400       /* Size of Environment vars (1kB) */
#define CONFIG_ENV_ADDR            0x0
#define CONFIG_ENV_MAP_ADRS        0xff000000
#define CFG_NV_SROM_COPY_ADDR   (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
#define CFG_NVRAM_ACCESS_ROUTINE            /* only byte accsess alowed */
#define CFG_SROM_SIZE           0x100       /* shadow of revision info is in nvram */

/*
 * Serial devices
 */
#define CFG_NS16550
#define CFG_NS16550_SERIAL
#define CFG_NS16550_REG_SIZE    1
#define CFG_NS16550_CLK         24000000
#define CFG_NS16550_COM1        (CFG_UART_BASE + 0)
#define CFG_NS16550_COM2        (CFG_UART_BASE + 8)

/*
 * PCI stuff
 */
#define CONFIG_PCI                                /* include pci support */
#define CONFIG_PCI_PNP                            /* pci plug-and-play */
#define CONFIG_PCI_HOST         PCI_HOST_AUTO
#undef  CONFIG_PCI_SCAN_SHOW

/*
 * Optional Video console (graphic: SMI LynxEM)
 */
#define CONFIG_VIDEO
#define CONFIG_CFB_CONSOLE
#define VIDEO_KBD_INIT_FCT    (simple_strtol (getenv("console"), NULL, 10))
#define VIDEO_TSTC_FCT        serial_tstc
#define VIDEO_GETC_FCT        serial_getc

#define CONFIG_VIDEO_SMI_LYNXEM
#define CONFIG_VIDEO_LOGO
#define CONFIG_CONSOLE_EXTRA_INFO

/*
 * Initial BATs
 */
#if 1

#define CFG_IBAT0L 0
#define CFG_IBAT0U 0
#define CFG_DBAT0L CFG_IBAT1L
#define CFG_DBAT0U CFG_IBAT1U

#define CFG_IBAT1L 0
#define CFG_IBAT1U 0
#define CFG_DBAT1L CFG_IBAT1L
#define CFG_DBAT1U CFG_IBAT1U

#define CFG_IBAT2L 0
#define CFG_IBAT2U 0
#define CFG_DBAT2L CFG_IBAT2L
#define CFG_DBAT2U CFG_IBAT2U

#define CFG_IBAT3L 0
#define CFG_IBAT3U 0
#define CFG_DBAT3L CFG_IBAT3L
#define CFG_DBAT3U CFG_IBAT3U

#else

/* SDRAM */
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_RW)
#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_DBAT0L CFG_IBAT1L
#define CFG_DBAT0U CFG_IBAT1U

/* address range for flashes */
#define CFG_IBAT1L (CFG_FLASH_BASE | BATL_RW | BATL_CACHEINHIBIT)
#define CFG_IBAT1U (CFG_FLASH_BASE | BATU_BL_16M | BATU_VS | BATU_VP)
#define CFG_DBAT1L CFG_IBAT1L
#define CFG_DBAT1U CFG_IBAT1U

/* ISA IO space */
#define CFG_IBAT2L (CFG_ISA_IO | BATL_RW | BATL_CACHEINHIBIT)
#define CFG_IBAT2U (CFG_ISA_IO | BATU_BL_16M | BATU_VS | BATU_VP)
#define CFG_DBAT2L CFG_IBAT2L
#define CFG_DBAT2U CFG_IBAT2U

/* ISA memory space */
#define CFG_IBAT3L (CFG_ISA_MEM | BATL_RW | BATL_CACHEINHIBIT)
#define CFG_IBAT3U (CFG_ISA_MEM | BATU_BL_16M | BATU_VS | BATU_VP)
#define CFG_DBAT3L CFG_IBAT3L
#define CFG_DBAT3U CFG_IBAT3U

#endif

/*
 * Speed settings are board specific
 */
#define CFG_BUS_HZ              100000000
#define CFG_CPU_CLK             400000000
#define CFG_BUS_CLK             CFG_BUS_HZ

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ           (8 << 20)           /* Initial Memory map for Linux */

/*
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE        32    /* For all MPC74xx CPUs */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT        5    /* log base 2 of the above value */
#endif

/*
 * L2CR setup -- make sure this is right for your board!
 * look in include/74xx_7xx.h for the defines used here
 */

#define CFG_L2

#if 1
#define L2_INIT     0       /* cpu 750 CXe*/
#else
#define L2_INIT     (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
		     L2CR_L2OH_5   | L2CR_L2CTL | L2CR_L2WT)
#endif
#define L2_ENABLE   (L2_INIT | L2CR_L2E)

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM           0x02    /* Software reboot */

#define CONFIG_NET_MULTI        /* Multi ethernet cards support */
#define CONFIG_EEPRO100
#define CFG_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
#define CONFIG_EEPRO100_SROM_WRITE

#endif    /* __CONFIG_H */
Commit	Line	Data
e2211743 WD	1	/*
	2	* (C) Copyright 2002 ELTEC Elektronik AG
	3	* Frank Gottschling <[email protected]>
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* board/config.h - configuration options, board specific
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
e2211743 WD	31	#define GTREGREAD(x) 0xffffffff /* needed for debug */
	32
	33	/*
	34	* High Level Configuration Options
	35	* (easy to change)
	36	*/
	37
	38	/* these hardware addresses are pretty bogus, please change them to
	39	suit your needs */
	40
	41	/* first ethernet */
	42	#define CONFIG_ETHADDR 00:00:5b:ee:de:ad
	43
	44	#define CONFIG_IPADDR 192.168.0.105
	45	#define CONFIG_SERVERIP 192.168.0.100
	46
	47	#define CONFIG_ELPPC 1 /* this is an BAB740/BAB750 board */
	48
	49	#define CONFIG_BAUDRATE 9600 /* console baudrate */
	50
	51	#undef CONFIG_WATCHDOG
	52
	53	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	54
	55	#define CONFIG_ZERO_BOOTDELAY_CHECK
	56
	57	#undef CONFIG_BOOTARGS
	58	#define CONFIG_BOOTCOMMAND \
	59	"bootp 1000000; " \
	60	"setenv bootargs root=ramfs console=ttyS00,9600 " \
fe126d8b WD	61	"ip=${ipaddr}:${serverip}:${rootpath}:${gatewayip}:" \
fe126d8b WD	62	"${netmask}:${hostname}:eth0:none; " \
e2211743 WD	63	"bootm"
	64
	65	#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
	66	#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */
	67
5d2ebe1b JL	68	/*
	69	* BOOTP options
	70	*/
	71	#define CONFIG_BOOTP_SUBNETMASK
	72	#define CONFIG_BOOTP_GATEWAY
	73	#define CONFIG_BOOTP_HOSTNAME
	74	#define CONFIG_BOOTP_BOOTPATH
	75
	76	#define CONFIG_BOOTP_BOOTFILESIZE
e2211743	77
e2211743	78
dcaa7156 JL	79	/*
	80	* Command line configuration.
	81	*/
	82	#include <config_cmd_default.h>
	83
	84	#define CONFIG_CMD_PCI
	85	#define CONFIG_CMD_JFFS2
	86
e2211743 WD	87
	88	/*
	89	* Miscellaneous configurable options
	90	*/
	91	#define CFG_LONGHELP /* undef to save memory */
	92	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	93
	94	/*
	95	* choose between COM1 and COM2 as serial console
	96	*/
	97	#define CONFIG_CONS_INDEX 1
	98
dcaa7156	99	#if defined(CONFIG_CMD_KGDB)
e2211743 WD	100	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	101	#else
	102	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	103	#endif
	104	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	105	#define CFG_MAXARGS 16 /* max number of command args */
	106	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	107
	108	#define CFG_MEMTEST_START 0x00000000 /* memtest works on */
	109	#define CFG_MEMTEST_END 0x04000000 /* 0 ... 64 MB in DRAM */
	110
	111	#define CFG_LOAD_ADDR 0x1000000 /* default load address */
	112
	113	#define CFG_HZ 1000 /* dec. freq: 1 ms ticks */
	114
	115	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
	116
	117	/*
	118	* Low Level Configuration Settings
	119	* (address mappings, register initial values, etc.)
	120	* You should know what you are doing if you make changes here.
	121	*/
	122	#define CFG_BOARD_ASM_INIT
	123	#define CONFIG_MISC_INIT_R
	124
	125	/*
	126	* Address mapping scheme for the MPC107 mem controller is mapping B (CHRP)
	127	*/
	128	#undef CFG_ADDRESS_MAP_A
	129
	130	#define CFG_PCI_MEMORY_BUS 0x00000000
	131	#define CFG_PCI_MEMORY_PHYS 0x00000000
	132	#define CFG_PCI_MEMORY_SIZE 0x40000000
	133
	134	#define CFG_PCI_MEM_BUS 0x80000000
	135	#define CFG_PCI_MEM_PHYS 0x80000000
	136	#define CFG_PCI_MEM_SIZE 0x7d000000
	137
	138	#define CFG_ISA_MEM_BUS 0x00000000
	139	#define CFG_ISA_MEM_PHYS 0xfd000000
	140	#define CFG_ISA_MEM_SIZE 0x01000000
	141
	142	#define CFG_PCI_IO_BUS 0x00800000
	143	#define CFG_PCI_IO_PHYS 0xfe800000
	144	#define CFG_PCI_IO_SIZE 0x00400000
	145
	146	#define CFG_ISA_IO_BUS 0x00000000
	147	#define CFG_ISA_IO_PHYS 0xfe000000
	148	#define CFG_ISA_IO_SIZE 0x00800000
	149
	150	/* driver defines FDC,IDE,... */
	151	#define CFG_ISA_IO_BASE_ADDRESS CFG_ISA_IO_PHYS
	152	#define CFG_ISA_IO CFG_ISA_IO_PHYS
	153	#define CFG_60X_PCI_IO_OFFSET CFG_ISA_IO_PHYS
	154
	155	/*
	156	* Start addresses for the final memory configuration
	157	* (Set up by the startup code)
	158	* Please note that CFG_SDRAM_BASE _must_ start at 0
	159	*/
	160	#define CFG_SDRAM_BASE 0x00000000
	161
	162	#define CFG_USR_LED_BASE 0x78000000
	163	#define CFG_NVRAM_BASE 0xff000000
164	#define CFG_UART_BASE 0xff400000
165	#define CFG_FLASH_BASE 0xfff00000
166
167	#define MPC107_EUMB_ADDR 0xfce00000
168	#define MPC107_EUMB_PI 0xfce41090
169	#define MPC107_EUMB_GCR 0xfce41020
170	#define MPC107_EUMB_IACKR 0xfce600a0
171	#define MPC107_I2C_ADDR 0xfce03000
172
173	/*
174	* Definitions for initial stack pointer and data area
175	*/
176	#define CFG_INIT_RAM_ADDR 0x00fd0000 /* above the memtest region */
177	#define CFG_INIT_RAM_END 0x4000
178	#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for init data */
179	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
180	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
181
182	/*
183	* Flash mapping/organization on the MPC10x.
184	*/
185	#define FLASH_BASE0_PRELIM 0xff800000
186	#define FLASH_BASE1_PRELIM 0xffc00000
187
188	#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
189	#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
190
191	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
192	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
193
700a0c64 WD	194	/*
	195	* JFFS2 partitions
	196	*
	197	*/
	198	/* No command line, one static partition, whole device */
	199	#undef CONFIG_JFFS2_CMDLINE
	200	#define CONFIG_JFFS2_DEV "nor0"
	201	#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
	202	#define CONFIG_JFFS2_PART_OFFSET 0x00000000
	203
	204	/* mtdparts command line support */
	205	/* Note: fake mtd_id used, no linux mtd map file */
	206	/*
	207	#define CONFIG_JFFS2_CMDLINE
	208	#define MTDIDS_DEFAULT "nor0=elppc-0,nor1=elppc-1"
	209	#define MTDPARTS_DEFAULT "mtdparts=elppc-0:-(jffs2),elppc-1:-(user)"
	210	*/
e2211743 WD	211
	212	#define CFG_MONITOR_BASE CFG_FLASH_BASE
	213	#define CFG_MONITOR_LEN 0x40000 /* Reserve 256 kB for Monitor */
	214	#define CFG_MALLOC_LEN 0x20000 /* Reserve 128 kB for malloc() */
	215	#undef CFG_MEMTEST
	216
	217	/*
	218	* Environment settings
	219	*/
	220	#define CONFIG_ENV_OVERWRITE
9314cee6	221	#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
e2211743	222	#define CFG_NVRAM_SIZE 0x800 /* NVRAM size (2kB) */
0e8d1586 JCPV	223	#define CONFIG_ENV_SIZE 0x400 /* Size of Environment vars (1kB) */
	224	#define CONFIG_ENV_ADDR 0x0
	225	#define CONFIG_ENV_MAP_ADRS 0xff000000
	226	#define CFG_NV_SROM_COPY_ADDR (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
e2211743 WD	227	#define CFG_NVRAM_ACCESS_ROUTINE /* only byte accsess alowed */
	228	#define CFG_SROM_SIZE 0x100 /* shadow of revision info is in nvram */
	229
	230	/*
	231	* Serial devices
	232	*/
	233	#define CFG_NS16550
	234	#define CFG_NS16550_SERIAL
	235	#define CFG_NS16550_REG_SIZE 1
	236	#define CFG_NS16550_CLK 24000000
	237	#define CFG_NS16550_COM1 (CFG_UART_BASE + 0)
	238	#define CFG_NS16550_COM2 (CFG_UART_BASE + 8)
	239
	240	/*
	241	* PCI stuff
	242	*/
	243	#define CONFIG_PCI /* include pci support */
	244	#define CONFIG_PCI_PNP /* pci plug-and-play */
	245	#define CONFIG_PCI_HOST PCI_HOST_AUTO
	246	#undef CONFIG_PCI_SCAN_SHOW
	247
	248	/*
	249	* Optional Video console (graphic: SMI LynxEM)
	250	*/
	251	#define CONFIG_VIDEO
	252	#define CONFIG_CFB_CONSOLE
	253	#define VIDEO_KBD_INIT_FCT (simple_strtol (getenv("console"), NULL, 10))
	254	#define VIDEO_TSTC_FCT serial_tstc
	255	#define VIDEO_GETC_FCT serial_getc
	256
	257	#define CONFIG_VIDEO_SMI_LYNXEM
	258	#define CONFIG_VIDEO_LOGO
	259	#define CONFIG_CONSOLE_EXTRA_INFO
	260
	261	/*
	262	* Initial BATs
	263	*/
	264	#if 1
	265
	266	#define CFG_IBAT0L 0
	267	#define CFG_IBAT0U 0
	268	#define CFG_DBAT0L CFG_IBAT1L
	269	#define CFG_DBAT0U CFG_IBAT1U
	270
	271	#define CFG_IBAT1L 0
	272	#define CFG_IBAT1U 0
	273	#define CFG_DBAT1L CFG_IBAT1L
	274	#define CFG_DBAT1U CFG_IBAT1U
	275
	276	#define CFG_IBAT2L 0
	277	#define CFG_IBAT2U 0
	278	#define CFG_DBAT2L CFG_IBAT2L
	279	#define CFG_DBAT2U CFG_IBAT2U
	280
	281	#define CFG_IBAT3L 0
	282	#define CFG_IBAT3U 0
	283	#define CFG_DBAT3L CFG_IBAT3L
	284	#define CFG_DBAT3U CFG_IBAT3U
	285
	286	#else
	287
	288	/* SDRAM */
	289	#define CFG_IBAT0L (CFG_SDRAM_BASE \| BATL_RW)
	290	#define CFG_IBAT0U (CFG_SDRAM_BASE \| BATU_BL_256M \| BATU_VS \| BATU_VP)
291	#define CFG_DBAT0L CFG_IBAT1L
292	#define CFG_DBAT0U CFG_IBAT1U
293
294	/* address range for flashes */
295	#define CFG_IBAT1L (CFG_FLASH_BASE \| BATL_RW \| BATL_CACHEINHIBIT)
296	#define CFG_IBAT1U (CFG_FLASH_BASE \| BATU_BL_16M \| BATU_VS \| BATU_VP)
297	#define CFG_DBAT1L CFG_IBAT1L
298	#define CFG_DBAT1U CFG_IBAT1U
299
300	/* ISA IO space */
301	#define CFG_IBAT2L (CFG_ISA_IO \| BATL_RW \| BATL_CACHEINHIBIT)
302	#define CFG_IBAT2U (CFG_ISA_IO \| BATU_BL_16M \| BATU_VS \| BATU_VP)
303	#define CFG_DBAT2L CFG_IBAT2L
304	#define CFG_DBAT2U CFG_IBAT2U
305
306	/* ISA memory space */
307	#define CFG_IBAT3L (CFG_ISA_MEM \| BATL_RW \| BATL_CACHEINHIBIT)
308	#define CFG_IBAT3U (CFG_ISA_MEM \| BATU_BL_16M \| BATU_VS \| BATU_VP)
309	#define CFG_DBAT3L CFG_IBAT3L
310	#define CFG_DBAT3U CFG_IBAT3U
311
312	#endif
313
314	/*
315	* Speed settings are board specific
316	*/
317	#define CFG_BUS_HZ 100000000
318	#define CFG_CPU_CLK 400000000
319	#define CFG_BUS_CLK CFG_BUS_HZ
320
321	/*
322	* For booting Linux, the board info and command line data
323	* have to be in the first 8 MB of memory, since this is
324	* the maximum mapped by the Linux kernel during initialization.
325	*/
326	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
327
328	/*
329	* Cache Configuration
330	*/
331	#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
dcaa7156	332	#if defined(CONFIG_CMD_KGDB)
e2211743 WD	333	#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	334	#endif
	335
	336	/*
	337	* L2CR setup -- make sure this is right for your board!
1d0350ed	338	* look in include/74xx_7xx.h for the defines used here
e2211743 WD	339	*/
	340
	341	#define CFG_L2
	342
	343	#if 1
	344	#define L2_INIT 0 /* cpu 750 CXe*/
	345	#else
	346	#define L2_INIT (L2CR_L2SIZ_2M \| L2CR_L2CLK_3 \| L2CR_L2RAM_BURST \| \
8bde7f77	347	L2CR_L2OH_5 \| L2CR_L2CTL \| L2CR_L2WT)
e2211743 WD	348	#endif
	349	#define L2_ENABLE (L2_INIT \| L2CR_L2E)
	350
	351	/*
	352	* Internal Definitions
	353	*
	354	* Boot Flags
	355	*/
	356	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	357	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	358
	359	#define CONFIG_NET_MULTI /* Multi ethernet cards support */
	360	#define CONFIG_EEPRO100
53cf9435	361	#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
e2211743 WD	362	#define CONFIG_EEPRO100_SROM_WRITE
	363
	364	#endif /* __CONFIG_H */