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ram: stm32mp1: Only print RAM config with CONFIG_SPL_DISPLAY_PRINT
[u-boot.git] / drivers / spi / atmel-quadspi.c
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24c8ff46
TA		 1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Driver for Atmel QSPI Controller
4 *
5 * Copyright (C) 2015 Atmel Corporation
6 * Copyright (C) 2018 Cryptera A/S
7 *
8 * Author: Cyrille Pitchen <[email protected]>
9 * Author: Piotr Bugalski <[email protected]>
10 */
11
336d4615 12#include <malloc.h>
24c8ff46
TA		 13#include <asm/io.h>
14#include <clk.h>
15#include <common.h>
16#include <dm.h>
17#include <errno.h>
18#include <fdtdec.h>
336d4615 19#include <dm/device_compat.h>
2fd1b97f 20#include <linux/bitfield.h>
cd93d625 21#include <linux/bitops.h>
61b29b82 22#include <linux/err.h>
24c8ff46
TA		 23#include <linux/io.h>
24#include <linux/iopoll.h>
25#include <linux/ioport.h>
26#include <mach/clk.h>
27#include <spi.h>
28#include <spi-mem.h>
29
30/* QSPI register offsets */
31#define QSPI_CR 0x0000 /* Control Register */
32#define QSPI_MR 0x0004 /* Mode Register */
33#define QSPI_RD 0x0008 /* Receive Data Register */
34#define QSPI_TD 0x000c /* Transmit Data Register */
35#define QSPI_SR 0x0010 /* Status Register */
2fd1b97f 36#define QSPI_SR2 0x0024 /* SAMA7G5 Status Register */
24c8ff46
TA		 37#define QSPI_IER 0x0014 /* Interrupt Enable Register */
38#define QSPI_IDR 0x0018 /* Interrupt Disable Register */
39#define QSPI_IMR 0x001c /* Interrupt Mask Register */
40#define QSPI_SCR 0x0020 /* Serial Clock Register */
41
42#define QSPI_IAR 0x0030 /* Instruction Address Register */
43#define QSPI_ICR 0x0034 /* Instruction Code Register */
44#define QSPI_WICR 0x0034 /* Write Instruction Code Register */
45#define QSPI_IFR 0x0038 /* Instruction Frame Register */
46#define QSPI_RICR 0x003C /* Read Instruction Code Register */
47
48#define QSPI_SMR 0x0040 /* Scrambling Mode Register */
49#define QSPI_SKR 0x0044 /* Scrambling Key Register */
50
2fd1b97f
TA		 51#define QSPI_REFRESH 0x0050 /* Refresh Register */
52#define QSPI_WRACNT 0x0054 /* Write Access Counter Register */
53#define QSPI_DLLCFG 0x0058 /* DLL Configuration Register */
54#define QSPI_PCALCFG 0x005C /* Pad Calibration Configuration Register */
55#define QSPI_PCALBP 0x0060 /* Pad Calibration Bypass Register */
56#define QSPI_TOUT 0x0064 /* Timeout Register */
57
24c8ff46
TA		 58#define QSPI_WPMR 0x00E4 /* Write Protection Mode Register */
59#define QSPI_WPSR 0x00E8 /* Write Protection Status Register */
60
61#define QSPI_VERSION 0x00FC /* Version Register */
62
63/* Bitfields in QSPI_CR (Control Register) */
64#define QSPI_CR_QSPIEN BIT(0)
65#define QSPI_CR_QSPIDIS BIT(1)
2fd1b97f
TA		 66#define QSPI_CR_DLLON BIT(2)
67#define QSPI_CR_DLLOFF BIT(3)
68#define QSPI_CR_STPCAL BIT(4)
69#define QSPI_CR_SRFRSH BIT(5)
24c8ff46 70#define QSPI_CR_SWRST BIT(7)
2fd1b97f
TA		 71#define QSPI_CR_UPDCFG BIT(8)
72#define QSPI_CR_STTFR BIT(9)
73#define QSPI_CR_RTOUT BIT(10)
24c8ff46
TA		 74#define QSPI_CR_LASTXFER BIT(24)
75
76/* Bitfields in QSPI_MR (Mode Register) */
77#define QSPI_MR_SMM BIT(0)
78#define QSPI_MR_LLB BIT(1)
79#define QSPI_MR_WDRBT BIT(2)
80#define QSPI_MR_SMRM BIT(3)
2fd1b97f
TA		 81#define QSPI_MR_DQSDLYEN BIT(3)
82
24c8ff46
TA		 83#define QSPI_MR_CSMODE_MASK GENMASK(5, 4)
84#define QSPI_MR_CSMODE_NOT_RELOADED (0 << 4)
85#define QSPI_MR_CSMODE_LASTXFER (1 << 4)
86#define QSPI_MR_CSMODE_SYSTEMATICALLY (2 << 4)
87#define QSPI_MR_NBBITS_MASK GENMASK(11, 8)
88#define QSPI_MR_NBBITS(n) ((((n) - 8) << 8) & QSPI_MR_NBBITS_MASK)
2fd1b97f 89#define QSPI_MR_OENSD BIT(15)
24c8ff46
TA		 90#define QSPI_MR_DLYBCT_MASK GENMASK(23, 16)
91#define QSPI_MR_DLYBCT(n) (((n) << 16) & QSPI_MR_DLYBCT_MASK)
92#define QSPI_MR_DLYCS_MASK GENMASK(31, 24)
93#define QSPI_MR_DLYCS(n) (((n) << 24) & QSPI_MR_DLYCS_MASK)
94
95/* Bitfields in QSPI_SR/QSPI_IER/QSPI_IDR/QSPI_IMR */
96#define QSPI_SR_RDRF BIT(0)
97#define QSPI_SR_TDRE BIT(1)
98#define QSPI_SR_TXEMPTY BIT(2)
99#define QSPI_SR_OVRES BIT(3)
100#define QSPI_SR_CSR BIT(8)
101#define QSPI_SR_CSS BIT(9)
102#define QSPI_SR_INSTRE BIT(10)
2fd1b97f
TA		 103#define QSPI_SR_LWRA BIT(11)
104#define QSPI_SR_QITF BIT(12)
105#define QSPI_SR_QITR BIT(13)
106#define QSPI_SR_CSFA BIT(14)
107#define QSPI_SR_CSRA BIT(15)
108#define QSPI_SR_RFRSHD BIT(16)
109#define QSPI_SR_TOUT BIT(17)
24c8ff46
TA		 110#define QSPI_SR_QSPIENS BIT(24)
111
112#define QSPI_SR_CMD_COMPLETED (QSPI_SR_INSTRE | QSPI_SR_CSR)
113
114/* Bitfields in QSPI_SCR (Serial Clock Register) */
115#define QSPI_SCR_CPOL BIT(0)
116#define QSPI_SCR_CPHA BIT(1)
117#define QSPI_SCR_SCBR_MASK GENMASK(15, 8)
118#define QSPI_SCR_SCBR(n) (((n) << 8) & QSPI_SCR_SCBR_MASK)
119#define QSPI_SCR_DLYBS_MASK GENMASK(23, 16)
120#define QSPI_SCR_DLYBS(n) (((n) << 16) & QSPI_SCR_DLYBS_MASK)
121
2fd1b97f
TA		 122/* Bitfields in QSPI_SR2 (SAMA7G5 Status Register) */
123#define QSPI_SR2_SYNCBSY BIT(0)
124#define QSPI_SR2_QSPIENS BIT(1)
125#define QSPI_SR2_CSS BIT(2)
126#define QSPI_SR2_RBUSY BIT(3)
127#define QSPI_SR2_HIDLE BIT(4)
128#define QSPI_SR2_DLOCK BIT(5)
129#define QSPI_SR2_CALBSY BIT(6)
130
131/* Bitfields in QSPI_IAR (Instruction Address Register) */
132#define QSPI_IAR_ADDR GENMASK(31, 0)
133
24c8ff46
TA		 134/* Bitfields in QSPI_ICR (Read/Write Instruction Code Register) */
135#define QSPI_ICR_INST_MASK GENMASK(7, 0)
136#define QSPI_ICR_INST(inst) (((inst) << 0) & QSPI_ICR_INST_MASK)
2fd1b97f 137#define QSPI_ICR_INST_MASK_SAMA7G5 GENMASK(15, 0)
24c8ff46
TA		 138#define QSPI_ICR_OPT_MASK GENMASK(23, 16)
139#define QSPI_ICR_OPT(opt) (((opt) << 16) & QSPI_ICR_OPT_MASK)
140
141/* Bitfields in QSPI_IFR (Instruction Frame Register) */
142#define QSPI_IFR_WIDTH_MASK GENMASK(2, 0)
143#define QSPI_IFR_WIDTH_SINGLE_BIT_SPI (0 << 0)
144#define QSPI_IFR_WIDTH_DUAL_OUTPUT (1 << 0)
145#define QSPI_IFR_WIDTH_QUAD_OUTPUT (2 << 0)
146#define QSPI_IFR_WIDTH_DUAL_IO (3 << 0)
147#define QSPI_IFR_WIDTH_QUAD_IO (4 << 0)
148#define QSPI_IFR_WIDTH_DUAL_CMD (5 << 0)
149#define QSPI_IFR_WIDTH_QUAD_CMD (6 << 0)
2fd1b97f
TA		 150#define QSPI_IFR_WIDTH_OCT_OUTPUT (7 << 0)
151#define QSPI_IFR_WIDTH_OCT_IO (8 << 0)
152#define QSPI_IFR_WIDTH_OCT_CMD (9 << 0)
24c8ff46
TA		 153#define QSPI_IFR_INSTEN BIT(4)
154#define QSPI_IFR_ADDREN BIT(5)
155#define QSPI_IFR_OPTEN BIT(6)
156#define QSPI_IFR_DATAEN BIT(7)
157#define QSPI_IFR_OPTL_MASK GENMASK(9, 8)
158#define QSPI_IFR_OPTL_1BIT (0 << 8)
159#define QSPI_IFR_OPTL_2BIT (1 << 8)
160#define QSPI_IFR_OPTL_4BIT (2 << 8)
161#define QSPI_IFR_OPTL_8BIT (3 << 8)
162#define QSPI_IFR_ADDRL BIT(10)
2fd1b97f 163#define QSPI_IFR_ADDRL_SAMA7G5 GENMASK(11, 10)
24c8ff46
TA		 164#define QSPI_IFR_TFRTYP_MEM BIT(12)
165#define QSPI_IFR_SAMA5D2_WRITE_TRSFR BIT(13)
166#define QSPI_IFR_CRM BIT(14)
2fd1b97f 167#define QSPI_IFR_DDREN BIT(15)
24c8ff46
TA		 168#define QSPI_IFR_NBDUM_MASK GENMASK(20, 16)
169#define QSPI_IFR_NBDUM(n) (((n) << 16) & QSPI_IFR_NBDUM_MASK)
2fd1b97f
TA		 170#define QSPI_IFR_END BIT(22)
171#define QSPI_IFR_SMRM BIT(23)
24c8ff46 172#define QSPI_IFR_APBTFRTYP_READ BIT(24) /* Defined in SAM9X60 */
2fd1b97f
TA		 173#define QSPI_IFR_DQSEN BIT(25)
174#define QSPI_IFR_DDRCMDEN BIT(26)
175#define QSPI_IFR_HFWBEN BIT(27)
176#define QSPI_IFR_PROTTYP GENMASK(29, 28)
177#define QSPI_IFR_PROTTYP_STD_SPI 0
178#define QSPI_IFR_PROTTYP_TWIN_QUAD 1
179#define QSPI_IFR_PROTTYP_OCTAFLASH 2
180#define QSPI_IFR_PROTTYP_HYPERFLASH 3
24c8ff46
TA		 181
182/* Bitfields in QSPI_SMR (Scrambling Mode Register) */
183#define QSPI_SMR_SCREN BIT(0)
184#define QSPI_SMR_RVDIS BIT(1)
2fd1b97f
TA		 185#define QSPI_SMR_SCRKL BIT(2)
186
187/* Bitfields in QSPI_REFRESH (Refresh Register) */
188#define QSPI_REFRESH_DELAY_COUNTER GENMASK(31, 0)
189
190/* Bitfields in QSPI_WRACNT (Write Access Counter Register) */
191#define QSPI_WRACNT_NBWRA GENMASK(31, 0)
192
193/* Bitfields in QSPI_DLLCFG (DLL Configuration Register) */
194#define QSPI_DLLCFG_RANGE BIT(0)
195
196/* Bitfields in QSPI_PCALCFG (DLL Pad Calibration Configuration Register) */
197#define QSPI_PCALCFG_AAON BIT(0)
198#define QSPI_PCALCFG_DAPCAL BIT(1)
199#define QSPI_PCALCFG_DIFFPM BIT(2)
200#define QSPI_PCALCFG_CLKDIV GENMASK(6, 4)
201#define QSPI_PCALCFG_CALCNT GENMASK(16, 8)
202#define QSPI_PCALCFG_CALP GENMASK(27, 24)
203#define QSPI_PCALCFG_CALN GENMASK(31, 28)
204
205/* Bitfields in QSPI_PCALBP (DLL Pad Calibration Bypass Register) */
206#define QSPI_PCALBP_BPEN BIT(0)
207#define QSPI_PCALBP_CALPBP GENMASK(11, 8)
208#define QSPI_PCALBP_CALNBP GENMASK(19, 16)
209
210/* Bitfields in QSPI_TOUT (Timeout Register) */
211#define QSPI_TOUT_TCNTM GENMASK(15, 0)
24c8ff46
TA		 212
213/* Bitfields in QSPI_WPMR (Write Protection Mode Register) */
214#define QSPI_WPMR_WPEN BIT(0)
2fd1b97f
TA		 215#define QSPI_WPMR_WPITEN BIT(1)
216#define QSPI_WPMR_WPCREN BIT(2)
24c8ff46
TA		 217#define QSPI_WPMR_WPKEY_MASK GENMASK(31, 8)
218#define QSPI_WPMR_WPKEY(wpkey) (((wpkey) << 8) & QSPI_WPMR_WPKEY_MASK)
219
220/* Bitfields in QSPI_WPSR (Write Protection Status Register) */
221#define QSPI_WPSR_WPVS BIT(0)
222#define QSPI_WPSR_WPVSRC_MASK GENMASK(15, 8)
223#define QSPI_WPSR_WPVSRC(src) (((src) << 8) & QSPI_WPSR_WPVSRC)
224
2fd1b97f
TA		 225#define ATMEL_QSPI_TIMEOUT 1000000 /* us */
226#define ATMEL_QSPI_SYNC_TIMEOUT 300000 /* us */
227#define QSPI_DLLCFG_THRESHOLD_FREQ 90000000U
228#define QSPI_TOUT_MAX 0xffff
229
230/**
231 * struct atmel_qspi_pcal - Pad Calibration Clock Division
232 * @pclk_rate: peripheral clock rate.
233 * @pclkdiv: calibration clock division. The clock applied to the calibration
234 * cell is divided by pclkdiv + 1.
235 */
236struct atmel_qspi_pcal {
237 u32 pclk_rate;
238 u8 pclk_div;
239};
240
241#define ATMEL_QSPI_PCAL_ARRAY_SIZE 8
242static const struct atmel_qspi_pcal pcal[ATMEL_QSPI_PCAL_ARRAY_SIZE] = {
243 {25000000, 0},
244 {50000000, 1},
245 {75000000, 2},
246 {100000000, 3},
247 {125000000, 4},
248 {150000000, 5},
249 {175000000, 6},
250 {200000000, 7},
251};
252
24c8ff46
TA		 253struct atmel_qspi_caps {
254 bool has_qspick;
2fd1b97f 255 bool has_gclk;
24c8ff46 256 bool has_ricr;
2fd1b97f 257 bool octal;
24c8ff46
TA		 258};
259
2fd1b97f
TA		 260struct atmel_qspi_priv_ops;
261
24c8ff46
TA		 262struct atmel_qspi {
263 void __iomem *regs;
264 void __iomem *mem;
ba03a6c9 265 resource_size_t mmap_size;
24c8ff46 266 const struct atmel_qspi_caps *caps;
2fd1b97f 267 const struct atmel_qspi_priv_ops *ops;
52e2565b 268 struct udevice *dev;
24c8ff46
TA		 269 ulong bus_clk_rate;
270 u32 mr;
271};
272
2fd1b97f
TA		 273struct atmel_qspi_priv_ops {
274 int (*set_cfg)(struct atmel_qspi *aq, const struct spi_mem_op *op,
275 u32 *offset);
276 int (*transfer)(struct atmel_qspi *aq, const struct spi_mem_op *op,
277 u32 offset);
278};
279
24c8ff46
TA		 280struct atmel_qspi_mode {
281 u8 cmd_buswidth;
282 u8 addr_buswidth;
283 u8 data_buswidth;
284 u32 config;
285};
286
287static const struct atmel_qspi_mode atmel_qspi_modes[] = {
288 { 1, 1, 1, QSPI_IFR_WIDTH_SINGLE_BIT_SPI },
289 { 1, 1, 2, QSPI_IFR_WIDTH_DUAL_OUTPUT },
290 { 1, 1, 4, QSPI_IFR_WIDTH_QUAD_OUTPUT },
291 { 1, 2, 2, QSPI_IFR_WIDTH_DUAL_IO },
292 { 1, 4, 4, QSPI_IFR_WIDTH_QUAD_IO },
293 { 2, 2, 2, QSPI_IFR_WIDTH_DUAL_CMD },
294 { 4, 4, 4, QSPI_IFR_WIDTH_QUAD_CMD },
295};
296
2fd1b97f
TA		 297static const struct atmel_qspi_mode atmel_qspi_sama7g5_modes[] = {
298 { 1, 1, 1, QSPI_IFR_WIDTH_SINGLE_BIT_SPI },
299 { 1, 1, 2, QSPI_IFR_WIDTH_DUAL_OUTPUT },
300 { 1, 1, 4, QSPI_IFR_WIDTH_QUAD_OUTPUT },
301 { 1, 2, 2, QSPI_IFR_WIDTH_DUAL_IO },
302 { 1, 4, 4, QSPI_IFR_WIDTH_QUAD_IO },
303 { 2, 2, 2, QSPI_IFR_WIDTH_DUAL_CMD },
304 { 4, 4, 4, QSPI_IFR_WIDTH_QUAD_CMD },
305 { 1, 1, 8, QSPI_IFR_WIDTH_OCT_OUTPUT },
306 { 1, 8, 8, QSPI_IFR_WIDTH_OCT_IO },
307 { 8, 8, 8, QSPI_IFR_WIDTH_OCT_CMD },
308};
309
52e2565b
TA		 310#ifdef VERBOSE_DEBUG
311static const char *atmel_qspi_reg_name(u32 offset, char *tmp, size_t sz)
312{
313 switch (offset) {
314 case QSPI_CR:
315 return "CR";
316 case QSPI_MR:
317 return "MR";
318 case QSPI_RD:
7dc48b41 319 return "RD";
52e2565b
TA		 320 case QSPI_TD:
321 return "TD";
322 case QSPI_SR:
323 return "SR";
324 case QSPI_IER:
325 return "IER";
326 case QSPI_IDR:
327 return "IDR";
328 case QSPI_IMR:
329 return "IMR";
330 case QSPI_SCR:
331 return "SCR";
2fd1b97f
TA		 332 case QSPI_SR2:
333 return "SR2";
52e2565b
TA		 334 case QSPI_IAR:
335 return "IAR";
336 case QSPI_ICR:
337 return "ICR/WICR";
338 case QSPI_IFR:
339 return "IFR";
340 case QSPI_RICR:
341 return "RICR";
342 case QSPI_SMR:
343 return "SMR";
344 case QSPI_SKR:
345 return "SKR";
2fd1b97f
TA		 346 case QSPI_REFRESH:
347 return "REFRESH";
348 case QSPI_WRACNT:
349 return "WRACNT";
350 case QSPI_DLLCFG:
351 return "DLLCFG";
352 case QSPI_PCALCFG:
353 return "PCALCFG";
354 case QSPI_PCALBP:
355 return "PCALBP";
356 case QSPI_TOUT:
357 return "TOUT";
52e2565b
TA		 358 case QSPI_WPMR:
359 return "WPMR";
360 case QSPI_WPSR:
361 return "WPSR";
362 case QSPI_VERSION:
363 return "VERSION";
364 default:
365 snprintf(tmp, sz, "0x%02x", offset);
366 break;
367 }
368
369 return tmp;
370}
371#endif /* VERBOSE_DEBUG */
372
373static u32 atmel_qspi_read(struct atmel_qspi *aq, u32 offset)
374{
375 u32 value = readl(aq->regs + offset);
376
377#ifdef VERBOSE_DEBUG
378 char tmp[16];
379
380 dev_vdbg(aq->dev, "read 0x%08x from %s\n", value,
381 atmel_qspi_reg_name(offset, tmp, sizeof(tmp)));
382#endif /* VERBOSE_DEBUG */
383
384 return value;
385}
386
387static void atmel_qspi_write(u32 value, struct atmel_qspi *aq, u32 offset)
388{
389#ifdef VERBOSE_DEBUG
390 char tmp[16];
391
392 dev_vdbg(aq->dev, "write 0x%08x into %s\n", value,
393 atmel_qspi_reg_name(offset, tmp, sizeof(tmp)));
394#endif /* VERBOSE_DEBUG */
395
396 writel(value, aq->regs + offset);
397}
398
24c8ff46
TA		 399static inline bool atmel_qspi_is_compatible(const struct spi_mem_op *op,
400 const struct atmel_qspi_mode *mode)
401{
402 if (op->cmd.buswidth != mode->cmd_buswidth)
403 return false;
404
405 if (op->addr.nbytes && op->addr.buswidth != mode->addr_buswidth)
406 return false;
407
408 if (op->data.nbytes && op->data.buswidth != mode->data_buswidth)
409 return false;
410
411 return true;
412}
413
414static int atmel_qspi_find_mode(const struct spi_mem_op *op)
415{
416 u32 i;
417
418 for (i = 0; i < ARRAY_SIZE(atmel_qspi_modes); i++)
419 if (atmel_qspi_is_compatible(op, &atmel_qspi_modes[i]))
420 return i;
421
422 return -ENOTSUPP;
423}
424
2fd1b97f
TA		 425static int atmel_qspi_sama7g5_find_mode(const struct spi_mem_op *op)
426{
427 u32 i;
428
429 for (i = 0; i < ARRAY_SIZE(atmel_qspi_sama7g5_modes); i++)
430 if (atmel_qspi_is_compatible(op, &atmel_qspi_sama7g5_modes[i]))
431 return i;
432
433 return -EOPNOTSUPP;
434}
435
24c8ff46
TA		 436static bool atmel_qspi_supports_op(struct spi_slave *slave,
437 const struct spi_mem_op *op)
438{
2fd1b97f
TA		 439 struct atmel_qspi *aq = dev_get_priv(slave->dev->parent);
440
20ced4b2
TA		 441 if (!spi_mem_default_supports_op(slave, op))
442 return false;
443
2fd1b97f
TA		 444 if (aq->caps->octal) {
445 if (atmel_qspi_sama7g5_find_mode(op) < 0)
446 return false;
447 else
448 return true;
449 }
450
24c8ff46
TA		 451 if (atmel_qspi_find_mode(op) < 0)
452 return false;
453
454 /* special case not supported by hardware */
455 if (op->addr.nbytes == 2 && op->cmd.buswidth != op->addr.buswidth &&
456 op->dummy.nbytes == 0)
457 return false;
458
459 return true;
460}
461
462static int atmel_qspi_set_cfg(struct atmel_qspi *aq,
463 const struct spi_mem_op *op, u32 *offset)
464{
465 u32 iar, icr, ifr;
466 u32 dummy_cycles = 0;
467 int mode;
468
469 iar = 0;
470 icr = QSPI_ICR_INST(op->cmd.opcode);
471 ifr = QSPI_IFR_INSTEN;
472
473 mode = atmel_qspi_find_mode(op);
474 if (mode < 0)
475 return mode;
476 ifr |= atmel_qspi_modes[mode].config;
477
478 if (op->dummy.buswidth && op->dummy.nbytes)
479 dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth;
480
481 /*
482 * The controller allows 24 and 32-bit addressing while NAND-flash
483 * requires 16-bit long. Handling 8-bit long addresses is done using
484 * the option field. For the 16-bit addresses, the workaround depends
485 * of the number of requested dummy bits. If there are 8 or more dummy
486 * cycles, the address is shifted and sent with the first dummy byte.
487 * Otherwise opcode is disabled and the first byte of the address
488 * contains the command opcode (works only if the opcode and address
489 * use the same buswidth). The limitation is when the 16-bit address is
490 * used without enough dummy cycles and the opcode is using a different
491 * buswidth than the address.
492 */
493 if (op->addr.buswidth) {
494 switch (op->addr.nbytes) {
495 case 0:
496 break;
497 case 1:
498 ifr |= QSPI_IFR_OPTEN | QSPI_IFR_OPTL_8BIT;
499 icr |= QSPI_ICR_OPT(op->addr.val & 0xff);
500 break;
501 case 2:
502 if (dummy_cycles < 8 / op->addr.buswidth) {
503 ifr &= ~QSPI_IFR_INSTEN;
504 ifr |= QSPI_IFR_ADDREN;
505 iar = (op->cmd.opcode << 16) |
506 (op->addr.val & 0xffff);
507 } else {
508 ifr |= QSPI_IFR_ADDREN;
509 iar = (op->addr.val << 8) & 0xffffff;
510 dummy_cycles -= 8 / op->addr.buswidth;
511 }
512 break;
513 case 3:
514 ifr |= QSPI_IFR_ADDREN;
515 iar = op->addr.val & 0xffffff;
516 break;
517 case 4:
518 ifr |= QSPI_IFR_ADDREN | QSPI_IFR_ADDRL;
519 iar = op->addr.val & 0x7ffffff;
520 break;
521 default:
522 return -ENOTSUPP;
523 }
524 }
525
526 /* offset of the data access in the QSPI memory space */
527 *offset = iar;
528
529 /* Set number of dummy cycles */
530 if (dummy_cycles)
531 ifr |= QSPI_IFR_NBDUM(dummy_cycles);
532
533 /* Set data enable */
534 if (op->data.nbytes)
535 ifr |= QSPI_IFR_DATAEN;
536
537 /*
538 * If the QSPI controller is set in regular SPI mode, set it in
539 * Serial Memory Mode (SMM).
540 */
541 if (aq->mr != QSPI_MR_SMM) {
52e2565b 542 atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR);
24c8ff46
TA		 543 aq->mr = QSPI_MR_SMM;
544 }
545
546 /* Clear pending interrupts */
52e2565b 547 (void)atmel_qspi_read(aq, QSPI_SR);
24c8ff46
TA		 548
549 if (aq->caps->has_ricr) {
550 if (!op->addr.nbytes && op->data.dir == SPI_MEM_DATA_IN)
551 ifr |= QSPI_IFR_APBTFRTYP_READ;
552
553 /* Set QSPI Instruction Frame registers */
52e2565b 554 atmel_qspi_write(iar, aq, QSPI_IAR);
24c8ff46 555 if (op->data.dir == SPI_MEM_DATA_IN)
52e2565b 556 atmel_qspi_write(icr, aq, QSPI_RICR);
24c8ff46 557 else
52e2565b
TA		 558 atmel_qspi_write(icr, aq, QSPI_WICR);
559 atmel_qspi_write(ifr, aq, QSPI_IFR);
24c8ff46
TA		 560 } else {
561 if (op->data.dir == SPI_MEM_DATA_OUT)
562 ifr |= QSPI_IFR_SAMA5D2_WRITE_TRSFR;
563
564 /* Set QSPI Instruction Frame registers */
52e2565b
TA		 565 atmel_qspi_write(iar, aq, QSPI_IAR);
566 atmel_qspi_write(icr, aq, QSPI_ICR);
567 atmel_qspi_write(ifr, aq, QSPI_IFR);
24c8ff46
TA		 568 }
569
570 return 0;
571}
572
2fd1b97f
TA		 573static int atmel_qspi_transfer(struct atmel_qspi *aq,
574 const struct spi_mem_op *op, u32 offset)
24c8ff46 575{
2fd1b97f 576 u32 sr, imr;
24c8ff46
TA		 577
578 /* Skip to the final steps if there is no data */
579 if (op->data.nbytes) {
580 /* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */
52e2565b 581 (void)atmel_qspi_read(aq, QSPI_IFR);
24c8ff46
TA		 582
583 /* Send/Receive data */
584 if (op->data.dir == SPI_MEM_DATA_IN)
585 memcpy_fromio(op->data.buf.in, aq->mem + offset,
586 op->data.nbytes);
587 else
588 memcpy_toio(aq->mem + offset, op->data.buf.out,
589 op->data.nbytes);
590
591 /* Release the chip-select */
52e2565b 592 atmel_qspi_write(QSPI_CR_LASTXFER, aq, QSPI_CR);
24c8ff46
TA		 593 }
594
595 /* Poll INSTruction End and Chip Select Rise flags. */
596 imr = QSPI_SR_INSTRE | QSPI_SR_CSR;
597 return readl_poll_timeout(aq->regs + QSPI_SR, sr, (sr & imr) == imr,
2fd1b97f
TA		 598 ATMEL_QSPI_TIMEOUT);
599}
600
601static int atmel_qspi_reg_sync(struct atmel_qspi *aq)
602{
603 u32 val;
604
605 return readl_poll_timeout(aq->regs + QSPI_SR2, val,
606 !(val & QSPI_SR2_SYNCBSY),
607 ATMEL_QSPI_SYNC_TIMEOUT);
608}
609
610static int atmel_qspi_update_config(struct atmel_qspi *aq)
611{
612 int ret;
613
614 ret = atmel_qspi_reg_sync(aq);
615 if (ret)
616 return ret;
617 atmel_qspi_write(QSPI_CR_UPDCFG, aq, QSPI_CR);
618 return atmel_qspi_reg_sync(aq);
619}
620
621static int atmel_qspi_sama7g5_set_cfg(struct atmel_qspi *aq,
622 const struct spi_mem_op *op, u32 *offset)
623{
624 u32 iar, icr, ifr;
625 int mode, ret;
626
627 iar = 0;
628 icr = FIELD_PREP(QSPI_ICR_INST_MASK_SAMA7G5, op->cmd.opcode);
629 ifr = QSPI_IFR_INSTEN;
630
631 mode = atmel_qspi_sama7g5_find_mode(op);
632 if (mode < 0)
633 return mode;
634 ifr |= atmel_qspi_sama7g5_modes[mode].config;
635
636 if (op->dummy.buswidth && op->dummy.nbytes) {
637 if (op->addr.dtr && op->dummy.dtr && op->data.dtr)
638 ifr |= QSPI_IFR_NBDUM(op->dummy.nbytes * 8 /
639 (2 * op->dummy.buswidth));
640 else
641 ifr |= QSPI_IFR_NBDUM(op->dummy.nbytes * 8 /
642 op->dummy.buswidth);
643 }
644
645 if (op->addr.buswidth && op->addr.nbytes) {
646 ifr |= FIELD_PREP(QSPI_IFR_ADDRL_SAMA7G5, op->addr.nbytes - 1) |
647 QSPI_IFR_ADDREN;
648 iar = FIELD_PREP(QSPI_IAR_ADDR, op->addr.val);
649 }
650
651 if (op->addr.dtr && op->dummy.dtr && op->data.dtr) {
652 ifr |= QSPI_IFR_DDREN;
653 if (op->cmd.dtr)
654 ifr |= QSPI_IFR_DDRCMDEN;
655 ifr |= QSPI_IFR_DQSEN;
656 }
657
658 if (op->cmd.buswidth == 8 || op->addr.buswidth == 8 ||
659 op->data.buswidth == 8)
660 ifr |= FIELD_PREP(QSPI_IFR_PROTTYP, QSPI_IFR_PROTTYP_OCTAFLASH);
661
662 /* offset of the data access in the QSPI memory space */
663 *offset = iar;
664
665 /* Set data enable */
666 if (op->data.nbytes) {
667 ifr |= QSPI_IFR_DATAEN;
668 if (op->addr.nbytes)
669 ifr |= QSPI_IFR_TFRTYP_MEM;
670 }
671
672 /*
673 * If the QSPI controller is set in regular SPI mode, set it in
674 * Serial Memory Mode (SMM).
675 */
676 if (aq->mr != QSPI_MR_SMM) {
677 atmel_qspi_write(QSPI_MR_SMM | QSPI_MR_DQSDLYEN, aq, QSPI_MR);
678 ret = atmel_qspi_update_config(aq);
679 if (ret)
680 return ret;
681 aq->mr = QSPI_MR_SMM;
682 }
683
684 /* Clear pending interrupts */
685 (void)atmel_qspi_read(aq, QSPI_SR);
686
687 /* Set QSPI Instruction Frame registers */
688 if (op->addr.nbytes && !op->data.nbytes)
689 atmel_qspi_write(iar, aq, QSPI_IAR);
690
691 if (op->data.dir == SPI_MEM_DATA_IN) {
692 atmel_qspi_write(icr, aq, QSPI_RICR);
693 } else {
694 atmel_qspi_write(icr, aq, QSPI_WICR);
695 if (op->data.nbytes)
696 atmel_qspi_write(FIELD_PREP(QSPI_WRACNT_NBWRA,
697 op->data.nbytes),
698 aq, QSPI_WRACNT);
699 }
700
701 atmel_qspi_write(ifr, aq, QSPI_IFR);
702
703 return atmel_qspi_update_config(aq);
704}
705
706static int atmel_qspi_sama7g5_transfer(struct atmel_qspi *aq,
707 const struct spi_mem_op *op, u32 offset)
708{
709 int err;
710 u32 val;
711
712 if (!op->data.nbytes) {
713 /* Start the transfer. */
714 err = atmel_qspi_reg_sync(aq);
715 if (err)
716 return err;
717 atmel_qspi_write(QSPI_CR_STTFR, aq, QSPI_CR);
718
719 return readl_poll_timeout(aq->regs + QSPI_SR, val,
720 val & QSPI_SR_CSRA,
721 ATMEL_QSPI_TIMEOUT);
722 }
723
724 /* Send/Receive data. */
725 if (op->data.dir == SPI_MEM_DATA_IN) {
726 memcpy_fromio(op->data.buf.in, aq->mem + offset,
727 op->data.nbytes);
728
729 if (op->addr.nbytes) {
730 err = readl_poll_timeout(aq->regs + QSPI_SR2, val,
731 !(val & QSPI_SR2_RBUSY),
732 ATMEL_QSPI_SYNC_TIMEOUT);
733 if (err)
734 return err;
735 }
736 } else {
737 memcpy_toio(aq->mem + offset, op->data.buf.out,
738 op->data.nbytes);
739
740 err = readl_poll_timeout(aq->regs + QSPI_SR, val,
741 val & QSPI_SR_LWRA,
742 ATMEL_QSPI_TIMEOUT);
743 if (err)
744 return err;
745 }
746
747 /* Release the chip-select. */
748 err = atmel_qspi_reg_sync(aq);
749 if (err)
750 return err;
751 atmel_qspi_write(QSPI_CR_LASTXFER, aq, QSPI_CR);
752
753 return readl_poll_timeout(aq->regs + QSPI_SR, val, val & QSPI_SR_CSRA,
754 ATMEL_QSPI_TIMEOUT);
755}
756
757static int atmel_qspi_exec_op(struct spi_slave *slave,
758 const struct spi_mem_op *op)
759{
760 struct atmel_qspi *aq = dev_get_priv(slave->dev->parent);
761 u32 offset;
762 int err;
763
764 /*
765 * Check if the address exceeds the MMIO window size. An improvement
766 * would be to add support for regular SPI mode and fall back to it
767 * when the flash memories overrun the controller's memory space.
768 */
769 if (op->addr.val + op->data.nbytes > aq->mmap_size)
770 return -ENOTSUPP;
771
772 if (op->addr.nbytes > 4)
773 return -EOPNOTSUPP;
774
775 err = aq->ops->set_cfg(aq, op, &offset);
776 if (err)
777 return err;
778
779 return aq->ops->transfer(aq, op, offset);
780}
781
782static int atmel_qspi_set_pad_calibration(struct udevice *bus, uint hz)
783{
784 struct atmel_qspi *aq = dev_get_priv(bus);
785 u32 status, val;
786 int i, ret;
787 u8 pclk_div = 0;
788
789 for (i = 0; i < ATMEL_QSPI_PCAL_ARRAY_SIZE; i++) {
790 if (aq->bus_clk_rate <= pcal[i].pclk_rate) {
791 pclk_div = pcal[i].pclk_div;
792 break;
793 }
794 }
795
796 /*
797 * Use the biggest divider in case the peripheral clock exceeds
798 * 200MHZ.
799 */
800 if (aq->bus_clk_rate > pcal[ATMEL_QSPI_PCAL_ARRAY_SIZE - 1].pclk_rate)
801 pclk_div = pcal[ATMEL_QSPI_PCAL_ARRAY_SIZE - 1].pclk_div;
802
803 /* Disable QSPI while configuring the pad calibration. */
804 status = atmel_qspi_read(aq, QSPI_SR2);
805 if (status & QSPI_SR2_QSPIENS) {
806 ret = atmel_qspi_reg_sync(aq);
807 if (ret)
808 return ret;
809 atmel_qspi_write(QSPI_CR_QSPIDIS, aq, QSPI_CR);
810 }
811
812 /*
813 * The analog circuitry is not shut down at the end of the calibration
814 * and the start-up time is only required for the first calibration
815 * sequence, thus increasing performance. Set the delay between the Pad
816 * calibration analog circuitry and the calibration request to 2us.
817 */
818 atmel_qspi_write(QSPI_PCALCFG_AAON |
819 FIELD_PREP(QSPI_PCALCFG_CLKDIV, pclk_div) |
820 FIELD_PREP(QSPI_PCALCFG_CALCNT,
821 2 * (aq->bus_clk_rate / 1000000)),
822 aq, QSPI_PCALCFG);
823
824 /* DLL On + start calibration. */
825 atmel_qspi_write(QSPI_CR_DLLON | QSPI_CR_STPCAL, aq, QSPI_CR);
826 ret = readl_poll_timeout(aq->regs + QSPI_SR2, val,
827 (val & QSPI_SR2_DLOCK) &&
828 !(val & QSPI_SR2_CALBSY),
829 ATMEL_QSPI_TIMEOUT);
830
831 /* Refresh analogic blocks every 1 ms.*/
832 atmel_qspi_write(FIELD_PREP(QSPI_REFRESH_DELAY_COUNTER, hz / 1000),
833 aq, QSPI_REFRESH);
834
835 return ret;
836}
837
838static int atmel_qspi_set_gclk(struct udevice *bus, uint hz)
839{
840 struct atmel_qspi *aq = dev_get_priv(bus);
841 struct clk gclk;
842 u32 status, val;
843 int ret;
844
845 /* Disable DLL before setting GCLK */
846 status = atmel_qspi_read(aq, QSPI_SR2);
847 if (status & QSPI_SR2_DLOCK) {
848 atmel_qspi_write(QSPI_CR_DLLOFF, aq, QSPI_CR);
849 ret = readl_poll_timeout(aq->regs + QSPI_SR2, val,
850 !(val & QSPI_SR2_DLOCK),
851 ATMEL_QSPI_TIMEOUT);
852 if (ret)
853 return ret;
854 }
855
856 if (hz > QSPI_DLLCFG_THRESHOLD_FREQ)
857 atmel_qspi_write(QSPI_DLLCFG_RANGE, aq, QSPI_DLLCFG);
858 else
859 atmel_qspi_write(0, aq, QSPI_DLLCFG);
860
861 ret = clk_get_by_name(bus, "gclk", &gclk);
862 if (ret) {
863 dev_err(bus, "Missing QSPI generic clock\n");
864 return ret;
865 }
866
867 ret = clk_disable(&gclk);
868 if (ret)
869 dev_err(bus, "Failed to disable QSPI generic clock\n");
870
871 ret = clk_set_rate(&gclk, hz);
872 if (ret < 0) {
873 dev_err(bus, "Failed to set generic clock rate.\n");
874 return ret;
875 }
876
877 ret = clk_enable(&gclk);
878 if (ret)
879 dev_err(bus, "Failed to enable QSPI generic clock\n");
880 clk_free(&gclk);
881
882 return ret;
883}
884
885static int atmel_qspi_sama7g5_set_speed(struct udevice *bus, uint hz)
886{
887 struct atmel_qspi *aq = dev_get_priv(bus);
888 u32 val;
889 int ret;
890
891 ret = atmel_qspi_set_gclk(bus, hz);
892 if (ret)
893 return ret;
894
895 if (aq->caps->octal) {
896 ret = atmel_qspi_set_pad_calibration(bus, hz);
897 if (ret)
898 return ret;
899 } else {
900 atmel_qspi_write(QSPI_CR_DLLON, aq, QSPI_CR);
901 ret = readl_poll_timeout(aq->regs + QSPI_SR2, val,
902 val & QSPI_SR2_DLOCK,
903 ATMEL_QSPI_TIMEOUT);
904 }
905
906 /* Set the QSPI controller by default in Serial Memory Mode */
907 atmel_qspi_write(QSPI_MR_SMM | QSPI_MR_DQSDLYEN, aq, QSPI_MR);
908 ret = atmel_qspi_update_config(aq);
909 if (ret)
910 return ret;
911 aq->mr = QSPI_MR_SMM;
912
913 /* Enable the QSPI controller. */
914 ret = atmel_qspi_reg_sync(aq);
915 if (ret)
916 return ret;
917 atmel_qspi_write(QSPI_CR_QSPIEN, aq, QSPI_CR);
918 ret = readl_poll_timeout(aq->regs + QSPI_SR2, val,
919 val & QSPI_SR2_QSPIENS,
920 ATMEL_QSPI_SYNC_TIMEOUT);
921 if (ret)
922 return ret;
923
924 if (aq->caps->octal)
925 ret = readl_poll_timeout(aq->regs + QSPI_SR, val,
926 val & QSPI_SR_RFRSHD,
927 ATMEL_QSPI_TIMEOUT);
928
929 atmel_qspi_write(FIELD_PREP(QSPI_TOUT_TCNTM, QSPI_TOUT_MAX),
930 aq, QSPI_TOUT);
931
932 return ret;
24c8ff46
TA		 933}
934
935static int atmel_qspi_set_speed(struct udevice *bus, uint hz)
936{
937 struct atmel_qspi *aq = dev_get_priv(bus);
938 u32 scr, scbr, mask, new_value;
939
2fd1b97f
TA		 940 if (aq->caps->has_gclk)
941 return atmel_qspi_sama7g5_set_speed(bus, hz);
942
24c8ff46
TA		 943 /* Compute the QSPI baudrate */
944 scbr = DIV_ROUND_UP(aq->bus_clk_rate, hz);
945 if (scbr > 0)
946 scbr--;
947
948 new_value = QSPI_SCR_SCBR(scbr);
949 mask = QSPI_SCR_SCBR_MASK;
950
52e2565b 951 scr = atmel_qspi_read(aq, QSPI_SCR);
24c8ff46
TA		 952 if ((scr & mask) == new_value)
953 return 0;
954
955 scr = (scr & ~mask) | new_value;
52e2565b 956 atmel_qspi_write(scr, aq, QSPI_SCR);
24c8ff46
TA		 957
958 return 0;
959}
960
961static int atmel_qspi_set_mode(struct udevice *bus, uint mode)
962{
963 struct atmel_qspi *aq = dev_get_priv(bus);
964 u32 scr, mask, new_value = 0;
965
966 if (mode & SPI_CPOL)
967 new_value = QSPI_SCR_CPOL;
968 if (mode & SPI_CPHA)
969 new_value = QSPI_SCR_CPHA;
970
971 mask = QSPI_SCR_CPOL | QSPI_SCR_CPHA;
972
52e2565b 973 scr = atmel_qspi_read(aq, QSPI_SCR);
24c8ff46
TA		 974 if ((scr & mask) == new_value)
975 return 0;
976
977 scr = (scr & ~mask) | new_value;
52e2565b 978 atmel_qspi_write(scr, aq, QSPI_SCR);
2fd1b97f
TA		 979 if (aq->caps->has_gclk)
980 return atmel_qspi_update_config(aq);
24c8ff46
TA		 981
982 return 0;
983}
984
985static int atmel_qspi_enable_clk(struct udevice *dev)
986{
987 struct atmel_qspi *aq = dev_get_priv(dev);
2fd1b97f 988 struct clk pclk, qspick, gclk;
24c8ff46
TA		 989 int ret;
990
991 ret = clk_get_by_name(dev, "pclk", &pclk);
992 if (ret)
993 ret = clk_get_by_index(dev, 0, &pclk);
994
995 if (ret) {
996 dev_err(dev, "Missing QSPI peripheral clock\n");
997 return ret;
998 }
999
1000 ret = clk_enable(&pclk);
1001 if (ret) {
1002 dev_err(dev, "Failed to enable QSPI peripheral clock\n");
1003 goto free_pclk;
1004 }
1005
1006 if (aq->caps->has_qspick) {
1007 /* Get the QSPI system clock */
1008 ret = clk_get_by_name(dev, "qspick", &qspick);
1009 if (ret) {
1010 dev_err(dev, "Missing QSPI peripheral clock\n");
1011 goto free_pclk;
1012 }
1013
1014 ret = clk_enable(&qspick);
1015 if (ret)
1016 dev_err(dev, "Failed to enable QSPI system clock\n");
1017 clk_free(&qspick);
2fd1b97f
TA		 1018 } else if (aq->caps->has_gclk) {
1019 ret = clk_get_by_name(dev, "gclk", &gclk);
1020 if (ret) {
1021 dev_err(dev, "Missing QSPI generic clock\n");
1022 goto free_pclk;
1023 }
1024
1025 ret = clk_enable(&gclk);
1026 if (ret)
1027 dev_err(dev, "Failed to enable QSPI system clock\n");
1028 clk_free(&gclk);
24c8ff46
TA		 1029 }
1030
1031 aq->bus_clk_rate = clk_get_rate(&pclk);
1032 if (!aq->bus_clk_rate)
1033 ret = -EINVAL;
1034
1035free_pclk:
1036 clk_free(&pclk);
1037
1038 return ret;
1039}
1040
2fd1b97f 1041static int atmel_qspi_init(struct atmel_qspi *aq)
24c8ff46 1042{
2fd1b97f
TA		 1043 int ret;
1044
1045 if (aq->caps->has_gclk) {
1046 ret = atmel_qspi_reg_sync(aq);
1047 if (ret)
1048 return ret;
1049 atmel_qspi_write(QSPI_CR_SWRST, aq, QSPI_CR);
1050 return 0;
1051 }
1052
24c8ff46 1053 /* Reset the QSPI controller */
52e2565b 1054 atmel_qspi_write(QSPI_CR_SWRST, aq, QSPI_CR);
24c8ff46
TA		 1055
1056 /* Set the QSPI controller by default in Serial Memory Mode */
52e2565b 1057 atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR);
24c8ff46
TA		 1058 aq->mr = QSPI_MR_SMM;
1059
1060 /* Enable the QSPI controller */
52e2565b 1061 atmel_qspi_write(QSPI_CR_QSPIEN, aq, QSPI_CR);
2fd1b97f
TA		 1062
1063 return 0;
24c8ff46
TA		 1064}
1065
2fd1b97f
TA		 1066static const struct atmel_qspi_priv_ops atmel_qspi_priv_ops = {
1067 .set_cfg = atmel_qspi_set_cfg,
1068 .transfer = atmel_qspi_transfer,
1069};
1070
1071static const struct atmel_qspi_priv_ops atmel_qspi_sama7g5_priv_ops = {
1072 .set_cfg = atmel_qspi_sama7g5_set_cfg,
1073 .transfer = atmel_qspi_sama7g5_transfer,
1074};
1075
24c8ff46
TA		 1076static int atmel_qspi_probe(struct udevice *dev)
1077{
1078 struct atmel_qspi *aq = dev_get_priv(dev);
1079 struct resource res;
1080 int ret;
1081
1082 aq->caps = (struct atmel_qspi_caps *)dev_get_driver_data(dev);
1083 if (!aq->caps) {
1084 dev_err(dev, "Could not retrieve QSPI caps\n");
1085 return -EINVAL;
1086 };
1087
2fd1b97f
TA		 1088 if (aq->caps->has_gclk)
1089 aq->ops = &atmel_qspi_sama7g5_priv_ops;
1090 else
1091 aq->ops = &atmel_qspi_priv_ops;
1092
24c8ff46
TA		 1093 /* Map the registers */
1094 ret = dev_read_resource_byname(dev, "qspi_base", &res);
1095 if (ret) {
1096 dev_err(dev, "missing registers\n");
1097 return ret;
1098 }
1099
1100 aq->regs = devm_ioremap(dev, res.start, resource_size(&res));
1101 if (IS_ERR(aq->regs))
1102 return PTR_ERR(aq->regs);
1103
1104 /* Map the AHB memory */
1105 ret = dev_read_resource_byname(dev, "qspi_mmap", &res);
1106 if (ret) {
1107 dev_err(dev, "missing AHB memory\n");
1108 return ret;
1109 }
1110
1111 aq->mem = devm_ioremap(dev, res.start, resource_size(&res));
1112 if (IS_ERR(aq->mem))
1113 return PTR_ERR(aq->mem);
1114
ba03a6c9
TA		 1115 aq->mmap_size = resource_size(&res);
1116
24c8ff46
TA		 1117 ret = atmel_qspi_enable_clk(dev);
1118 if (ret)
1119 return ret;
1120
52e2565b 1121 aq->dev = dev;
2fd1b97f 1122 return atmel_qspi_init(aq);
24c8ff46
TA		 1123}
1124
1125static const struct spi_controller_mem_ops atmel_qspi_mem_ops = {
1126 .supports_op = atmel_qspi_supports_op,
1127 .exec_op = atmel_qspi_exec_op,
1128};
1129
1130static const struct dm_spi_ops atmel_qspi_ops = {
1131 .set_speed = atmel_qspi_set_speed,
1132 .set_mode = atmel_qspi_set_mode,
1133 .mem_ops = &atmel_qspi_mem_ops,
1134};
1135
1136static const struct atmel_qspi_caps atmel_sama5d2_qspi_caps = {};
1137
1138static const struct atmel_qspi_caps atmel_sam9x60_qspi_caps = {
1139 .has_qspick = true,
1140 .has_ricr = true,
1141};
1142
2fd1b97f
TA		 1143static const struct atmel_qspi_caps atmel_sama7g5_ospi_caps = {
1144 .has_gclk = true,
1145 .octal = true,
1146};
1147
1148static const struct atmel_qspi_caps atmel_sama7g5_qspi_caps = {
1149 .has_gclk = true,
1150};
1151
24c8ff46
TA		 1152static const struct udevice_id atmel_qspi_ids[] = {
1153 {
1154 .compatible = "atmel,sama5d2-qspi",
1155 .data = (ulong)&atmel_sama5d2_qspi_caps,
1156 },
1157 {
1158 .compatible = "microchip,sam9x60-qspi",
1159 .data = (ulong)&atmel_sam9x60_qspi_caps,
1160 },
2fd1b97f
TA		 1161 {
1162 .compatible = "microchip,sama7g5-ospi",
1163 .data = (ulong)&atmel_sama7g5_ospi_caps,
1164 },
1165 {
1166 .compatible = "microchip,sama7g5-qspi",
1167 .data = (ulong)&atmel_sama7g5_qspi_caps,
1168 },
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TA		 1169 { /* sentinel */ }
1170};
1171
1172U_BOOT_DRIVER(atmel_qspi) = {
1173 .name = "atmel_qspi",
1174 .id = UCLASS_SPI,
1175 .of_match = atmel_qspi_ids,
1176 .ops = &atmel_qspi_ops,
41575d8e 1177 .priv_auto = sizeof(struct atmel_qspi),
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TA		 1178 .probe = atmel_qspi_probe,
1179};
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