[u-boot.git] / include / configs / MPC8349EMDS_SDRAM.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * (C) Copyright 2006-2010
 * Wolfgang Denk, DENX Software Engineering, [email protected].
 */

/*
 * mpc8349emds board configuration file
 *
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_E300		1	/* E300 Family */

#undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */

/*
 * DDR Setup
 */
#define CONFIG_DDR_ECC			/* support DDR ECC function */
#define CONFIG_DDR_ECC_CMD		/* use DDR ECC user commands */
#define CONFIG_SPD_EEPROM		/* use SPD EEPROM for DDR setup*/

/*
 * SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver
 * unselect it to use old spd_sdram.c
 */
#define CONFIG_SYS_SPD_BUS_NUM	0
#define SPD_EEPROM_ADDRESS1	0x52
#define SPD_EEPROM_ADDRESS2	0x51
#define CONFIG_DIMM_SLOTS_PER_CTLR	2
#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE	0xDeadBeef

/*
 * 32-bit data path mode.
 *
 * Please note that using this mode for devices with the real density of 64-bit
 * effectively reduces the amount of available memory due to the effect of
 * wrapping around while translating address to row/columns, for example in the
 * 256MB module the upper 128MB get aliased with contents of the lower
 * 128MB); normally this define should be used for devices with real 32-bit
 * data path.
 */
#undef CONFIG_DDR_32BIT

#define CONFIG_SYS_SDRAM_BASE	0x00000000	/* DDR is system memory*/
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN \
					| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
#undef  CONFIG_DDR_2T_TIMING

/*
 * DDRCDR - DDR Control Driver Register
 */
#define CONFIG_SYS_DDRCDR_VALUE	0x80080001

#if defined(CONFIG_SPD_EEPROM)
/*
 * Determine DDR configuration from I2C interface.
 */
#define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
#else
/*
 * Manually set up DDR parameters
 */
#define CONFIG_SYS_DDR_SIZE		256		/* MB */
#if defined(CONFIG_DDR_II)
#define CONFIG_SYS_DDRCDR		0x80080001
#define CONFIG_SYS_DDR_CS2_BNDS		0x0000000f
#define CONFIG_SYS_DDR_CS2_CONFIG	0x80330102
#define CONFIG_SYS_DDR_TIMING_0		0x00220802
#define CONFIG_SYS_DDR_TIMING_1		0x38357322
#define CONFIG_SYS_DDR_TIMING_2		0x2f9048c8
#define CONFIG_SYS_DDR_TIMING_3		0x00000000
#define CONFIG_SYS_DDR_CLK_CNTL		0x02000000
#define CONFIG_SYS_DDR_MODE		0x47d00432
#define CONFIG_SYS_DDR_MODE2		0x8000c000
#define CONFIG_SYS_DDR_INTERVAL		0x03cf0080
#define CONFIG_SYS_DDR_SDRAM_CFG	0x43000000
#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
#else
#define CONFIG_SYS_DDR_CS2_CONFIG	(CSCONFIG_EN \
				| CSCONFIG_ROW_BIT_13 \
				| CSCONFIG_COL_BIT_10)
#define CONFIG_SYS_DDR_TIMING_1	0x36332321
#define CONFIG_SYS_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
#define CONFIG_SYS_DDR_CONTROL	0xc2000000	/* unbuffered,no DYN_PWR */
#define CONFIG_SYS_DDR_INTERVAL	0x04060100	/* autocharge,no open page */

#if defined(CONFIG_DDR_32BIT)
/* set burst length to 8 for 32-bit data path */
				/* DLL,normal,seq,4/2.5, 8 burst len */
#define CONFIG_SYS_DDR_MODE	0x00000023
#else
/* the default burst length is 4 - for 64-bit data path */
				/* DLL,normal,seq,4/2.5, 4 burst len */
#define CONFIG_SYS_DDR_MODE	0x00000022
#endif
#endif
#endif

/*
 * SDRAM on the Local Bus
 */
#define CONFIG_SYS_LBC_SDRAM_BASE	0xF0000000	/* Localbus SDRAM */
#define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */

/*
 * FLASH on the Local Bus
 */
#define CONFIG_SYS_FLASH_BASE		0xFE000000	/* start of FLASH   */
#define CONFIG_SYS_FLASH_SIZE		32	/* max flash size in MB */

#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max sectors per device */

#undef CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */

#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#else
#undef  CONFIG_SYS_RAMBOOT
#endif

/*
 * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
 */
#define CONFIG_SYS_BCSR			0xE2400000
					/* Access window base at BCSR base */
#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000	/* Initial RAM addr */
#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in RAM*/

#define CONFIG_SYS_GBL_DATA_OFFSET	\
			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_LEN	(512 * 1024)	/* Reserve 512 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN	(256 * 1024)	/* Reserved for malloc */

/*
 * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory.
 */

/* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */
/*
 * Base Register 2 and Option Register 2 configure SDRAM.
 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 *
 * For BR2, need:
 *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 *    port-size = 32-bits = BR2[19:20] = 11
 *    no parity checking = BR2[21:22] = 00
 *    SDRAM for MSEL = BR2[24:26] = 011
 *    Valid = BR[31] = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
 */

/*
 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 *
 * For OR2, need:
 *    64MB mask for AM, OR2[0:7] = 1111 1100
 *                 XAM, OR2[17:18] = 11
 *    9 columns OR2[19-21] = 010
 *    13 rows   OR2[23-25] = 100
 *    EAD set for extra time OR[31] = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
 */


				/* LB sdram refresh timer, about 6us */
#define CONFIG_SYS_LBC_LSRT	0x32000000
				/* LB refresh timer prescal, 266MHz/32 */
#define CONFIG_SYS_LBC_MRTPR	0x20000000

#define CONFIG_SYS_LBC_LSDMR_COMMON    (LSDMR_RFEN	\
				| LSDMR_BSMA1516	\
				| LSDMR_RFCR8		\
				| LSDMR_PRETOACT6	\
				| LSDMR_ACTTORW3	\
				| LSDMR_BL8		\
				| LSDMR_WRC3		\
				| LSDMR_CL3)

/*
 * SDRAM Controller configuration sequence.
 */
#define CONFIG_SYS_LBC_LSDMR_1	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
#define CONFIG_SYS_LBC_LSDMR_2	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
#define CONFIG_SYS_LBC_LSDMR_3	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
#define CONFIG_SYS_LBC_LSDMR_4	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
#define CONFIG_SYS_LBC_LSDMR_5	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)

/*
 * Serial Port
 */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE    1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_BAUDRATE_TABLE  \
		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}

#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_IMMR+0x4500)
#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_IMMR+0x4600)

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
#define CONFIG_SYS_FSL_I2C2_SPEED	400000
#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }

/* SPI */
#undef CONFIG_SOFT_SPI			/* SPI bit-banged */

/* GPIOs.  Used as SPI chip selects */
#define CONFIG_SYS_GPIO1_PRELIM
#define CONFIG_SYS_GPIO1_DIR		0xC0000000  /* SPI CS on 0, LED on 1 */
#define CONFIG_SYS_GPIO1_DAT		0xC0000000  /* Both are active LOW */

/* TSEC */
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
#define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
#define CONFIG_SYS_TSEC2_OFFSET 0x25000
#define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)

/* USB */
#define CONFIG_SYS_USE_MPC834XSYS_USB_PHY	1 /* Use SYS board PHY */

/*
 * General PCI
 * Addresses are mapped 1-1.
 */
#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI1_IO_BASE		0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS		0xE2000000
#define CONFIG_SYS_PCI1_IO_SIZE		0x00100000	/* 1M */

#define CONFIG_SYS_PCI2_MEM_BASE	0xA0000000
#define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BASE
#define CONFIG_SYS_PCI2_MEM_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI2_MMIO_BASE	0xB0000000
#define CONFIG_SYS_PCI2_MMIO_PHYS	CONFIG_SYS_PCI2_MMIO_BASE
#define CONFIG_SYS_PCI2_MMIO_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI2_IO_BASE		0x00000000
#define CONFIG_SYS_PCI2_IO_PHYS		0xE2100000
#define CONFIG_SYS_PCI2_IO_SIZE		0x00100000	/* 1M */

#if defined(CONFIG_PCI)

#define CONFIG_83XX_PCI_STREAMING

#undef CONFIG_EEPRO100
#undef CONFIG_TULIP

#if !defined(CONFIG_PCI_PNP)
	#define PCI_ENET0_IOADDR	0xFIXME
	#define PCI_ENET0_MEMADDR	0xFIXME
	#define PCI_IDSEL_NUMBER	0x0c	/* slot0->3(IDSEL)=12->15 */
#endif

#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957  /* Freescale */

#endif	/* CONFIG_PCI */

/*
 * TSEC configuration
 */

#if defined(CONFIG_TSEC_ENET)

#define CONFIG_GMII		1	/* MII PHY management */
#define CONFIG_TSEC1		1
#define CONFIG_TSEC1_NAME	"TSEC0"
#define CONFIG_TSEC2		1
#define CONFIG_TSEC2_NAME	"TSEC1"
#define TSEC1_PHY_ADDR		0
#define TSEC2_PHY_ADDR		1
#define TSEC1_PHYIDX		0
#define TSEC2_PHYIDX		0
#define TSEC1_FLAGS		TSEC_GIGABIT
#define TSEC2_FLAGS		TSEC_GIGABIT

/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME		"TSEC0"

#endif	/* CONFIG_TSEC_ENET */

/*
 * Configure on-board RTC
 */
#define CONFIG_RTC_DS1374		/* use ds1374 rtc via i2c */
#define CONFIG_SYS_I2C_RTC_ADDR	0x68	/* at address 0x68 */

/*
 * Environment
 */
#ifndef CONFIG_SYS_RAMBOOT
/* Address and size of Redundant Environment Sector	*/
#endif

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE

/*
 * Command line configuration.
 */

#undef CONFIG_WATCHDOG			/* watchdog disabled */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 256 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
				/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)
#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */

#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */

/*
 * System performance
 */
#define CONFIG_SYS_SPCR_TSEC1EP	3	/* TSEC1 emergency priority (0-3) */
#define CONFIG_SYS_SPCR_TSEC2EP	3	/* TSEC2 emergency priority (0-3) */
#define CONFIG_SYS_SCCR_TSEC1CM	1	/* TSEC1 clock mode (0-3) */
#define CONFIG_SYS_SCCR_TSEC2CM	1	/* TSEC2 & I2C0 clock mode (0-3) */

/* System IO Config */
#define CONFIG_SYS_SICRH 0
#define CONFIG_SYS_SICRL SICRL_LDP_A

#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
#endif

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
#endif

/*
 * Environment Configuration
 */
#define CONFIG_ENV_OVERWRITE

#if defined(CONFIG_TSEC_ENET)
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH0
#endif

#define CONFIG_HOSTNAME		"mpc8349emds"
#define CONFIG_ROOTPATH		"/nfsroot/rootfs"
#define CONFIG_BOOTFILE		"uImage"

#define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"hostname=mpc8349emds\0"					\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
	"flash_nfs=run nfsargs addip addtty;"				\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip addtty;"				\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"	\
		"bootm\0"						\
	"load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0"		\
	"update=protect off fe000000 fe03ffff; "			\
		"era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\
	"upd=run load update\0"						\
	"fdtaddr=780000\0"						\
	"fdtfile=mpc834x_mds.dtb\0"					\
	""

#define CONFIG_NFSBOOTCOMMAND						\
	"setenv bootargs root=/dev/nfs rw "				\
		"nfsroot=$serverip:$rootpath "				\
		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"	\
							"$netdev:off "	\
		"console=$consoledev,$baudrate $othbootargs;"		\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr - $fdtaddr"

#define CONFIG_RAMBOOTCOMMAND						\
	"setenv bootargs root=/dev/ram rw "				\
		"console=$consoledev,$baudrate $othbootargs;"		\
	"tftp $ramdiskaddr $ramdiskfile;"				\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr $ramdiskaddr $fdtaddr"

#define CONFIG_BOOTCOMMAND	"run flash_self"

#endif	/* __CONFIG_H */
Commit	Line	Data
ddc935fc MS	1	/* SPDX-License-Identifier: GPL-2.0+ */
	2	/*
	3	* (C) Copyright 2006-2010
	4	* Wolfgang Denk, DENX Software Engineering, [email protected].
	5	*/
	6
	7	/*
	8	* mpc8349emds board configuration file
	9	*
	10	*/
	11
	12	#ifndef __CONFIG_H
	13	#define __CONFIG_H
	14
	15	/*
	16	* High Level Configuration Options
	17	*/
	18	#define CONFIG_E300 1 /* E300 Family */
	19
ddc935fc	20	#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
ddc935fc MS	21
	22	/*
	23	* DDR Setup
	24	*/
	25	#define CONFIG_DDR_ECC /* support DDR ECC function */
	26	#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
	27	#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
	28
	29	/*
	30	* SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver
	31	* unselect it to use old spd_sdram.c
	32	*/
	33	#define CONFIG_SYS_SPD_BUS_NUM 0
	34	#define SPD_EEPROM_ADDRESS1 0x52
	35	#define SPD_EEPROM_ADDRESS2 0x51
	36	#define CONFIG_DIMM_SLOTS_PER_CTLR 2
	37	#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
	38	#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
	39	#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
	40
	41	/*
	42	* 32-bit data path mode.
	43	*
	44	* Please note that using this mode for devices with the real density of 64-bit
	45	* effectively reduces the amount of available memory due to the effect of
	46	* wrapping around while translating address to row/columns, for example in the
	47	* 256MB module the upper 128MB get aliased with contents of the lower
	48	* 128MB); normally this define should be used for devices with real 32-bit
	49	* data path.
	50	*/
	51	#undef CONFIG_DDR_32BIT
	52
8a81bfd2	53	#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
ddc935fc MS	54	#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
	55	\| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
	56	#undef CONFIG_DDR_2T_TIMING
	57
	58	/*
	59	* DDRCDR - DDR Control Driver Register
	60	*/
	61	#define CONFIG_SYS_DDRCDR_VALUE 0x80080001
	62
	63	#if defined(CONFIG_SPD_EEPROM)
	64	/*
	65	* Determine DDR configuration from I2C interface.
	66	*/
	67	#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
	68	#else
	69	/*
	70	* Manually set up DDR parameters
	71	*/
	72	#define CONFIG_SYS_DDR_SIZE 256 /* MB */
	73	#if defined(CONFIG_DDR_II)
	74	#define CONFIG_SYS_DDRCDR 0x80080001
	75	#define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f
	76	#define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102
	77	#define CONFIG_SYS_DDR_TIMING_0 0x00220802
	78	#define CONFIG_SYS_DDR_TIMING_1 0x38357322
	79	#define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8
	80	#define CONFIG_SYS_DDR_TIMING_3 0x00000000
	81	#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
	82	#define CONFIG_SYS_DDR_MODE 0x47d00432
	83	#define CONFIG_SYS_DDR_MODE2 0x8000c000
	84	#define CONFIG_SYS_DDR_INTERVAL 0x03cf0080
	85	#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
	86	#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
	87	#else
	88	#define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \
	89	\| CSCONFIG_ROW_BIT_13 \
	90	\| CSCONFIG_COL_BIT_10)
	91	#define CONFIG_SYS_DDR_TIMING_1 0x36332321
	92	#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
	93	#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
	94	#define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */
	95
	96	#if defined(CONFIG_DDR_32BIT)
	97	/* set burst length to 8 for 32-bit data path */
	98	/* DLL,normal,seq,4/2.5, 8 burst len */
	99	#define CONFIG_SYS_DDR_MODE 0x00000023
	100	#else
	101	/* the default burst length is 4 - for 64-bit data path */
	102	/* DLL,normal,seq,4/2.5, 4 burst len */
	103	#define CONFIG_SYS_DDR_MODE 0x00000022
	104	#endif
	105	#endif
	106	#endif
	107
	108	/*
	109	* SDRAM on the Local Bus
	110	*/
	111	#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */
	112	#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
	113
	114	/*
	115	* FLASH on the Local Bus
	116	*/
	117	#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
118	#define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */
119
ddc935fc MS	120	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
	121	#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
	122
	123	#undef CONFIG_SYS_FLASH_CHECKSUM
	124	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	125	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	126
	127	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
	128
	129	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
	130	#define CONFIG_SYS_RAMBOOT
	131	#else
	132	#undef CONFIG_SYS_RAMBOOT
	133	#endif
	134
	135	/*
	136	* BCSR register on local bus 32KB, 8-bit wide for MDS config reg
	137	*/
	138	#define CONFIG_SYS_BCSR 0xE2400000
	139	/* Access window base at BCSR base */
ddc935fc MS	140	#define CONFIG_SYS_INIT_RAM_LOCK 1
	141	#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
	142	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
	143
	144	#define CONFIG_SYS_GBL_DATA_OFFSET \
	145	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	146	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
	147
	148	#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
	149	#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
	150
ddc935fc MS	151	/*
	152	* The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory.
	153	*/
	154
	155	/* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */
	156	/*
	157	* Base Register 2 and Option Register 2 configure SDRAM.
	158	* The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
	159	*
	160	* For BR2, need:
	161	* Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
	162	* port-size = 32-bits = BR2[19:20] = 11
	163	* no parity checking = BR2[21:22] = 00
	164	* SDRAM for MSEL = BR2[24:26] = 011
	165	* Valid = BR[31] = 1
	166	*
	167	* 0 4 8 12 16 20 24 28
	168	* 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
	169	*/
	170
ddc935fc MS	171	/*
	172	* The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
	173	*
	174	* For OR2, need:
	175	* 64MB mask for AM, OR2[0:7] = 1111 1100
	176	* XAM, OR2[17:18] = 11
	177	* 9 columns OR2[19-21] = 010
	178	* 13 rows OR2[23-25] = 100
	179	* EAD set for extra time OR[31] = 1
	180	*
	181	* 0 4 8 12 16 20 24 28
	182	* 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
	183	*/
	184
ddc935fc MS	185
	186	/* LB sdram refresh timer, about 6us */
	187	#define CONFIG_SYS_LBC_LSRT 0x32000000
	188	/* LB refresh timer prescal, 266MHz/32 */
	189	#define CONFIG_SYS_LBC_MRTPR 0x20000000
	190
	191	#define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \
	192	\| LSDMR_BSMA1516 \
	193	\| LSDMR_RFCR8 \
	194	\| LSDMR_PRETOACT6 \
	195	\| LSDMR_ACTTORW3 \
	196	\| LSDMR_BL8 \
	197	\| LSDMR_WRC3 \
	198	\| LSDMR_CL3)
	199
	200	/*
	201	* SDRAM Controller configuration sequence.
	202	*/
	203	#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON \| LSDMR_OP_PCHALL)
	204	#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON \| LSDMR_OP_ARFRSH)
	205	#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON \| LSDMR_OP_ARFRSH)
	206	#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON \| LSDMR_OP_MRW)
	207	#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON \| LSDMR_OP_NORMAL)
	208
	209	/*
	210	* Serial Port
	211	*/
	212	#define CONFIG_SYS_NS16550_SERIAL
	213	#define CONFIG_SYS_NS16550_REG_SIZE 1
	214	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
	215
	216	#define CONFIG_SYS_BAUDRATE_TABLE \
	217	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
	218
	219	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
	220	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
	221
	222	/* I2C */
	223	#define CONFIG_SYS_I2C
	224	#define CONFIG_SYS_I2C_FSL
	225	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	226	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	227	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
	228	#define CONFIG_SYS_FSL_I2C2_SPEED 400000
	229	#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
	230	#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
	231	#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
	232
	233	/* SPI */
	234	#undef CONFIG_SOFT_SPI /* SPI bit-banged */
	235
	236	/* GPIOs. Used as SPI chip selects */
	237	#define CONFIG_SYS_GPIO1_PRELIM
	238	#define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */
	239	#define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */
	240
	241	/* TSEC */
	242	#define CONFIG_SYS_TSEC1_OFFSET 0x24000
	243	#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
	244	#define CONFIG_SYS_TSEC2_OFFSET 0x25000
	245	#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
	246
	247	/* USB */
	248	#define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */
249
250	/*
251	* General PCI
252	* Addresses are mapped 1-1.
253	*/
254	#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
255	#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
256	#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
257	#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
258	#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
259	#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
260	#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
261	#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
262	#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
263
264	#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
265	#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
266	#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
267	#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
268	#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
269	#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
270	#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
271	#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
272	#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
273
274	#if defined(CONFIG_PCI)
275
ddc935fc MS	276	#define CONFIG_83XX_PCI_STREAMING
	277
	278	#undef CONFIG_EEPRO100
	279	#undef CONFIG_TULIP
	280
	281	#if !defined(CONFIG_PCI_PNP)
	282	#define PCI_ENET0_IOADDR 0xFIXME
	283	#define PCI_ENET0_MEMADDR 0xFIXME
	284	#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
	285	#endif
	286
	287	#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
	288	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
	289
	290	#endif /* CONFIG_PCI */
	291
	292	/*
	293	* TSEC configuration
	294	*/
	295
	296	#if defined(CONFIG_TSEC_ENET)
	297
	298	#define CONFIG_GMII 1 /* MII PHY management */
	299	#define CONFIG_TSEC1 1
	300	#define CONFIG_TSEC1_NAME "TSEC0"
	301	#define CONFIG_TSEC2 1
	302	#define CONFIG_TSEC2_NAME "TSEC1"
	303	#define TSEC1_PHY_ADDR 0
	304	#define TSEC2_PHY_ADDR 1
	305	#define TSEC1_PHYIDX 0
	306	#define TSEC2_PHYIDX 0
	307	#define TSEC1_FLAGS TSEC_GIGABIT
	308	#define TSEC2_FLAGS TSEC_GIGABIT
	309
	310	/* Options are: TSEC[0-1] */
	311	#define CONFIG_ETHPRIME "TSEC0"
	312
	313	#endif /* CONFIG_TSEC_ENET */
	314
	315	/*
	316	* Configure on-board RTC
	317	*/
	318	#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
	319	#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
	320
	321	/*
	322	* Environment
	323	*/
	324	#ifndef CONFIG_SYS_RAMBOOT
ddc935fc	325	/* Address and size of Redundant Environment Sector */
ddc935fc MS	326	#endif
	327
	328	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	329	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
	330
	331	/*
	332	* BOOTP options
	333	*/
	334	#define CONFIG_BOOTP_BOOTFILESIZE
	335
	336	/*
	337	* Command line configuration.
	338	*/
	339
	340	#undef CONFIG_WATCHDOG /* watchdog disabled */
	341
	342	/*
	343	* Miscellaneous configurable options
	344	*/
	345	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
	346
	347	/*
	348	* For booting Linux, the board info and command line data
	349	* have to be in the first 256 MB of memory, since this is
	350	* the maximum mapped by the Linux kernel during initialization.
	351	*/
	352	/* Initial Memory map for Linux*/
	353	#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
	354	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
	355
	356	#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
	357
ddc935fc MS	358	/*
	359	* System performance
	360	*/
ddc935fc MS	361	#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
	362	#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
	363	#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
	364	#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
	365
	366	/* System IO Config */
	367	#define CONFIG_SYS_SICRH 0
	368	#define CONFIG_SYS_SICRL SICRL_LDP_A
	369
ddc935fc MS	370	#ifdef CONFIG_PCI
ddc935fc MS	371	#define CONFIG_PCI_INDIRECT_BRIDGE
ddc935fc MS	372	#endif
ddc935fc MS	373
ddc935fc MS	374	#if defined(CONFIG_CMD_KGDB)
	375	#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
	376	#endif
	377
	378	/*
	379	* Environment Configuration
	380	*/
	381	#define CONFIG_ENV_OVERWRITE
	382
	383	#if defined(CONFIG_TSEC_ENET)
	384	#define CONFIG_HAS_ETH1
	385	#define CONFIG_HAS_ETH0
	386	#endif
	387
	388	#define CONFIG_HOSTNAME "mpc8349emds"
	389	#define CONFIG_ROOTPATH "/nfsroot/rootfs"
	390	#define CONFIG_BOOTFILE "uImage"
	391
	392	#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
	393
ddc935fc MS	394	#define CONFIG_EXTRA_ENV_SETTINGS \
	395	"netdev=eth0\0" \
	396	"hostname=mpc8349emds\0" \
	397	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	398	"nfsroot=${serverip}:${rootpath}\0" \
	399	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	400	"addip=setenv bootargs ${bootargs} " \
	401	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	402	":${hostname}:${netdev}:off panic=1\0" \
	403	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
	404	"flash_nfs=run nfsargs addip addtty;" \
	405	"bootm ${kernel_addr}\0" \
	406	"flash_self=run ramargs addip addtty;" \
	407	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
	408	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
	409	"bootm\0" \
	410	"load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \
	411	"update=protect off fe000000 fe03ffff; " \
	412	"era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\
	413	"upd=run load update\0" \
	414	"fdtaddr=780000\0" \
	415	"fdtfile=mpc834x_mds.dtb\0" \
	416	""
	417
	418	#define CONFIG_NFSBOOTCOMMAND \
	419	"setenv bootargs root=/dev/nfs rw " \
	420	"nfsroot=$serverip:$rootpath " \
	421	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
	422	"$netdev:off " \
	423	"console=$consoledev,$baudrate $othbootargs;" \
	424	"tftp $loadaddr $bootfile;" \
	425	"tftp $fdtaddr $fdtfile;" \
	426	"bootm $loadaddr - $fdtaddr"
	427
	428	#define CONFIG_RAMBOOTCOMMAND \
	429	"setenv bootargs root=/dev/ram rw " \
	430	"console=$consoledev,$baudrate $othbootargs;" \
	431	"tftp $ramdiskaddr $ramdiskfile;" \
	432	"tftp $loadaddr $bootfile;" \
	433	"tftp $fdtaddr $fdtfile;" \
	434	"bootm $loadaddr $ramdiskaddr $fdtaddr"
	435
	436	#define CONFIG_BOOTCOMMAND "run flash_self"
	437
	438	#endif /* __CONFIG_H */