[u-boot.git] / include / configs / EXBITGEN.h

/*
 * (C) Copyright 2000-2004
 * Wolfgang Denk, DENX Software Engineering, [email protected].
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_405GP		1	/* This is a PPC405GP CPU	*/
#define CONFIG_4xx		1	/* ...member of PPC4xx family   */
#define CONFIG_EXBITGEN		1	/* on a Exbit Generic board     */

#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/

#define CONFIG_SYS_CLK_FREQ     25000000 /* external frequency to pll   */

/* I2C configuration */
#define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
#define CONFIG_SYS_I2C_SPEED		40000	/* I2C speed			*/
#define CONFIG_SYS_I2C_SLAVE		0x7F	/* I2C slave address		*/

/* environment is in EEPROM */
#define CONFIG_ENV_IS_IN_EEPROM    1
#undef CONFIG_ENV_IS_IN_FLASH
#undef CONFIG_ENV_IS_IN_NVRAM

#ifdef CONFIG_ENV_IS_IN_EEPROM
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x56    /* 1010110 */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1	/* 8-bit internal addressing */
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	1	/* ... and 1 bit in I2C address */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3	/* 4 bytes per page */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	40	/* write takes up to 40 msec */
#define CONFIG_ENV_OFFSET		4	/* Offset of Environment Sector	*/
#define	CONFIG_ENV_SIZE		350	/* that is 350 bytes only!	*/
#endif

#define CONFIG_BOOTDELAY	10	/* autoboot after 10 seconds	*/
/* Explanation:
   autbooting is altogether disabled and cannot be
   enabled if CONFIG_BOOTDELAY is negative.
   If you want shorter bootdelay, then
   - "setenv bootdelay <delay>" to the proper value
*/

#define CONFIG_BOOTCOMMAND	"bootm 20400000 20800000"

#define CONFIG_BOOTARGS		"root=/dev/ram "  \
				"ramdisk_size=32768 " \
				"console=ttyS0,115200 " \
				"ram=128M debug"

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#define CONFIG_MII		1	/* MII PHY management		*/
#define CONFIG_PHY_ADDR		0	/* PHY address			*/


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>


#undef CONFIG_WATCHDOG			/* watchdog disabled		*/

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

/* UART configuration */
#define CONFIG_SYS_BASE_BAUD		691200

/* Default baud rate */
#define CONFIG_BAUDRATE		115200

/* The following table includes the supported baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE      \
	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
	 57600, 115200, 230400, 460800, 921600 }

#define CONFIG_SYS_CLKS_IN_HZ		1	/* everything, incl board info, in Hz */

#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */

#define	CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks	*/

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#undef CONFIG_PCI			/* no pci support	        */

/*-----------------------------------------------------------------------
 * External peripheral base address
 *-----------------------------------------------------------------------
 */
#undef  CONFIG_IDE_PCMCIA               /* no pcmcia interface required */
#undef  CONFIG_IDE_LED                  /* no led for ide supported     */
#undef  CONFIG_IDE_RESET                /* no reset for ide supported   */

#define	CONFIG_SYS_KEY_REG_BASE_ADDR	0xF0100000
#define	CONFIG_SYS_IR_REG_BASE_ADDR	0xF0200000
#define	CONFIG_SYS_FPGA_REG_BASE_ADDR	0xF0300000

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH0_BASE		0xFFF80000
#define CONFIG_SYS_FLASH0_SIZE		0x00080000
#define CONFIG_SYS_FLASH1_BASE		0x20000000
#define CONFIG_SYS_FLASH1_SIZE		0x02000000
#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_FLASH0_BASE
#define CONFIG_SYS_FLASH_SIZE		CONFIG_SYS_FLASH0_SIZE
#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN		(192 * 1024)	/* Reserve 196 kB for Monitor	*/
#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/

#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH0_BASE
#define CONFIG_SYS_RAMSTART
#endif

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	5	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#ifdef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_OFFSET		0x00060000 /* Offset of Environment Sector      */
#define	CONFIG_ENV_SIZE		0x00010000 /* Total Size of Environment Sector	*/
#define CONFIG_ENV_SECT_SIZE	0x00010000 /* see README - env sector total size */
#endif

/* On Chip Memory location/size */
#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
#define CONFIG_SYS_OCM_DATA_SIZE	0x1000

/* Global info and initial stack */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of on-chip SRAM	*/
#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/
#define CONFIG_SYS_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
#endif
#endif	/* __CONFIG_H */
Commit	Line	Data
d1cbe85b	1	/*
c837dcb1	2	* (C) Copyright 2000-2004
d1cbe85b WD	3	* Wolfgang Denk, DENX Software Engineering, [email protected].
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* board/config.h - configuration options, board specific
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/*
	32	* High Level Configuration Options
	33	* (easy to change)
	34	*/
	35
53677ef1	36	#define CONFIG_405GP 1 /* This is a PPC405GP CPU */
d1cbe85b WD	37	#define CONFIG_4xx 1 /* ...member of PPC4xx family */
	38	#define CONFIG_EXBITGEN 1 /* on a Exbit Generic board */
	39
c837dcb1	40	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
d1cbe85b WD	41
	42	#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
	43
	44	/* I2C configuration */
	45	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
6d0f6bcf JCPV	46	#define CONFIG_SYS_I2C_SPEED 40000 /* I2C speed */
6d0f6bcf JCPV	47	#define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */
d1cbe85b WD	48
d1cbe85b WD	49	/* environment is in EEPROM */
bb1f8b4f	50	#define CONFIG_ENV_IS_IN_EEPROM 1
5a1aceb0	51	#undef CONFIG_ENV_IS_IN_FLASH
9314cee6	52	#undef CONFIG_ENV_IS_IN_NVRAM
d1cbe85b	53
bb1f8b4f	54	#ifdef CONFIG_ENV_IS_IN_EEPROM
6d0f6bcf JCPV	55	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x56 /* 1010110 */
	56	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* 8-bit internal addressing */
	57	#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 1 /* ... and 1 bit in I2C address */
	58	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* 4 bytes per page */
	59	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 40 /* write takes up to 40 msec */
0e8d1586 JCPV	60	#define CONFIG_ENV_OFFSET 4 /* Offset of Environment Sector */
0e8d1586 JCPV	61	#define CONFIG_ENV_SIZE 350 /* that is 350 bytes only! */
d1cbe85b WD	62	#endif
	63
	64	#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */
	65	/* Explanation:
	66	autbooting is altogether disabled and cannot be
	67	enabled if CONFIG_BOOTDELAY is negative.
945af8d7	68	If you want shorter bootdelay, then
d1cbe85b WD	69	- "setenv bootdelay <delay>" to the proper value
	70	*/
	71
	72	#define CONFIG_BOOTCOMMAND "bootm 20400000 20800000"
	73
	74	#define CONFIG_BOOTARGS "root=/dev/ram " \
	75	"ramdisk_size=32768 " \
	76	"console=ttyS0,115200 " \
	77	"ram=128M debug"
	78
	79	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	80	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
d1cbe85b WD	81
	82	#define CONFIG_MII 1 /* MII PHY management */
	83	#define CONFIG_PHY_ADDR 0 /* PHY address */
	84
d1cbe85b	85
11799434 JL	86	/*
	87	* BOOTP options
	88	*/
	89	#define CONFIG_BOOTP_BOOTFILESIZE
	90	#define CONFIG_BOOTP_BOOTPATH
	91	#define CONFIG_BOOTP_GATEWAY
	92	#define CONFIG_BOOTP_HOSTNAME
	93
	94
dcaa7156 JL	95	/*
	96	* Command line configuration.
	97	*/
	98	#include <config_cmd_default.h>
	99
d1cbe85b WD	100
	101	#undef CONFIG_WATCHDOG /* watchdog disabled */
	102
	103	/*
	104	* Miscellaneous configurable options
	105	*/
6d0f6bcf JCPV	106	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	107	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
dcaa7156	108	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	109	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
d1cbe85b	110	#else
6d0f6bcf	111	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
d1cbe85b	112	#endif
6d0f6bcf JCPV	113	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	114	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	115	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
d1cbe85b	116
6d0f6bcf JCPV	117	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
6d0f6bcf JCPV	118	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
d1cbe85b WD	119
d1cbe85b WD	120	/* UART configuration */
6d0f6bcf	121	#define CONFIG_SYS_BASE_BAUD 691200
d1cbe85b WD	122
	123	/* Default baud rate */
	124	#define CONFIG_BAUDRATE 115200
945af8d7	125
d1cbe85b	126	/* The following table includes the supported baudrates */
6d0f6bcf	127	#define CONFIG_SYS_BAUDRATE_TABLE \
945af8d7 WD	128	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
945af8d7 WD	129	57600, 115200, 230400, 460800, 921600 }
d1cbe85b	130
6d0f6bcf	131	#define CONFIG_SYS_CLKS_IN_HZ 1 /* everything, incl board info, in Hz */
d1cbe85b	132
6d0f6bcf JCPV	133	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
6d0f6bcf JCPV	134	#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
d1cbe85b	135
6d0f6bcf	136	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
d1cbe85b WD	137
	138	/*-----------------------------------------------------------------------
	139	* PCI stuff
	140	*-----------------------------------------------------------------------
	141	*/
	142	#undef CONFIG_PCI /* no pci support */
	143
	144	/*-----------------------------------------------------------------------
	145	* External peripheral base address
	146	*-----------------------------------------------------------------------
	147	*/
	148	#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */
	149	#undef CONFIG_IDE_LED /* no led for ide supported */
	150	#undef CONFIG_IDE_RESET /* no reset for ide supported */
	151
6d0f6bcf JCPV	152	#define CONFIG_SYS_KEY_REG_BASE_ADDR 0xF0100000
	153	#define CONFIG_SYS_IR_REG_BASE_ADDR 0xF0200000
	154	#define CONFIG_SYS_FPGA_REG_BASE_ADDR 0xF0300000
d1cbe85b WD	155
	156	/*-----------------------------------------------------------------------
	157	* Start addresses for the final memory configuration
	158	* (Set up by the startup code)
6d0f6bcf	159	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
d1cbe85b	160	*/
6d0f6bcf JCPV	161	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	162	#define CONFIG_SYS_FLASH0_BASE 0xFFF80000
	163	#define CONFIG_SYS_FLASH0_SIZE 0x00080000
	164	#define CONFIG_SYS_FLASH1_BASE 0x20000000
	165	#define CONFIG_SYS_FLASH1_SIZE 0x02000000
	166	#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
	167	#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
	168	#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
	169	#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */
	170	#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
	171
	172	#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH0_BASE
	173	#define CONFIG_SYS_RAMSTART
d1cbe85b WD	174	#endif
	175
	176	/*
	177	* For booting Linux, the board info and command line data
	178	* have to be in the first 8 MB of memory, since this is
	179	* the maximum mapped by the Linux kernel during initialization.
	180	*/
6d0f6bcf	181	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
d1cbe85b WD	182	/*-----------------------------------------------------------------------
	183	* FLASH organization
	184	*/
6d0f6bcf JCPV	185	#define CONFIG_SYS_MAX_FLASH_BANKS 5 /* max number of memory banks */
6d0f6bcf JCPV	186	#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
d1cbe85b	187
6d0f6bcf JCPV	188	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	189	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
d1cbe85b	190
5a1aceb0	191	#ifdef CONFIG_ENV_IS_IN_FLASH
0e8d1586 JCPV	192	#define CONFIG_ENV_OFFSET 0x00060000 /* Offset of Environment Sector */
	193	#define CONFIG_ENV_SIZE 0x00010000 /* Total Size of Environment Sector */
	194	#define CONFIG_ENV_SECT_SIZE 0x00010000 /* see README - env sector total size */
d1cbe85b WD	195	#endif
	196
	197	/* On Chip Memory location/size */
6d0f6bcf JCPV	198	#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
6d0f6bcf JCPV	199	#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
d1cbe85b WD	200
d1cbe85b WD	201	/* Global info and initial stack */
6d0f6bcf JCPV	202	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of on-chip SRAM */
	203	#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
	204	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	205	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
	206	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
d1cbe85b	207
d1cbe85b WD	208	/*
	209	* Internal Definitions
	210	*
	211	* Boot Flags
	212	*/
	213	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	214	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	215
dcaa7156	216	#if defined(CONFIG_CMD_KGDB)
d1cbe85b WD	217	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
	218	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
	219	#endif
	220	#endif /* __CONFIG_H */