[u-boot.git] / cpu / ixp / cpu.c

/*
 * (C) Copyright 2002
 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Marius Groeger <[email protected]>
 *
 * (C) Copyright 2002
 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Alex Zuepke <[email protected]>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * CPU specific code
 */

#include <common.h>
#include <command.h>
#include <asm/arch/ixp425.h>

ulong loops_per_jiffy;

#ifdef CONFIG_USE_IRQ
DECLARE_GLOBAL_DATA_PTR;
#endif

#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo (void)
{
	unsigned long id;
	int speed = 0;

	asm ("mrc p15, 0, %0, c0, c0, 0":"=r" (id));

	puts("CPU:   Intel IXP425 at ");
	switch ((id & 0x000003f0) >> 4) {
	case 0x1c:
		loops_per_jiffy = 887467;
		speed = 533;
		break;

	case 0x1d:
		loops_per_jiffy = 666016;
		speed = 400;
		break;

	case 0x1f:
		loops_per_jiffy = 442901;
		speed = 266;
		break;
	}

	if (speed)
		printf("%d MHz\n", speed);
	else
		puts("unknown revision\n");

	return 0;
}
#endif /* CONFIG_DISPLAY_CPUINFO */

int cpu_init (void)
{
	/*
	 * setup up stacks if necessary
	 */
#ifdef CONFIG_USE_IRQ
	IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
#endif

#if defined(CONFIG_CMD_PCI) || defined (CONFIG_PCI)
	pci_init();
#endif
	return 0;
}

int cleanup_before_linux (void)
{
	/*
	 * this function is called just before we call linux
	 * it prepares the processor for linux
	 *
	 * just disable everything that can disturb booting linux
	 */

	unsigned long i;

	disable_interrupts ();

	/* turn off I-cache */
	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
	i &= ~0x1000;
	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));

	/* flush I-cache */
	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));

	return (0);
}

int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
	printf ("resetting ...\n");

	udelay (50000);				/* wait 50 ms */
	disable_interrupts ();
	reset_cpu (0);

	/*NOTREACHED*/
	return (0);
}

/* taken from blob */
void icache_enable (void)
{
	register u32 i;

	/* read control register */
	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));

	/* set i-cache */
	i |= 0x1000;

	/* write back to control register */
	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
}

void icache_disable (void)
{
	register u32 i;

	/* read control register */
	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));

	/* clear i-cache */
	i &= ~0x1000;

	/* write back to control register */
	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));

	/* flush i-cache */
	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
}

int icache_status (void)
{
	register u32 i;

	/* read control register */
	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));

	/* return bit */
	return (i & 0x1000);
}

/* we will never enable dcache, because we have to setup MMU first */
void dcache_enable (void)
{
	return;
}

void dcache_disable (void)
{
	return;
}

int dcache_status (void)
{
	return 0;					/* always off */
}

/* FIXME */
/*
void pci_init(void)
{
	return;
}
*/

#ifdef CONFIG_BOOTCOUNT_LIMIT

void bootcount_store (ulong a)
{
	volatile ulong *save_addr = (volatile ulong *)(CONFIG_SYS_BOOTCOUNT_ADDR);

	save_addr[0] = a;
	save_addr[1] = BOOTCOUNT_MAGIC;
}

ulong bootcount_load (void)
{
	volatile ulong *save_addr = (volatile ulong *)(CONFIG_SYS_BOOTCOUNT_ADDR);

	if (save_addr[1] != BOOTCOUNT_MAGIC)
		return 0;
	else
		return save_addr[0];
}

#endif /* CONFIG_BOOTCOUNT_LIMIT */
Commit	Line	Data
2d5b561e WD	1	/*
	2	* (C) Copyright 2002
	3	* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
	4	* Marius Groeger <[email protected]>
	5	*
	6	* (C) Copyright 2002
	7	* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
	8	* Alex Zuepke <[email protected]>
	9	*
	10	* See file CREDITS for list of people who contributed to this
	11	* project.
	12	*
	13	* This program is free software; you can redistribute it and/or
	14	* modify it under the terms of the GNU General Public License as
	15	* published by the Free Software Foundation; either version 2 of
	16	* the License, or (at your option) any later version.
	17	*
	18	* This program is distributed in the hope that it will be useful,
	19	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	21	* GNU General Public License for more details.
	22	*
	23	* You should have received a copy of the GNU General Public License
	24	* along with this program; if not, write to the Free Software
	25	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	26	* MA 02111-1307 USA
	27	*/
	28
	29	/*
	30	* CPU specific code
	31	*/
	32
	33	#include <common.h>
	34	#include <command.h>
	35	#include <asm/arch/ixp425.h>
	36
ba94a1bb WD	37	ulong loops_per_jiffy;
ba94a1bb WD	38
d87080b7 WD	39	#ifdef CONFIG_USE_IRQ
	40	DECLARE_GLOBAL_DATA_PTR;
	41	#endif
	42
ba94a1bb WD	43	#if defined(CONFIG_DISPLAY_CPUINFO)
	44	int print_cpuinfo (void)
	45	{
	46	unsigned long id;
	47	int speed = 0;
	48
	49	asm ("mrc p15, 0, %0, c0, c0, 0":"=r" (id));
	50
	51	puts("CPU: Intel IXP425 at ");
	52	switch ((id & 0x000003f0) >> 4) {
	53	case 0x1c:
	54	loops_per_jiffy = 887467;
	55	speed = 533;
	56	break;
	57
	58	case 0x1d:
	59	loops_per_jiffy = 666016;
	60	speed = 400;
	61	break;
	62
	63	case 0x1f:
	64	loops_per_jiffy = 442901;
	65	speed = 266;
	66	break;
	67	}
	68
	69	if (speed)
	70	printf("%d MHz\n", speed);
	71	else
	72	puts("unknown revision\n");
	73
	74	return 0;
	75	}
	76	#endif /* CONFIG_DISPLAY_CPUINFO */
	77
2d5b561e WD	78	int cpu_init (void)
	79	{
	80	/*
f6e20fc6	81	* setup up stacks if necessary
2d5b561e	82	*/
2d5b561e	83	#ifdef CONFIG_USE_IRQ
6d0f6bcf	84	IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
f6e20fc6	85	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
2d5b561e	86	#endif
f6e20fc6	87
3a1ed1e1	88	#if defined(CONFIG_CMD_PCI) \|\| defined (CONFIG_PCI)
f6e20fc6	89	pci_init();
ba94a1bb	90	#endif
2d5b561e WD	91	return 0;
	92	}
	93
	94	int cleanup_before_linux (void)
	95	{
	96	/*
	97	* this function is called just before we call linux
	98	* it prepares the processor for linux
	99	*
	100	* just disable everything that can disturb booting linux
	101	*/
	102
	103	unsigned long i;
	104
	105	disable_interrupts ();
	106
	107	/* turn off I-cache */
	108	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
	109	i &= ~0x1000;
	110	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
	111
	112	/* flush I-cache */
	113	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
	114
	115	return (0);
	116	}
	117
	118	int do_reset (cmd_tbl_t cmdtp, int flag, int argc, char argv[])
	119	{
f6e20fc6	120	printf ("resetting ...\n");
2d5b561e WD	121
	122	udelay (50000); /* wait 50 ms */
	123	disable_interrupts ();
	124	reset_cpu (0);
	125
	126	/NOTREACHED/
	127	return (0);
	128	}
	129
	130	/* taken from blob */
	131	void icache_enable (void)
	132	{
	133	register u32 i;
	134
	135	/* read control register */
	136	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
	137
	138	/* set i-cache */
	139	i \|= 0x1000;
	140
	141	/* write back to control register */
	142	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
	143	}
	144
	145	void icache_disable (void)
	146	{
	147	register u32 i;
	148
	149	/* read control register */
	150	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
	151
	152	/* clear i-cache */
	153	i &= ~0x1000;
	154
	155	/* write back to control register */
	156	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
	157
	158	/* flush i-cache */
	159	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
	160	}
	161
	162	int icache_status (void)
	163	{
	164	register u32 i;
	165
	166	/* read control register */
	167	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
	168
	169	/* return bit */
	170	return (i & 0x1000);
	171	}
	172
	173	/* we will never enable dcache, because we have to setup MMU first */
	174	void dcache_enable (void)
	175	{
	176	return;
	177	}
	178
	179	void dcache_disable (void)
	180	{
	181	return;
	182	}
	183
	184	int dcache_status (void)
185	{
186	return 0; /* always off */
187	}
188
189	/* FIXME */
a1191902	190	/*
2d5b561e WD	191	void pci_init(void)
	192	{
	193	return;
	194	}
a1191902	195	*/
ba94a1bb WD	196
	197	#ifdef CONFIG_BOOTCOUNT_LIMIT
	198
	199	void bootcount_store (ulong a)
	200	{
6d0f6bcf	201	volatile ulong save_addr = (volatile ulong )(CONFIG_SYS_BOOTCOUNT_ADDR);
ba94a1bb WD	202
	203	save_addr[0] = a;
	204	save_addr[1] = BOOTCOUNT_MAGIC;
	205	}
	206
	207	ulong bootcount_load (void)
	208	{
6d0f6bcf	209	volatile ulong save_addr = (volatile ulong )(CONFIG_SYS_BOOTCOUNT_ADDR);
ba94a1bb WD	210
	211	if (save_addr[1] != BOOTCOUNT_MAGIC)
	212	return 0;
	213	else
	214	return save_addr[0];
	215	}
	216
	217	#endif /* CONFIG_BOOTCOUNT_LIMIT */