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Squashed 'dts/upstream/' changes from b35b9bd1d4ee..7e08733c96c8
[u-boot.git] / src / arm64 / ti / k3-am68-sk-base-board.dts
CommitLineData
6bb92fcf 1// SPDX-License-Identifier: GPL-2.0-only OR MIT
53633a89 2/*
6bb92fcf 3 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
53633a89
TR		 4 *
5 * Base Board: https://www.ti.com/lit/zip/SPRR463
6 */
7
8/dts-v1/;
9
10#include "k3-am68-sk-som.dtsi"
11#include <dt-bindings/net/ti-dp83867.h>
12#include <dt-bindings/phy/phy-cadence.h>
13#include <dt-bindings/phy/phy.h>
14
15#include "k3-serdes.h"
16
17/ {
18 compatible = "ti,am68-sk", "ti,j721s2";
19 model = "Texas Instruments AM68 SK";
20
21 chosen {
22 stdout-path = "serial2:115200n8";
23 };
24
25 aliases {
26 serial0 = &wkup_uart0;
27 serial1 = &mcu_uart0;
28 serial2 = &main_uart8;
29 mmc1 = &main_sdhci1;
30 can0 = &mcu_mcan0;
31 can1 = &mcu_mcan1;
32 can2 = &main_mcan6;
33 can3 = &main_mcan7;
93743d24 34 ethernet0 = &cpsw_port1;
53633a89
TR		 35 };
36
37 vusb_main: regulator-vusb-main5v0 {
38 /* USB MAIN INPUT 5V DC */
39 compatible = "regulator-fixed";
40 regulator-name = "vusb-main5v0";
41 regulator-min-microvolt = <5000000>;
42 regulator-max-microvolt = <5000000>;
43 regulator-always-on;
44 regulator-boot-on;
45 };
46
47 vsys_3v3: regulator-vsys3v3 {
48 /* Output of LM5141 */
49 compatible = "regulator-fixed";
50 regulator-name = "vsys_3v3";
51 regulator-min-microvolt = <3300000>;
52 regulator-max-microvolt = <3300000>;
53 vin-supply = <&vusb_main>;
54 regulator-always-on;
55 regulator-boot-on;
56 };
57
58 vdd_mmc1: regulator-sd {
59 /* Output of TPS22918 */
60 compatible = "regulator-fixed";
61 regulator-name = "vdd_mmc1";
62 regulator-min-microvolt = <3300000>;
63 regulator-max-microvolt = <3300000>;
64 regulator-boot-on;
65 enable-active-high;
66 vin-supply = <&vsys_3v3>;
67 gpio = <&exp1 8 GPIO_ACTIVE_HIGH>;
68 };
69
70 vdd_sd_dv: regulator-tlv71033 {
71 /* Output of TLV71033 */
72 compatible = "regulator-gpio";
73 regulator-name = "tlv71033";
74 pinctrl-names = "default";
75 pinctrl-0 = <&vdd_sd_dv_pins_default>;
76 regulator-min-microvolt = <1800000>;
77 regulator-max-microvolt = <3300000>;
78 regulator-boot-on;
79 vin-supply = <&vsys_3v3>;
80 gpios = <&main_gpio0 49 GPIO_ACTIVE_HIGH>;
81 states = <1800000 0x0>,
82 <3300000 0x1>;
83 };
84
85 vsys_io_1v8: regulator-vsys-io-1v8 {
86 compatible = "regulator-fixed";
87 regulator-name = "vsys_io_1v8";
88 regulator-min-microvolt = <1800000>;
89 regulator-max-microvolt = <1800000>;
90 regulator-always-on;
91 regulator-boot-on;
92 };
93
94 vsys_io_1v2: regulator-vsys-io-1v2 {
95 compatible = "regulator-fixed";
96 regulator-name = "vsys_io_1v2";
97 regulator-min-microvolt = <1200000>;
98 regulator-max-microvolt = <1200000>;
99 regulator-always-on;
100 regulator-boot-on;
101 };
102
103 transceiver1: can-phy0 {
104 compatible = "ti,tcan1042";
105 #phy-cells = <0>;
106 max-bitrate = <5000000>;
107 };
108
109 transceiver2: can-phy1 {
110 compatible = "ti,tcan1042";
111 #phy-cells = <0>;
112 max-bitrate = <5000000>;
113 };
114
115 transceiver3: can-phy2 {
116 compatible = "ti,tcan1042";
117 #phy-cells = <0>;
118 max-bitrate = <5000000>;
119 };
120
121 transceiver4: can-phy3 {
122 compatible = "ti,tcan1042";
123 #phy-cells = <0>;
124 max-bitrate = <5000000>;
125 };
126
127 connector-hdmi {
128 compatible = "hdmi-connector";
129 label = "hdmi";
130 type = "a";
131 pinctrl-names = "default";
132 pinctrl-0 = <&hdmi_hpd_pins_default>;
133 ddc-i2c-bus = <&mcu_i2c1>;
134 /* HDMI_HPD */
135 hpd-gpios = <&main_gpio0 0 GPIO_ACTIVE_HIGH>;
136
137 port {
138 hdmi_connector_in: endpoint {
139 remote-endpoint = <&tfp410_out>;
140 };
141 };
142 };
143
144 bridge-dvi {
145 compatible = "ti,tfp410";
146 /* HDMI_PDn */
147 powerdown-gpios = <&exp2 0 GPIO_ACTIVE_LOW>;
148 ti,deskew = <0>;
149
150 ports {
151 #address-cells = <1>;
152 #size-cells = <0>;
153
154 port@0 {
155 reg = <0>;
156
157 tfp410_in: endpoint {
158 remote-endpoint = <&dpi_out0>;
159 pclk-sample = <1>;
160 };
161 };
162
163 port@1 {
164 reg = <1>;
165
166 tfp410_out: endpoint {
167 remote-endpoint = <&hdmi_connector_in>;
168 };
169 };
170 };
171 };
6bb92fcf
TR		 172
173 csi_mux: mux-controller {
174 compatible = "gpio-mux";
175 #mux-state-cells = <1>;
176 mux-gpios = <&exp3 1 GPIO_ACTIVE_HIGH>;
177 idle-state = <0>;
178 };
53633a89
TR		 179};
180
181&main_pmx0 {
182 main_uart8_pins_default: main-uart8-default-pins {
183 pinctrl-single,pins = <
184 J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */
185 J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */
186 >;
187 };
188
189 main_i2c0_pins_default: main-i2c0-default-pins {
190 pinctrl-single,pins = <
191 J721S2_IOPAD(0x0e0, PIN_INPUT, 0) /* (AH25) I2C0_SCL */
192 J721S2_IOPAD(0x0e4, PIN_INPUT, 0) /* (AE24) I2C0_SDA */
193 >;
194 };
195
6bb92fcf
TR		 196 main_i2c1_pins_default: main-i2c1-default-pins {
197 pinctrl-single,pins = <
198 J721S2_IOPAD(0x0ac, PIN_INPUT, 13) /* (AC25) MCASP0_AXR15.I2C1_SCL */
199 J721S2_IOPAD(0x0b0, PIN_INPUT, 13) /* (AD26) MCASP1_AXR3.I2C1_SDA */
200 >;
201 };
202
53633a89
TR		 203 main_mmc1_pins_default: main-mmc1-default-pins {
204 pinctrl-single,pins = <
205 J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */
206 J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */
207 J721S2_IOPAD(0x0fc, PIN_INPUT, 0) /* (M23) MMC1_DAT0 */
208 J721S2_IOPAD(0x0f8, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
209 J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */
210 J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */
211 J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */
212 >;
213 };
214
215 vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
216 pinctrl-single,pins = <
217 J721S2_IOPAD(0x0c4, PIN_INPUT, 7) /* (AB26) ECAP0_IN_APWM_OUT.GPIO0_49 */
218 >;
219 };
220
221 main_usbss0_pins_default: main-usbss0-default-pins {
222 pinctrl-single,pins = <
223 J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */
224 >;
225 };
226
227 main_mcan6_pins_default: main-mcan6-default-pins {
228 pinctrl-single,pins = <
229 J721S2_IOPAD(0x098, PIN_INPUT, 0) /* (V25) MCASP0_AXR10.MCAN6_RX */
230 J721S2_IOPAD(0x094, PIN_INPUT, 0) /* (AA25) MCASP0_AXR9.MCAN6_TX */
231 >;
232 };
233
234 main_mcan7_pins_default: main-mcan7-default-pins {
235 pinctrl-single,pins = <
236 J721S2_IOPAD(0x0a0, PIN_INPUT, 0) /* (AB25) MCASP0_AXR12.MCAN7_RX */
237 J721S2_IOPAD(0x09c, PIN_INPUT, 0) /* (T24) MCASP0_AXR11.MCAN7_TX */
238 >;
239 };
240
241 main_i2c4_pins_default: main-i2c4-default-pins {
242 pinctrl-single,pins = <
243 J721S2_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AF28) MCAN13_RX.I2C4_SDA */
244 J721S2_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AD25) MCAN14_TX.I2C4_SCL */
245 >;
246 };
247
248 rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins {
249 pinctrl-single,pins = <
250 J721S2_IOPAD(0x0a8, PIN_INPUT, 7) /* (U24) MCASP0_AXR14.GPIO0_42 */
251 J721S2_IOPAD(0x090, PIN_INPUT, 7) /* (W24) MCASP0_AXR8.GPIO0_36 */
252 J721S2_IOPAD(0x0bc, PIN_INPUT, 7) /* (V28) MCASP1_AFSX.GPIO0_47 */
253 J721S2_IOPAD(0x06c, PIN_INPUT, 7) /* (V26) MCAN1_TX.GPIO0_27 */
254 J721S2_IOPAD(0x004, PIN_INPUT, 7) /* (W25) MCAN12_TX.GPIO0_1 */
255 J721S2_IOPAD(0x008, PIN_INPUT, 7) /* (AC24) MCAN12_RX.GPIO0_2 */
256 J721S2_IOPAD(0x0b8, PIN_INPUT, 7) /* (AA24) MCASP1_ACLKX.GPIO0_46 */
257 J721S2_IOPAD(0x00c, PIN_INPUT, 7) /* (AE28) MCAN13_TX.GPIO0_3 */
258 J721S2_IOPAD(0x034, PIN_INPUT, 7) /* (AD24) PMIC_WAKE0.GPIO0_13 */
259 J721S2_IOPAD(0x0a4, PIN_INPUT, 7) /* (T23) MCASP0_AXR13.GPIO0_41 */
260 J721S2_IOPAD(0x0c0, PIN_INPUT, 7) /* (T28) MCASP1_AXR0.GPIO0_48 */
261 J721S2_IOPAD(0x0b4, PIN_INPUT, 7) /* (U25) MCASP1_AXR4.GPIO0_45 */
262 J721S2_IOPAD(0x0cc, PIN_INPUT, 7) /* (AE27) SPI0_CS0.GPIO0_51 */
263 J721S2_IOPAD(0x08c, PIN_INPUT, 7) /* (T25) MCASP0_AXR7.GPIO0_35 */
264 >;
265 };
266
267 dss_vout0_pins_default: dss-vout0-default-pins {
268 pinctrl-single,pins = <
269 J721S2_IOPAD(0x074, PIN_OUTPUT, 2) /* (R28) MCAN2_TX.VOUT0_DATA0 */
270 J721S2_IOPAD(0x070, PIN_OUTPUT, 2) /* (R27) MCAN1_RX.VOUT0_DATA1 */
271 J721S2_IOPAD(0x04c, PIN_OUTPUT, 2) /* (V27) MCASP1_AXR1.VOUT0_DATA10 */
272 J721S2_IOPAD(0x048, PIN_OUTPUT, 2) /* (AB27) MCASP0_AXR2.VOUT0_DATA11 */
273 J721S2_IOPAD(0x044, PIN_OUTPUT, 2) /* (Y26) MCASP0_AXR1.VOUT0_DATA12 */
274 J721S2_IOPAD(0x040, PIN_OUTPUT, 2) /* (AC28) MCASP0_AXR0.VOUT0_DATA13 */
275 J721S2_IOPAD(0x03c, PIN_OUTPUT, 2) /* (U27) MCASP0_AFSX.VOUT0_DATA14 */
276 J721S2_IOPAD(0x038, PIN_OUTPUT, 2) /* (AB28) MCASP0_ACLKX.VOUT0_DATA15 */
277 J721S2_IOPAD(0x0c8, PIN_OUTPUT, 2) /* (AD28) EXT_REFCLK1.VOUT0_DATA16 */
278 J721S2_IOPAD(0x030, PIN_OUTPUT, 2) /* (T26) GPIO0_12.VOUT0_DATA17 */
279 J721S2_IOPAD(0x02c, PIN_OUTPUT, 2) /* (V23) GPIO0_11.VOUT0_DATA18 */
280 J721S2_IOPAD(0x028, PIN_OUTPUT, 2) /* (AB24) MCAN16_RX.VOUT0_DATA19 */
281 J721S2_IOPAD(0x07c, PIN_OUTPUT, 2) /* (T27) MCASP0_AXR3.VOUT0_DATA2 */
282 J721S2_IOPAD(0x024, PIN_OUTPUT, 2) /* (Y28) MCAN16_TX.VOUT0_DATA20 */
283 J721S2_IOPAD(0x020, PIN_OUTPUT, 2) /* (AA23) MCAN15_RX.VOUT0_DATA21 */
284 J721S2_IOPAD(0x01c, PIN_OUTPUT, 2) /* (Y24) MCAN15_TX.VOUT0_DATA22 */
285 J721S2_IOPAD(0x018, PIN_OUTPUT, 2) /* (W23) MCAN14_RX.VOUT0_DATA23 */
286 J721S2_IOPAD(0x068, PIN_OUTPUT, 2) /* (U28) MCAN0_RX.VOUT0_DATA3 */
287 J721S2_IOPAD(0x064, PIN_OUTPUT, 2) /* (W28) MCAN0_TX.VOUT0_DATA4 */
288 J721S2_IOPAD(0x060, PIN_OUTPUT, 2) /* (AC27) MCASP2_AXR1.VOUT0_DATA5 */
289 J721S2_IOPAD(0x05c, PIN_OUTPUT, 2) /* (AA26) MCASP2_AXR0.VOUT0_DATA6 */
290 J721S2_IOPAD(0x058, PIN_OUTPUT, 2) /* (AA27) MCASP2_AFSX.VOUT0_DATA7 */
291 J721S2_IOPAD(0x054, PIN_OUTPUT, 2) /* (Y27) MCASP2_ACLKX.VOUT0_DATA8 */
292 J721S2_IOPAD(0x050, PIN_OUTPUT, 2) /* (W27) MCASP1_AXR2.VOUT0_DATA9 */
293 J721S2_IOPAD(0x084, PIN_OUTPUT, 2) /* (AA28) MCASP0_AXR5.VOUT0_DE */
294 J721S2_IOPAD(0x080, PIN_OUTPUT, 2) /* (U26) MCASP0_AXR4.VOUT0_HSYNC */
295 J721S2_IOPAD(0x078, PIN_OUTPUT, 2) /* (Y25) MCAN2_RX.VOUT0_PCLK */
296 J721S2_IOPAD(0x088, PIN_OUTPUT, 2) /* (AD27) MCASP0_AXR6.VOUT0_VP0_VSYNC */
297 >;
298 };
299
300 hdmi_hpd_pins_default: hdmi-hpd-default-pins {
301 pinctrl-single,pins = <
302 J721S2_IOPAD(0x000, PIN_INPUT, 7) /* (AG24) EXTINTN.GPIO0_0 */
303 >;
304 };
305};
306
307&wkup_pmx2 {
308 wkup_uart0_pins_default: wkup-uart0-default-pins {
309 pinctrl-single,pins = <
310 J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (E25) WKUP_GPIO0_6.WKUP_UART0_CTSn */
311 J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (F28) WKUP_GPIO0_7.WKUP_UART0_RTSn */
312 J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */
313 J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */
314 >;
315 };
316
317 mcu_cpsw_pins_default: mcu-cpsw-default-pins {
318 pinctrl-single,pins = <
319 J721S2_WKUP_IOPAD(0x02C, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */
320 J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */
321 J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */
322 J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */
323 J721S2_WKUP_IOPAD(0x01C, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */
324 J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */
325 J721S2_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */
326 J721S2_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */
327 J721S2_WKUP_IOPAD(0x00C, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */
328 J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */
329 J721S2_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */
330 J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */
331 >;
332 };
333
334 mcu_mdio_pins_default: mcu-mdio-default-pins {
335 pinctrl-single,pins = <
336 J721S2_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */
337 J721S2_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */
338 >;
339 };
340
341 mcu_mcan0_pins_default: mcu-mcan0-default-pins {
342 pinctrl-single,pins = <
343 J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */
344 J721S2_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */
345 >;
346 };
347
348 mcu_mcan1_pins_default: mcu-mcan1-default-pins {
349 pinctrl-single,pins = <
350 J721S2_WKUP_IOPAD(0x06C, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */
351 J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (C23) WKUP_GPIO0_4.MCU_MCAN1_TX*/
352 >;
353 };
354
355 mcu_i2c0_pins_default: mcu-i2c0-default-pins {
356 pinctrl-single,pins = <
357 J721S2_WKUP_IOPAD(0x0a0, PIN_INPUT, 0) /* (G24) MCU_I2C0_SCL */
358 J721S2_WKUP_IOPAD(0x0a4, PIN_INPUT, 0) /* (J25) MCU_I2C0_SDA */
359 >;
360 };
361
362 mcu_i2c1_pins_default: mcu-i2c1-default-pins {
363 pinctrl-single,pins = <
364 J721S2_WKUP_IOPAD(0x078, PIN_INPUT, 0) /* (F24) WKUP_GPIO0_8.MCU_I2C1_SCL */
365 J721S2_WKUP_IOPAD(0x07c, PIN_INPUT, 0) /* (H26) WKUP_GPIO0_9.MCU_I2C1_SDA */
366 >;
367 };
368
369 mcu_uart0_pins_default: mcu-uart0-default-pins {
370 pinctrl-single,pins = <
371 J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */
372 J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */
373 >;
374 };
375
376 mcu_rpi_header_gpio0_pins0_default: mcu-rpi-header-gpio0-default-pins-0 {
377 pinctrl-single,pins = <
378 J721S2_WKUP_IOPAD(0x118, PIN_INPUT, 7) /* (G25) WKUP_GPIO0_66 */
379 J721S2_WKUP_IOPAD(0x05C, PIN_INPUT, 7) /* (E24) MCU_SPI1_D0.WKUP_GPIO0_1 */
380 J721S2_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (C28) MCU_SPI1_D1.WKUP_GPIO0_2 */
381 J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 7) /* (D26) MCU_SPI1_CLK.WKUP_GPIO0_0 */
382 J721S2_WKUP_IOPAD(0x094, PIN_INPUT, 7) /* (D25) MCU_SPI1_CS2.WKUP_GPIO0_15*/
383 J721S2_WKUP_IOPAD(0x0B8, PIN_INPUT, 7) /* (G27) WKUP_GPIO0_56 */
384 J721S2_WKUP_IOPAD(0x114, PIN_INPUT, 7) /* (J26) WKUP_GPIO0_57 */
385 J721S2_WKUP_IOPAD(0x11C, PIN_INPUT, 7) /* (J27) WKUP_GPIO0_67 */
386 J721S2_WKUP_IOPAD(0x064, PIN_INPUT, 7) /* (C27) MCU_SPI1_CS0.WKUP_GPIO0_3 */
387 >;
388 };
389};
390
391&wkup_pmx3 {
392 mcu_rpi_header_gpio0_pins1_default: mcu-rpi-header-gpio0-default-pins-1 {
393 pinctrl-single,pins = <
394 J721S2_WKUP_IOPAD(0x000, PIN_INPUT, 7) /* (K26) WKUP_GPIO0_49 */
395 >;
396 };
397};
398
399&main_gpio0 {
400 status = "okay";
401 pinctrl-names = "default";
402 pinctrl-0 = <&rpi_header_gpio0_pins_default>;
403};
404
405&wkup_gpio0 {
406 status = "okay";
407 pinctrl-names = "default";
408 pinctrl-0 = <&mcu_rpi_header_gpio0_pins0_default>, <&mcu_rpi_header_gpio0_pins1_default>;
409};
410
411&wkup_uart0 {
412 status = "reserved";
413 pinctrl-names = "default";
414 pinctrl-0 = <&wkup_uart0_pins_default>;
415};
416
417&mcu_uart0 {
418 status = "okay";
419 pinctrl-names = "default";
420 pinctrl-0 = <&mcu_uart0_pins_default>;
421};
422
423&main_uart8 {
424 status = "okay";
425 pinctrl-names = "default";
426 pinctrl-0 = <&main_uart8_pins_default>;
427 /* Shared with TFA on this platform */
428 power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>;
429};
430
431&main_i2c0 {
432 pinctrl-names = "default";
433 pinctrl-0 = <&main_i2c0_pins_default>;
434 clock-frequency = <400000>;
435
436 exp1: gpio@21 {
437 compatible = "ti,tca6416";
438 reg = <0x21>;
439 gpio-controller;
440 #gpio-cells = <2>;
441 gpio-line-names = " ", " ", " ", " ", " ",
442 "BOARDID_EEPROM_WP", "CAN_STB", " ",
443 "GPIO_uSD_PWR_EN", " ", "IO_EXP_PCIe1_M.2_RTSz",
444 "IO_EXP_MCU_RGMII_RST#", " ", " ", " ", " ";
445 };
446};
447
6bb92fcf
TR		 448&main_i2c1 {
449 pinctrl-names = "default";
450 pinctrl-0 = <&main_i2c1_pins_default>;
451 status = "okay";
452
453 exp3: gpio@20 {
454 compatible = "ti,tca6408";
455 reg = <0x20>;
456 gpio-controller;
457 #gpio-cells = <2>;
458 gpio-line-names = "CSI_VIO_SEL", "CSI_SEL_FPC_EXPn",
459 "IO_EXP_CSI2_EXP_RSTz","CSI0_B_GPIO1",
460 "CSI1_B_GPIO1";
461 };
462
463 i2c-mux@70 {
464 compatible = "nxp,pca9543";
465 #address-cells = <1>;
466 #size-cells = <0>;
467 reg = <0x70>;
468
469 cam0_i2c: i2c@0 {
470 #address-cells = <1>;
471 #size-cells = <0>;
472 reg = <0>;
473 };
474
475 cam1_i2c: i2c@1 {
476 #address-cells = <1>;
477 #size-cells = <0>;
478 reg = <1>;
479 };
480
481 };
482};
483
53633a89
TR		 484&main_i2c4 {
485 status = "okay";
486 pinctrl-names = "default";
487 pinctrl-0 = <&main_i2c4_pins_default>;
488 clock-frequency = <400000>;
489};
490
491&mcu_i2c0 {
492 status = "okay";
493 pinctrl-names = "default";
494 pinctrl-0 = <&mcu_i2c0_pins_default>;
495 clock-frequency = <400000>;
496};
497
498&mcu_i2c1 {
499 status = "okay";
500 pinctrl-names = "default";
501 pinctrl-0 = <&mcu_i2c1_pins_default>;
502 /* i2c1 is used for DVI DDC, so we need to use 100kHz */
503 clock-frequency = <100000>;
504
505 exp2: gpio@20 {
506 compatible = "ti,tca6408";
507 reg = <0x20>;
508 gpio-controller;
509 #gpio-cells = <2>;
510 gpio-line-names = "HDMI_PDn","HDMI_LS_OE",
511 "DP0_3V3_EN","eDP_ENABLE";
512 };
513};
514
515&main_sdhci1 {
516 /* SD card */
517 status = "okay";
518 pinctrl-0 = <&main_mmc1_pins_default>;
519 pinctrl-names = "default";
520 disable-wp;
521 vmmc-supply = <&vdd_mmc1>;
522 vqmmc-supply = <&vdd_sd_dv>;
523};
524
525&mcu_cpsw {
526 pinctrl-names = "default";
527 pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
528};
529
530&davinci_mdio {
531 phy0: ethernet-phy@0 {
532 reg = <0>;
533 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
534 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
535 ti,min-output-impedance;
536 };
537};
538
539&cpsw_port1 {
540 phy-mode = "rgmii-rxid";
541 phy-handle = <&phy0>;
542};
543
544&mcu_mcan0 {
545 status = "okay";
546 pinctrl-names = "default";
547 pinctrl-0 = <&mcu_mcan0_pins_default>;
548 phys = <&transceiver1>;
549};
550
551&mcu_mcan1 {
552 status = "okay";
553 pinctrl-names = "default";
554 pinctrl-0 = <&mcu_mcan1_pins_default>;
555 phys = <&transceiver2>;
556};
557
558&main_mcan6 {
559 status = "okay";
560 pinctrl-names = "default";
561 pinctrl-0 = <&main_mcan6_pins_default>;
562 phys = <&transceiver3>;
563};
564
565&main_mcan7 {
566 status = "okay";
567 pinctrl-names = "default";
568 pinctrl-0 = <&main_mcan7_pins_default>;
569 phys = <&transceiver4>;
570};
571
572&dss {
573 status = "okay";
574 pinctrl-names = "default";
575 pinctrl-0 = <&dss_vout0_pins_default>;
576 /*
577 * These clock assignments are chosen to enable the following outputs:
578 *
579 * VP0 - DisplayPort SST
580 * VP1 - DPI0
581 * VP2 - DSI
582 * VP3 - DPI1
583 */
584 assigned-clocks = <&k3_clks 158 2>,
585 <&k3_clks 158 5>,
586 <&k3_clks 158 14>,
587 <&k3_clks 158 18>;
588 assigned-clock-parents = <&k3_clks 158 3>,
589 <&k3_clks 158 7>,
590 <&k3_clks 158 16>,
591 <&k3_clks 158 22>;
592};
593
594&dss_ports {
595 #address-cells = <1>;
596 #size-cells = <0>;
597
598 /* HDMI */
599 port@1 {
600 reg = <1>;
601
602 dpi_out0: endpoint {
603 remote-endpoint = <&tfp410_in>;
604 };
605 };
606};
607
608&serdes_ln_ctrl {
609 idle-states = <J721S2_SERDES0_LANE0_PCIE1_LANE0>, <J721S2_SERDES0_LANE1_PCIE1_LANE1>,
610 <J721S2_SERDES0_LANE2_USB_SWAP>, <J721S2_SERDES0_LANE3_USB>;
611};
612
613&serdes_refclk {
614 clock-frequency = <100000000>;
615};
616
617&serdes0 {
618 status = "okay";
619
620 serdes0_pcie_link: phy@0 {
621 reg = <0>;
622 cdns,num-lanes = <2>;
623 #phy-cells = <0>;
624 cdns,phy-type = <PHY_TYPE_PCIE>;
625 resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
626 };
627
628 serdes0_usb_link: phy@2 {
629 status = "okay";
630 reg = <2>;
631 cdns,num-lanes = <1>;
632 #phy-cells = <0>;
633 cdns,phy-type = <PHY_TYPE_USB3>;
634 resets = <&serdes_wiz0 3>;
635 };
636};
637
638&pcie1_rc {
639 status = "okay";
640 reset-gpios = <&exp1 10 GPIO_ACTIVE_HIGH>;
641 phys = <&serdes0_pcie_link>;
642 phy-names = "pcie-phy";
643 num-lanes = <2>;
644};
645
646&usb_serdes_mux {
647 idle-states = <0>; /* USB0 to SERDES lane 2 */
648};
649
650&usbss0 {
651 status = "okay";
652 pinctrl-0 = <&main_usbss0_pins_default>;
653 pinctrl-names = "default";
654 ti,vbus-divider;
655};
656
657&usb0 {
658 dr_mode = "host";
659 maximum-speed = "super-speed";
660 phys = <&serdes0_usb_link>;
661 phy-names = "cdns3,usb3-phy";
662};
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