[u-boot.git] / board / freescale / mpc8572ds / mpc8572ds.c

/*
 * Copyright 2007-2008 Freescale Semiconductor, Inc.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <command.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/io.h>
#include <miiphy.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <tsec.h>

#include "../common/pixis.h"
#include "../common/sgmii_riser.h"

long int fixed_sdram(void);

int checkboard (void)
{
	u8 vboot;
	u8 *pixis_base = (u8 *)PIXIS_BASE;

	puts ("Board: MPC8572DS ");
#ifdef CONFIG_PHYS_64BIT
	puts ("(36-bit addrmap) ");
#endif
	printf ("Sys ID: 0x%02x, "
		"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
		in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
		in_8(pixis_base + PIXIS_PVER));

	vboot = in_8(pixis_base + PIXIS_VBOOT);
	switch ((vboot & PIXIS_VBOOT_LBMAP) >> 6) {
		case PIXIS_VBOOT_LBMAP_NOR0:
			puts ("vBank: 0\n");
			break;
		case PIXIS_VBOOT_LBMAP_PJET:
			puts ("Promjet\n");
			break;
		case PIXIS_VBOOT_LBMAP_NAND:
			puts ("NAND\n");
			break;
		case PIXIS_VBOOT_LBMAP_NOR1:
			puts ("vBank: 1\n");
			break;
	}

	return 0;
}

phys_size_t initdram(int board_type)
{
	phys_size_t dram_size = 0;

	puts("Initializing....");

#ifdef CONFIG_SPD_EEPROM
	dram_size = fsl_ddr_sdram();
#else
	dram_size = fixed_sdram();
#endif
	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
	dram_size *= 0x100000;

	puts("    DDR: ");
	return dram_size;
}

#if !defined(CONFIG_SPD_EEPROM)
/*
 * Fixed sdram init -- doesn't use serial presence detect.
 */

phys_size_t fixed_sdram (void)
{
	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
	volatile ccsr_ddr_t *ddr= &immap->im_ddr;
	uint d_init;

	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;

	ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
	ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
	ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
	ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
	ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
	ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;

#if defined (CONFIG_DDR_ECC)
	ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
	ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
	ddr->err_sbe = CONFIG_SYS_DDR_SBE;
#endif
	asm("sync;isync");

	udelay(500);

	ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;

#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	d_init = 1;
	debug("DDR - 1st controller: memory initializing\n");
	/*
	 * Poll until memory is initialized.
	 * 512 Meg at 400 might hit this 200 times or so.
	 */
	while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
		udelay(1000);
	}
	debug("DDR: memory initialized\n\n");
	asm("sync; isync");
	udelay(500);
#endif

	return 512 * 1024 * 1024;
}

#endif

#ifdef CONFIG_PCIE1
static struct pci_controller pcie1_hose;
#endif

#ifdef CONFIG_PCIE2
static struct pci_controller pcie2_hose;
#endif

#ifdef CONFIG_PCIE3
static struct pci_controller pcie3_hose;
#endif

int first_free_busno=0;
#ifdef CONFIG_PCI
void pci_init_board(void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	uint devdisr = gur->devdisr;
	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;

	debug ("   pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
			devdisr, io_sel, host_agent);

	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
		printf ("    eTSEC1 is in sgmii mode.\n");
	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
		printf ("    eTSEC2 is in sgmii mode.\n");
	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
		printf ("    eTSEC3 is in sgmii mode.\n");
	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
		printf ("    eTSEC4 is in sgmii mode.\n");


#ifdef CONFIG_PCIE3
	{
		volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
		struct pci_controller *hose = &pcie3_hose;
		int pcie_ep = (host_agent == 0) || (host_agent == 3) ||
			(host_agent == 5) || (host_agent == 6);
		int pcie_configured  = (io_sel == 0x7);
		struct pci_region *r = hose->regions;
		u32 temp32;

		if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
			printf ("\n    PCIE3 connected to ULI as %s (base address %x)",
					pcie_ep ? "End Point" : "Root Complex",
					(uint)pci);
			if (pci->pme_msg_det) {
				pci->pme_msg_det = 0xffffffff;
				debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
			}
			printf ("\n");

			/* inbound */
			r += fsl_pci_setup_inbound_windows(r);

			/* outbound memory */
			pci_set_region(r++,
					CONFIG_SYS_PCIE3_MEM_BUS,
					CONFIG_SYS_PCIE3_MEM_PHYS,
					CONFIG_SYS_PCIE3_MEM_SIZE,
					PCI_REGION_MEM);

			/* outbound io */
			pci_set_region(r++,
					CONFIG_SYS_PCIE3_IO_BUS,
					CONFIG_SYS_PCIE3_IO_PHYS,
					CONFIG_SYS_PCIE3_IO_SIZE,
					PCI_REGION_IO);

			hose->region_count = r - hose->regions;
			hose->first_busno=first_free_busno;
			pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);

			fsl_pci_init(hose);

			first_free_busno=hose->last_busno+1;
			printf ("    PCIE3 on bus %02x - %02x\n",
					hose->first_busno,hose->last_busno);

			/*
			 * Activate ULI1575 legacy chip by performing a fake
			 * memory access.  Needed to make ULI RTC work.
			 * Device 1d has the first on-board memory BAR.
			 */

			pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0 ),
					PCI_BASE_ADDRESS_1, &temp32);
			if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
				void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0),
								temp32, 4, 0);
				debug(" uli1572 read to %p\n", p);
				in_be32(p);
			}
		} else {
			printf ("    PCIE3: disabled\n");
		}

	}
#else
	gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
#endif

#ifdef CONFIG_PCIE2
	{
		volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
		struct pci_controller *hose = &pcie2_hose;
		int pcie_ep = (host_agent == 2) || (host_agent == 4) ||
			(host_agent == 6) || (host_agent == 0);
		int pcie_configured  = (io_sel == 0x3) || (io_sel == 0x7);
		struct pci_region *r = hose->regions;

		if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
			printf ("\n    PCIE2 connected to Slot 1 as %s (base address %x)",
					pcie_ep ? "End Point" : "Root Complex",
					(uint)pci);
			if (pci->pme_msg_det) {
				pci->pme_msg_det = 0xffffffff;
				debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
			}
			printf ("\n");

			/* inbound */
			r += fsl_pci_setup_inbound_windows(r);

			/* outbound memory */
			pci_set_region(r++,
					CONFIG_SYS_PCIE2_MEM_BUS,
					CONFIG_SYS_PCIE2_MEM_PHYS,
					CONFIG_SYS_PCIE2_MEM_SIZE,
					PCI_REGION_MEM);

			/* outbound io */
			pci_set_region(r++,
					CONFIG_SYS_PCIE2_IO_BUS,
					CONFIG_SYS_PCIE2_IO_PHYS,
					CONFIG_SYS_PCIE2_IO_SIZE,
					PCI_REGION_IO);

			hose->region_count = r - hose->regions;
			hose->first_busno=first_free_busno;
			pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);

			fsl_pci_init(hose);
			first_free_busno=hose->last_busno+1;
			printf ("    PCIE2 on bus %02x - %02x\n",
					hose->first_busno,hose->last_busno);

		} else {
			printf ("    PCIE2: disabled\n");
		}

	}
#else
	gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
#endif
#ifdef CONFIG_PCIE1
	{
		volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
		struct pci_controller *hose = &pcie1_hose;
		int pcie_ep = (host_agent <= 1) || (host_agent == 4) ||
			(host_agent == 5);
		int pcie_configured  = (io_sel == 0x2) || (io_sel == 0x3) ||
					(io_sel == 0x7) || (io_sel == 0xb) ||
					(io_sel == 0xc) || (io_sel == 0xf);
		struct pci_region *r = hose->regions;

		if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
			printf ("\n    PCIE1 connected to Slot 2 as %s (base address %x)",
					pcie_ep ? "End Point" : "Root Complex",
					(uint)pci);
			if (pci->pme_msg_det) {
				pci->pme_msg_det = 0xffffffff;
				debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
			}
			printf ("\n");

			/* inbound */
			r += fsl_pci_setup_inbound_windows(r);

			/* outbound memory */
			pci_set_region(r++,
					CONFIG_SYS_PCIE1_MEM_BUS,
					CONFIG_SYS_PCIE1_MEM_PHYS,
					CONFIG_SYS_PCIE1_MEM_SIZE,
					PCI_REGION_MEM);

			/* outbound io */
			pci_set_region(r++,
					CONFIG_SYS_PCIE1_IO_BUS,
					CONFIG_SYS_PCIE1_IO_PHYS,
					CONFIG_SYS_PCIE1_IO_SIZE,
					PCI_REGION_IO);

			hose->region_count = r - hose->regions;
			hose->first_busno=first_free_busno;

			pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);

			fsl_pci_init(hose);

			first_free_busno=hose->last_busno+1;
			printf("    PCIE1 on bus %02x - %02x\n",
					hose->first_busno,hose->last_busno);

		} else {
			printf ("    PCIE1: disabled\n");
		}

	}
#else
	gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
#endif
}
#endif

int board_early_init_r(void)
{
	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
	const u8 flash_esel = 2;

	/*
	 * Remap Boot flash + PROMJET region to caching-inhibited
	 * so that flash can be erased properly.
	 */

	/* Flush d-cache and invalidate i-cache of any FLASH data */
	flush_dcache();
	invalidate_icache();

	/* invalidate existing TLB entry for flash + promjet */
	disable_tlb(flash_esel);

	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,	/* tlb, epn, rpn */
			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,	/* perms, wimge */
			0, flash_esel, BOOKE_PAGESZ_256M, 1);	/* ts, esel, tsize, iprot */

	return 0;
}

#ifdef CONFIG_GET_CLK_FROM_ICS307
/* decode S[0-2] to Output Divider (OD) */
static unsigned char ics307_S_to_OD[] = {
	10, 2, 8, 4, 5, 7, 3, 6
};

/* Calculate frequency being generated by ICS307-02 clock chip based upon
 * the control bytes being programmed into it. */
/* XXX: This function should probably go into a common library */
static unsigned long
ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2)
{
	const unsigned long InputFrequency = CONFIG_ICS307_REFCLK_HZ;
	unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
	unsigned long RDW = cw2 & 0x7F;
	unsigned long OD = ics307_S_to_OD[cw0 & 0x7];
	unsigned long freq;

	/* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */

	/* cw0:  C1 C0 TTL F1 F0 S2 S1 S0
	 * cw1:  V8 V7 V6 V5 V4 V3 V2 V1
	 * cw2:  V0 R6 R5 R4 R3 R2 R1 R0
	 *
	 * R6:R0 = Reference Divider Word (RDW)
	 * V8:V0 = VCO Divider Word (VDW)
	 * S2:S0 = Output Divider Select (OD)
	 * F1:F0 = Function of CLK2 Output
	 * TTL = duty cycle
	 * C1:C0 = internal load capacitance for cyrstal
	 */

	/* Adding 1 to get a "nicely" rounded number, but this needs
	 * more tweaking to get a "properly" rounded number. */

	freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD));

	debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2,
			freq);
	return freq;
}

unsigned long get_board_sys_clk(ulong dummy)
{
	return ics307_clk_freq (
			in8(PIXIS_BASE + PIXIS_VSYSCLK0),
			in8(PIXIS_BASE + PIXIS_VSYSCLK1),
			in8(PIXIS_BASE + PIXIS_VSYSCLK2)
			);
}

unsigned long get_board_ddr_clk(ulong dummy)
{
	return ics307_clk_freq (
			in8(PIXIS_BASE + PIXIS_VDDRCLK0),
			in8(PIXIS_BASE + PIXIS_VDDRCLK1),
			in8(PIXIS_BASE + PIXIS_VDDRCLK2)
			);
}
#else
unsigned long get_board_sys_clk(ulong dummy)
{
	u8 i;
	ulong val = 0;

	i = in8(PIXIS_BASE + PIXIS_SPD);
	i &= 0x07;

	switch (i) {
		case 0:
			val = 33333333;
			break;
		case 1:
			val = 40000000;
			break;
		case 2:
			val = 50000000;
			break;
		case 3:
			val = 66666666;
			break;
		case 4:
			val = 83333333;
			break;
		case 5:
			val = 100000000;
			break;
		case 6:
			val = 133333333;
			break;
		case 7:
			val = 166666666;
			break;
	}

	return val;
}

unsigned long get_board_ddr_clk(ulong dummy)
{
	u8 i;
	ulong val = 0;

	i = in8(PIXIS_BASE + PIXIS_SPD);
	i &= 0x38;
	i >>= 3;

	switch (i) {
		case 0:
			val = 33333333;
			break;
		case 1:
			val = 40000000;
			break;
		case 2:
			val = 50000000;
			break;
		case 3:
			val = 66666666;
			break;
		case 4:
			val = 83333333;
			break;
		case 5:
			val = 100000000;
			break;
		case 6:
			val = 133333333;
			break;
		case 7:
			val = 166666666;
			break;
	}
	return val;
}
#endif

#ifdef CONFIG_TSEC_ENET
int board_eth_init(bd_t *bis)
{
	struct tsec_info_struct tsec_info[4];
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	int num = 0;

#ifdef CONFIG_TSEC1
	SET_STD_TSEC_INFO(tsec_info[num], 1);
	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
		tsec_info[num].flags |= TSEC_SGMII;
	num++;
#endif
#ifdef CONFIG_TSEC2
	SET_STD_TSEC_INFO(tsec_info[num], 2);
	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
		tsec_info[num].flags |= TSEC_SGMII;
	num++;
#endif
#ifdef CONFIG_TSEC3
	SET_STD_TSEC_INFO(tsec_info[num], 3);
	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
		tsec_info[num].flags |= TSEC_SGMII;
	num++;
#endif
#ifdef CONFIG_TSEC4
	SET_STD_TSEC_INFO(tsec_info[num], 4);
	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
		tsec_info[num].flags |= TSEC_SGMII;
	num++;
#endif

	if (!num) {
		printf("No TSECs initialized\n");

		return 0;
	}

#ifdef CONFIG_FSL_SGMII_RISER
	fsl_sgmii_riser_init(tsec_info, num);
#endif

	tsec_eth_init(bis, tsec_info, num);

	return 0;
}
#endif

#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
	phys_addr_t base;
	phys_size_t size;

	ft_cpu_setup(blob, bd);

	base = getenv_bootm_low();
	size = getenv_bootm_size();

	fdt_fixup_memory(blob, (u64)base, (u64)size);

#ifdef CONFIG_PCIE3
	ft_fsl_pci_setup(blob, "pci0", &pcie3_hose);
#endif
#ifdef CONFIG_PCIE2
	ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
#endif
#ifdef CONFIG_PCIE1
	ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
#endif
#ifdef CONFIG_FSL_SGMII_RISER
	fsl_sgmii_riser_fdt_fixup(blob);
#endif
}
#endif

#ifdef CONFIG_MP
extern void cpu_mp_lmb_reserve(struct lmb *lmb);

void board_lmb_reserve(struct lmb *lmb)
{
	cpu_mp_lmb_reserve(lmb);
}
#endif
Commit	Line	Data
129ba616 KG	1	/*
	2	* Copyright 2007-2008 Freescale Semiconductor, Inc.
	3	*
	4	* See file CREDITS for list of people who contributed to this
	5	* project.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
	21	*/
	22
	23	#include <common.h>
	24	#include <command.h>
	25	#include <pci.h>
	26	#include <asm/processor.h>
	27	#include <asm/mmu.h>
7c0d4a75	28	#include <asm/cache.h>
129ba616	29	#include <asm/immap_85xx.h>
c8514622	30	#include <asm/fsl_pci.h>
129ba616 KG	31	#include <asm/fsl_ddr_sdram.h>
	32	#include <asm/io.h>
	33	#include <miiphy.h>
	34	#include <libfdt.h>
	35	#include <fdt_support.h>
7e183cad	36	#include <tsec.h>
129ba616 KG	37
129ba616 KG	38	#include "../common/pixis.h"
7e183cad	39	#include "../common/sgmii_riser.h"
129ba616	40
129ba616 KG	41	long int fixed_sdram(void);
	42
	43	int checkboard (void)
	44	{
6bb5b412 KG	45	u8 vboot;
	46	u8 pixis_base = (u8 )PIXIS_BASE;
	47
cb69e4de KG	48	puts ("Board: MPC8572DS ");
	49	#ifdef CONFIG_PHYS_64BIT
	50	puts ("(36-bit addrmap) ");
	51	#endif
	52	printf ("Sys ID: 0x%02x, "
6bb5b412 KG	53	"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
	54	in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
	55	in_8(pixis_base + PIXIS_PVER));
	56
	57	vboot = in_8(pixis_base + PIXIS_VBOOT);
	58	switch ((vboot & PIXIS_VBOOT_LBMAP) >> 6) {
	59	case PIXIS_VBOOT_LBMAP_NOR0:
	60	puts ("vBank: 0\n");
	61	break;
	62	case PIXIS_VBOOT_LBMAP_PJET:
	63	puts ("Promjet\n");
	64	break;
	65	case PIXIS_VBOOT_LBMAP_NAND:
	66	puts ("NAND\n");
	67	break;
	68	case PIXIS_VBOOT_LBMAP_NOR1:
	69	puts ("vBank: 1\n");
	70	break;
	71	}
	72
129ba616 KG	73	return 0;
	74	}
	75
	76	phys_size_t initdram(int board_type)
	77	{
	78	phys_size_t dram_size = 0;
	79
	80	puts("Initializing....");
	81
	82	#ifdef CONFIG_SPD_EEPROM
	83	dram_size = fsl_ddr_sdram();
129ba616 KG	84	#else
	85	dram_size = fixed_sdram();
	86	#endif
e57f0fa1 DL	87	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
e57f0fa1 DL	88	dram_size *= 0x100000;
129ba616	89
129ba616 KG	90	puts(" DDR: ");
	91	return dram_size;
	92	}
	93
	94	#if !defined(CONFIG_SPD_EEPROM)
	95	/*
	96	* Fixed sdram init -- doesn't use serial presence detect.
	97	*/
	98
	99	phys_size_t fixed_sdram (void)
	100	{
6d0f6bcf	101	volatile immap_t immap = (immap_t )CONFIG_SYS_IMMR;
129ba616 KG	102	volatile ccsr_ddr_t *ddr= &immap->im_ddr;
	103	uint d_init;
	104
6d0f6bcf JCPV	105	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
6d0f6bcf JCPV	106	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
129ba616	107
6d0f6bcf JCPV	108	ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
	109	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
	110	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	111	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
	112	ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
	113	ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
	114	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
	115	ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
	116	ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
	117	ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
129ba616 KG	118
129ba616 KG	119	#if defined (CONFIG_DDR_ECC)
6d0f6bcf JCPV	120	ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
	121	ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
	122	ddr->err_sbe = CONFIG_SYS_DDR_SBE;
129ba616 KG	123	#endif
	124	asm("sync;isync");
	125
	126	udelay(500);
	127
6d0f6bcf	128	ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
129ba616 KG	129
	130	#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	131	d_init = 1;
	132	debug("DDR - 1st controller: memory initializing\n");
	133	/*
	134	* Poll until memory is initialized.
	135	* 512 Meg at 400 might hit this 200 times or so.
	136	*/
	137	while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
	138	udelay(1000);
	139	}
	140	debug("DDR: memory initialized\n\n");
	141	asm("sync; isync");
	142	udelay(500);
	143	#endif
	144
	145	return 512 * 1024 * 1024;
	146	}
	147
	148	#endif
	149
	150	#ifdef CONFIG_PCIE1
	151	static struct pci_controller pcie1_hose;
	152	#endif
	153
	154	#ifdef CONFIG_PCIE2
	155	static struct pci_controller pcie2_hose;
	156	#endif
	157
	158	#ifdef CONFIG_PCIE3
	159	static struct pci_controller pcie3_hose;
	160	#endif
	161
	162	int first_free_busno=0;
	163	#ifdef CONFIG_PCI
	164	void pci_init_board(void)
	165	{
6d0f6bcf	166	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
129ba616 KG	167	uint devdisr = gur->devdisr;
	168	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
	169	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
	170
	171	debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
	172	devdisr, io_sel, host_agent);
	173
	174	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
	175	printf (" eTSEC1 is in sgmii mode.\n");
	176	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
	177	printf (" eTSEC2 is in sgmii mode.\n");
	178	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
	179	printf (" eTSEC3 is in sgmii mode.\n");
	180	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
	181	printf (" eTSEC4 is in sgmii mode.\n");
	182
	183
	184	#ifdef CONFIG_PCIE3
	185	{
6d0f6bcf	186	volatile ccsr_fsl_pci_t pci = (ccsr_fsl_pci_t ) CONFIG_SYS_PCIE3_ADDR;
129ba616 KG	187	struct pci_controller *hose = &pcie3_hose;
	188	int pcie_ep = (host_agent == 0) \|\| (host_agent == 3) \|\|
	189	(host_agent == 5) \|\| (host_agent == 6);
9afc2ef0	190	int pcie_configured = (io_sel == 0x7);
2dba0dea	191	struct pci_region *r = hose->regions;
129ba616 KG	192	u32 temp32;
129ba616 KG	193
028e1168	194	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
129ba616 KG	195	printf ("\n PCIE3 connected to ULI as %s (base address %x)",
	196	pcie_ep ? "End Point" : "Root Complex",
	197	(uint)pci);
	198	if (pci->pme_msg_det) {
	199	pci->pme_msg_det = 0xffffffff;
	200	debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
	201	}
	202	printf ("\n");
	203
	204	/* inbound */
2dba0dea	205	r += fsl_pci_setup_inbound_windows(r);
129ba616 KG	206
129ba616 KG	207	/* outbound memory */
2dba0dea	208	pci_set_region(r++,
10795f42	209	CONFIG_SYS_PCIE3_MEM_BUS,
6d0f6bcf JCPV	210	CONFIG_SYS_PCIE3_MEM_PHYS,
6d0f6bcf JCPV	211	CONFIG_SYS_PCIE3_MEM_SIZE,
129ba616 KG	212	PCI_REGION_MEM);
	213
	214	/* outbound io */
2dba0dea	215	pci_set_region(r++,
5f91ef6a	216	CONFIG_SYS_PCIE3_IO_BUS,
6d0f6bcf JCPV	217	CONFIG_SYS_PCIE3_IO_PHYS,
6d0f6bcf JCPV	218	CONFIG_SYS_PCIE3_IO_SIZE,
129ba616 KG	219	PCI_REGION_IO);
129ba616 KG	220
2dba0dea	221	hose->region_count = r - hose->regions;
129ba616 KG	222	hose->first_busno=first_free_busno;
	223	pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
	224
	225	fsl_pci_init(hose);
	226
	227	first_free_busno=hose->last_busno+1;
	228	printf (" PCIE3 on bus %02x - %02x\n",
	229	hose->first_busno,hose->last_busno);
	230
	231	/*
	232	* Activate ULI1575 legacy chip by performing a fake
	233	* memory access. Needed to make ULI RTC work.
	234	* Device 1d has the first on-board memory BAR.
	235	*/
	236
	237	pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0 ),
	238	PCI_BASE_ADDRESS_1, &temp32);
5af0fdd8	239	if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
ad97dce1 KG	240	void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0),
	241	temp32, 4, 0);
	242	debug(" uli1572 read to %p\n", p);
	243	in_be32(p);
129ba616 KG	244	}
	245	} else {
	246	printf (" PCIE3: disabled\n");
	247	}
	248
	249	}
	250	#else
	251	gur->devdisr \|= MPC85xx_DEVDISR_PCIE3; /* disable */
	252	#endif
	253
	254	#ifdef CONFIG_PCIE2
	255	{
6d0f6bcf	256	volatile ccsr_fsl_pci_t pci = (ccsr_fsl_pci_t ) CONFIG_SYS_PCIE2_ADDR;
129ba616 KG	257	struct pci_controller *hose = &pcie2_hose;
129ba616 KG	258	int pcie_ep = (host_agent == 2) \|\| (host_agent == 4) \|\|
86be510f	259	(host_agent == 6) \|\| (host_agent == 0);
9afc2ef0	260	int pcie_configured = (io_sel == 0x3) \|\| (io_sel == 0x7);
2dba0dea	261	struct pci_region *r = hose->regions;
129ba616	262
028e1168	263	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
129ba616 KG	264	printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)",
	265	pcie_ep ? "End Point" : "Root Complex",
	266	(uint)pci);
	267	if (pci->pme_msg_det) {
	268	pci->pme_msg_det = 0xffffffff;
	269	debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
	270	}
	271	printf ("\n");
	272
	273	/* inbound */
2dba0dea	274	r += fsl_pci_setup_inbound_windows(r);
129ba616 KG	275
129ba616 KG	276	/* outbound memory */
2dba0dea	277	pci_set_region(r++,
10795f42	278	CONFIG_SYS_PCIE2_MEM_BUS,
6d0f6bcf JCPV	279	CONFIG_SYS_PCIE2_MEM_PHYS,
6d0f6bcf JCPV	280	CONFIG_SYS_PCIE2_MEM_SIZE,
129ba616 KG	281	PCI_REGION_MEM);
	282
	283	/* outbound io */
2dba0dea	284	pci_set_region(r++,
5f91ef6a	285	CONFIG_SYS_PCIE2_IO_BUS,
6d0f6bcf JCPV	286	CONFIG_SYS_PCIE2_IO_PHYS,
6d0f6bcf JCPV	287	CONFIG_SYS_PCIE2_IO_SIZE,
129ba616 KG	288	PCI_REGION_IO);
129ba616 KG	289
2dba0dea	290	hose->region_count = r - hose->regions;
129ba616 KG	291	hose->first_busno=first_free_busno;
	292	pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
	293
	294	fsl_pci_init(hose);
	295	first_free_busno=hose->last_busno+1;
	296	printf (" PCIE2 on bus %02x - %02x\n",
	297	hose->first_busno,hose->last_busno);
	298
	299	} else {
	300	printf (" PCIE2: disabled\n");
	301	}
	302
	303	}
	304	#else
	305	gur->devdisr \|= MPC85xx_DEVDISR_PCIE2; /* disable */
	306	#endif
	307	#ifdef CONFIG_PCIE1
	308	{
6d0f6bcf	309	volatile ccsr_fsl_pci_t pci = (ccsr_fsl_pci_t ) CONFIG_SYS_PCIE1_ADDR;
129ba616	310	struct pci_controller *hose = &pcie1_hose;
86be510f	311	int pcie_ep = (host_agent <= 1) \|\| (host_agent == 4) \|\|
129ba616	312	(host_agent == 5);
9afc2ef0 RZ	313	int pcie_configured = (io_sel == 0x2) \|\| (io_sel == 0x3) \|\|
	314	(io_sel == 0x7) \|\| (io_sel == 0xb) \|\|
	315	(io_sel == 0xc) \|\| (io_sel == 0xf);
2dba0dea	316	struct pci_region *r = hose->regions;
129ba616 KG	317
	318	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
	319	printf ("\n PCIE1 connected to Slot 2 as %s (base address %x)",
	320	pcie_ep ? "End Point" : "Root Complex",
	321	(uint)pci);
	322	if (pci->pme_msg_det) {
	323	pci->pme_msg_det = 0xffffffff;
	324	debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
	325	}
	326	printf ("\n");
	327
	328	/* inbound */
2dba0dea	329	r += fsl_pci_setup_inbound_windows(r);
129ba616 KG	330
129ba616 KG	331	/* outbound memory */
2dba0dea	332	pci_set_region(r++,
10795f42	333	CONFIG_SYS_PCIE1_MEM_BUS,
6d0f6bcf JCPV	334	CONFIG_SYS_PCIE1_MEM_PHYS,
6d0f6bcf JCPV	335	CONFIG_SYS_PCIE1_MEM_SIZE,
129ba616 KG	336	PCI_REGION_MEM);
	337
	338	/* outbound io */
2dba0dea	339	pci_set_region(r++,
5f91ef6a	340	CONFIG_SYS_PCIE1_IO_BUS,
6d0f6bcf JCPV	341	CONFIG_SYS_PCIE1_IO_PHYS,
6d0f6bcf JCPV	342	CONFIG_SYS_PCIE1_IO_SIZE,
129ba616 KG	343	PCI_REGION_IO);
129ba616 KG	344
2dba0dea	345	hose->region_count = r - hose->regions;
129ba616 KG	346	hose->first_busno=first_free_busno;
	347
	348	pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
	349
	350	fsl_pci_init(hose);
	351
	352	first_free_busno=hose->last_busno+1;
	353	printf(" PCIE1 on bus %02x - %02x\n",
	354	hose->first_busno,hose->last_busno);
	355
	356	} else {
	357	printf (" PCIE1: disabled\n");
	358	}
	359
	360	}
	361	#else
	362	gur->devdisr \|= MPC85xx_DEVDISR_PCIE; /* disable */
	363	#endif
	364	}
	365	#endif
	366
	367	int board_early_init_r(void)
	368	{
6d0f6bcf	369	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
129ba616 KG	370	const u8 flash_esel = 2;
	371
	372	/*
	373	* Remap Boot flash + PROMJET region to caching-inhibited
	374	* so that flash can be erased properly.
	375	*/
	376
7c0d4a75	377	/* Flush d-cache and invalidate i-cache of any FLASH data */
3cbd8231 WD	378	flush_dcache();
3cbd8231 WD	379	invalidate_icache();
129ba616 KG	380
	381	/* invalidate existing TLB entry for flash + promjet */
	382	disable_tlb(flash_esel);
	383
c953ddfd	384	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
129ba616 KG	385	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G, /* perms, wimge */
	386	0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
	387
	388	return 0;
	389	}
	390
	391	#ifdef CONFIG_GET_CLK_FROM_ICS307
	392	/* decode S[0-2] to Output Divider (OD) */
	393	static unsigned char ics307_S_to_OD[] = {
	394	10, 2, 8, 4, 5, 7, 3, 6
	395	};
	396
	397	/* Calculate frequency being generated by ICS307-02 clock chip based upon
	398	* the control bytes being programmed into it. */
	399	/* XXX: This function should probably go into a common library */
	400	static unsigned long
	401	ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2)
	402	{
	403	const unsigned long InputFrequency = CONFIG_ICS307_REFCLK_HZ;
	404	unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
	405	unsigned long RDW = cw2 & 0x7F;
	406	unsigned long OD = ics307_S_to_OD[cw0 & 0x7];
	407	unsigned long freq;
	408
	409	/* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */
	410
	411	/* cw0: C1 C0 TTL F1 F0 S2 S1 S0
	412	* cw1: V8 V7 V6 V5 V4 V3 V2 V1
	413	* cw2: V0 R6 R5 R4 R3 R2 R1 R0
	414	*
	415	* R6:R0 = Reference Divider Word (RDW)
	416	* V8:V0 = VCO Divider Word (VDW)
	417	* S2:S0 = Output Divider Select (OD)
	418	* F1:F0 = Function of CLK2 Output
	419	* TTL = duty cycle
	420	* C1:C0 = internal load capacitance for cyrstal
	421	*/
	422
	423	/* Adding 1 to get a "nicely" rounded number, but this needs
	424	* more tweaking to get a "properly" rounded number. */
	425
	426	freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD));
	427
	428	debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2,
	429	freq);
	430	return freq;
	431	}
	432
	433	unsigned long get_board_sys_clk(ulong dummy)
	434	{
	435	return ics307_clk_freq (
	436	in8(PIXIS_BASE + PIXIS_VSYSCLK0),
	437	in8(PIXIS_BASE + PIXIS_VSYSCLK1),
	438	in8(PIXIS_BASE + PIXIS_VSYSCLK2)
	439	);
	440	}
	441
	442	unsigned long get_board_ddr_clk(ulong dummy)
	443	{
	444	return ics307_clk_freq (
	445	in8(PIXIS_BASE + PIXIS_VDDRCLK0),
	446	in8(PIXIS_BASE + PIXIS_VDDRCLK1),
	447	in8(PIXIS_BASE + PIXIS_VDDRCLK2)
	448	);
449	}
450	#else
451	unsigned long get_board_sys_clk(ulong dummy)
452	{
453	u8 i;
454	ulong val = 0;
455
456	i = in8(PIXIS_BASE + PIXIS_SPD);
457	i &= 0x07;
458
459	switch (i) {
460	case 0:
461	val = 33333333;
462	break;
463	case 1:
464	val = 40000000;
465	break;
466	case 2:
467	val = 50000000;
468	break;
469	case 3:
470	val = 66666666;
471	break;
472	case 4:
473	val = 83333333;
474	break;
475	case 5:
476	val = 100000000;
477	break;
478	case 6:
479	val = 133333333;
480	break;
481	case 7:
482	val = 166666666;
483	break;
484	}
485
486	return val;
487	}
488
489	unsigned long get_board_ddr_clk(ulong dummy)
490	{
491	u8 i;
492	ulong val = 0;
493
494	i = in8(PIXIS_BASE + PIXIS_SPD);
495	i &= 0x38;
496	i >>= 3;
497
498	switch (i) {
499	case 0:
500	val = 33333333;
501	break;
502	case 1:
503	val = 40000000;
504	break;
505	case 2:
506	val = 50000000;
507	break;
508	case 3:
509	val = 66666666;
510	break;
511	case 4:
512	val = 83333333;
513	break;
514	case 5:
515	val = 100000000;
516	break;
517	case 6:
518	val = 133333333;
519	break;
520	case 7:
521	val = 166666666;
522	break;
523	}
524	return val;
525	}
526	#endif
527
7e183cad LY	528	#ifdef CONFIG_TSEC_ENET
	529	int board_eth_init(bd_t *bis)
	530	{
	531	struct tsec_info_struct tsec_info[4];
	532	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	533	int num = 0;
	534
	535	#ifdef CONFIG_TSEC1
	536	SET_STD_TSEC_INFO(tsec_info[num], 1);
	537	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
	538	tsec_info[num].flags \|= TSEC_SGMII;
	539	num++;
	540	#endif
	541	#ifdef CONFIG_TSEC2
	542	SET_STD_TSEC_INFO(tsec_info[num], 2);
	543	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
	544	tsec_info[num].flags \|= TSEC_SGMII;
	545	num++;
	546	#endif
	547	#ifdef CONFIG_TSEC3
	548	SET_STD_TSEC_INFO(tsec_info[num], 3);
	549	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
	550	tsec_info[num].flags \|= TSEC_SGMII;
	551	num++;
	552	#endif
	553	#ifdef CONFIG_TSEC4
	554	SET_STD_TSEC_INFO(tsec_info[num], 4);
	555	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
	556	tsec_info[num].flags \|= TSEC_SGMII;
	557	num++;
	558	#endif
	559
	560	if (!num) {
	561	printf("No TSECs initialized\n");
	562
	563	return 0;
	564	}
	565
feede8b0	566	#ifdef CONFIG_FSL_SGMII_RISER
7e183cad	567	fsl_sgmii_riser_init(tsec_info, num);
feede8b0	568	#endif
7e183cad LY	569
	570	tsec_eth_init(bis, tsec_info, num);
	571
	572	return 0;
	573	}
	574	#endif
	575
129ba616 KG	576	#if defined(CONFIG_OF_BOARD_SETUP)
	577	void ft_board_setup(void blob, bd_t bd)
	578	{
b6730512 KG	579	phys_addr_t base;
b6730512 KG	580	phys_size_t size;
129ba616 KG	581
	582	ft_cpu_setup(blob, bd);
	583
	584	base = getenv_bootm_low();
	585	size = getenv_bootm_size();
	586
	587	fdt_fixup_memory(blob, (u64)base, (u64)size);
	588
129ba616	589	#ifdef CONFIG_PCIE3
2dba0dea	590	ft_fsl_pci_setup(blob, "pci0", &pcie3_hose);
129ba616 KG	591	#endif
129ba616 KG	592	#ifdef CONFIG_PCIE2
2dba0dea	593	ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
129ba616 KG	594	#endif
129ba616 KG	595	#ifdef CONFIG_PCIE1
2dba0dea	596	ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
129ba616	597	#endif
feede8b0 AF	598	#ifdef CONFIG_FSL_SGMII_RISER
	599	fsl_sgmii_riser_fdt_fixup(blob);
	600	#endif
129ba616 KG	601	}
	602	#endif
	603
	604	#ifdef CONFIG_MP
	605	extern void cpu_mp_lmb_reserve(struct lmb *lmb);
	606
	607	void board_lmb_reserve(struct lmb *lmb)
	608	{
	609	cpu_mp_lmb_reserve(lmb);
	610	}
	611	#endif