[u-boot.git] / drivers / gpio / mvgpio.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * (C) Copyright 2011
 * eInfochips Ltd. <www.einfochips.com>
 * Written-by: Ajay Bhargav <[email protected]>
 *
 * (C) Copyright 2010
 * Marvell Semiconductor <www.marvell.com>
 */

#ifndef __MVGPIO_H__
#define __MVGPIO_H__

#include <common.h>

/*
 * GPIO Register map for Marvell SOCs
 */
struct gpio_reg {
	u32 gplr;	/* Pin Level Register - 0x0000 */
	u32 pad0[2];
	u32 gpdr;	/* Pin Direction Register - 0x000C */
	u32 pad1[2];
	u32 gpsr;	/* Pin Output Set Register - 0x0018 */
	u32 pad2[2];
	u32 gpcr;	/* Pin Output Clear Register - 0x0024 */
	u32 pad3[2];
	u32 grer;	/* Rising-Edge Detect Enable Register - 0x0030 */
	u32 pad4[2];
	u32 gfer;	/* Falling-Edge Detect Enable Register - 0x003C */
	u32 pad5[2];
	u32 gedr;	/* Edge Detect Status Register - 0x0048 */
	u32 pad6[2];
	u32 gsdr;	/* Bitwise Set of GPIO Direction Register - 0x0054 */
	u32 pad7[2];
	u32 gcdr;	/* Bitwise Clear of GPIO Direction Register - 0x0060 */
	u32 pad8[2];
	u32 gsrer;	/* Bitwise Set of Rising-Edge Detect Enable
			   Register - 0x006C */
	u32 pad9[2];
	u32 gcrer;	/* Bitwise Clear of Rising-Edge Detect Enable
			   Register - 0x0078 */
	u32 pad10[2];
	u32 gsfer;	/* Bitwise Set of Falling-Edge Detect Enable
			   Register - 0x0084 */
	u32 pad11[2];
	u32 gcfer;	/* Bitwise Clear of Falling-Edge Detect Enable
			   Register - 0x0090 */
	u32 pad12[2];
	u32 apmask;	/* Bitwise Mask of Edge Detect Register - 0x009C */
};

#endif /* __MVGPIO_H__ */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
0c442298 AB	2	/*
	3	* (C) Copyright 2011
	4	* eInfochips Ltd. <www.einfochips.com>
c7c47ca2	5	* Written-by: Ajay Bhargav <[email protected]>
0c442298 AB	6	*
	7	* (C) Copyright 2010
	8	* Marvell Semiconductor <www.marvell.com>
0c442298 AB	9	*/
	10
	11	#ifndef __MVGPIO_H__
	12	#define __MVGPIO_H__
	13
	14	#include <common.h>
	15
0c442298	16	/*
3d046f6a	17	* GPIO Register map for Marvell SOCs
0c442298 AB	18	*/
	19	struct gpio_reg {
	20	u32 gplr; /* Pin Level Register - 0x0000 */
	21	u32 pad0[2];
	22	u32 gpdr; /* Pin Direction Register - 0x000C */
	23	u32 pad1[2];
	24	u32 gpsr; /* Pin Output Set Register - 0x0018 */
	25	u32 pad2[2];
	26	u32 gpcr; /* Pin Output Clear Register - 0x0024 */
	27	u32 pad3[2];
	28	u32 grer; /* Rising-Edge Detect Enable Register - 0x0030 */
	29	u32 pad4[2];
	30	u32 gfer; /* Falling-Edge Detect Enable Register - 0x003C */
	31	u32 pad5[2];
	32	u32 gedr; /* Edge Detect Status Register - 0x0048 */
	33	u32 pad6[2];
	34	u32 gsdr; /* Bitwise Set of GPIO Direction Register - 0x0054 */
	35	u32 pad7[2];
	36	u32 gcdr; /* Bitwise Clear of GPIO Direction Register - 0x0060 */
	37	u32 pad8[2];
	38	u32 gsrer; /* Bitwise Set of Rising-Edge Detect Enable
	39	Register - 0x006C */
	40	u32 pad9[2];
	41	u32 gcrer; /* Bitwise Clear of Rising-Edge Detect Enable
	42	Register - 0x0078 */
	43	u32 pad10[2];
	44	u32 gsfer; /* Bitwise Set of Falling-Edge Detect Enable
	45	Register - 0x0084 */
	46	u32 pad11[2];
	47	u32 gcfer; /* Bitwise Clear of Falling-Edge Detect Enable
	48	Register - 0x0090 */
	49	u32 pad12[2];
	50	u32 apmask; /* Bitwise Mask of Edge Detect Register - 0x009C */
	51	};
0c442298 AB	52
0c442298 AB	53	#endif /* __MVGPIO_H__ */