[u-boot.git] / include / configs / work_92105.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * WORK Microwave work_92105 board configuration file
 *
 * (C) Copyright 2014  DENX Software Engineering GmbH
 * Written-by: Albert ARIBAUD <[email protected]>
 */

#ifndef __CONFIG_WORK_92105_H__
#define __CONFIG_WORK_92105_H__

/* SoC and board defines */
#include <linux/sizes.h>
#include <asm/arch/cpu.h>

/*
 * Define work_92105 machine type by hand -- done only for compatibility
 * with original board code
 */
#define CONFIG_MACH_TYPE		736

#if !defined(CONFIG_SPL_BUILD)
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif

/*
 * Memory configurations
 */
#define CONFIG_SYS_MALLOC_LEN		SZ_1M
#define CONFIG_SYS_SDRAM_BASE		EMC_DYCS0_BASE
#define CONFIG_SYS_SDRAM_SIZE		SZ_128M

#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + SZ_32K)

#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + SZ_512K \
					 - GENERATED_GBL_DATA_SIZE)

/*
 * Ethernet Driver
 */

#define CONFIG_LPC32XX_ETH
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
/* FIXME: remove "Waiting for PHY auto negotiation to complete..." message */

/*
 * I2C driver
 */

#define CONFIG_SYS_I2C_LEGACY
#define CONFIG_SYS_I2C_SPEED 350000

/*
 * I2C EEPROM
 */

#define CONFIG_SYS_I2C_EEPROM_ADDR 0x56
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2

/*
 * I2C RTC
 */

#define CONFIG_RTC_DS1374

/*
 * U-Boot General Configurations
 */
#define CONFIG_SYS_CBSIZE		1024
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE

/*
 * NAND chip timings for FIXME: which one?
 */

#define CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY  333333333
#define CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY   10000000
#define CONFIG_LPC32XX_NAND_MLC_NAND_TA      18181818
#define CONFIG_LPC32XX_NAND_MLC_RD_HIGH      31250000
#define CONFIG_LPC32XX_NAND_MLC_RD_LOW       45454545
#define CONFIG_LPC32XX_NAND_MLC_WR_HIGH      40000000
#define CONFIG_LPC32XX_NAND_MLC_WR_LOW       83333333

/*
 * NAND
 */

/* driver configuration */
#define CONFIG_SYS_NAND_SELF_INIT
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_MAX_NAND_CHIPS 1
#define CONFIG_SYS_NAND_BASE MLC_NAND_BASE
#define CONFIG_NAND_LPC32XX_MLC

/*
 * GPIO
 */

#define CONFIG_LPC32XX_GPIO

/*
 * Environment
 */

/*
 * Boot Linux
 */
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG

#define CONFIG_BOOTFILE			"uImage"
#define CONFIG_LOADADDR			0x80008000

/*
 * SPL
 */

/* SPL will be executed at offset 0 */
/* SPL will use SRAM as stack */
#define CONFIG_SPL_STACK     0x0000FFF8
/* Use the framework and generic lib */
/* SPL will use serial */
/* SPL will load U-Boot from NAND offset 0x40000 */
#define CONFIG_SYS_NAND_U_BOOT_OFFS  0x00040000
#define CONFIG_SPL_PAD_TO 0x20000
/* U-Boot will be 0x40000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */
#define CONFIG_SYS_MONITOR_LEN 0x40000 /* actually, MAX size */
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_DST   CONFIG_SYS_TEXT_BASE

/*
 * Include SoC specific configuration
 */
#include <asm/arch/config.h>

#endif  /* __CONFIG_WORK_92105_H__*/
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
412ae53a AA	2	/*
	3	* WORK Microwave work_92105 board configuration file
	4	*
	5	* (C) Copyright 2014 DENX Software Engineering GmbH
	6	* Written-by: Albert ARIBAUD <[email protected]>
412ae53a AA	7	*/
	8
	9	#ifndef __CONFIG_WORK_92105_H__
	10	#define __CONFIG_WORK_92105_H__
	11
	12	/* SoC and board defines */
	13	#include <linux/sizes.h>
	14	#include <asm/arch/cpu.h>
	15
	16	/*
	17	* Define work_92105 machine type by hand -- done only for compatibility
	18	* with original board code
	19	*/
cd7b6344	20	#define CONFIG_MACH_TYPE 736
412ae53a	21
412ae53a AA	22	#if !defined(CONFIG_SPL_BUILD)
	23	#define CONFIG_SKIP_LOWLEVEL_INIT
	24	#endif
412ae53a AA	25
	26	/*
	27	* Memory configurations
	28	*/
412ae53a AA	29	#define CONFIG_SYS_MALLOC_LEN SZ_1M
	30	#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE
	31	#define CONFIG_SYS_SDRAM_SIZE SZ_128M
412ae53a AA	32
	33	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K)
	34
	35	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_512K \
	36	- GENERATED_GBL_DATA_SIZE)
	37
412ae53a AA	38	/*
	39	* Ethernet Driver
	40	*/
	41
412ae53a	42	#define CONFIG_LPC32XX_ETH
412ae53a	43	#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
412ae53a AA	44	/* FIXME: remove "Waiting for PHY auto negotiation to complete..." message */
	45
	46	/*
	47	* I2C driver
	48	*/
	49
69d9eda4	50	#define CONFIG_SYS_I2C_LEGACY
412ae53a AA	51	#define CONFIG_SYS_I2C_SPEED 350000
	52
	53	/*
	54	* I2C EEPROM
	55	*/
	56
412ae53a AA	57	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x56
	58	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
	59
	60	/*
	61	* I2C RTC
	62	*/
	63
412ae53a AA	64	#define CONFIG_RTC_DS1374
412ae53a AA	65
412ae53a AA	66	/*
	67	* U-Boot General Configurations
	68	*/
412ae53a	69	#define CONFIG_SYS_CBSIZE 1024
412ae53a AA	70	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
412ae53a AA	71
412ae53a AA	72	/*
	73	* NAND chip timings for FIXME: which one?
	74	*/
	75
	76	#define CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY 333333333
	77	#define CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY 10000000
	78	#define CONFIG_LPC32XX_NAND_MLC_NAND_TA 18181818
	79	#define CONFIG_LPC32XX_NAND_MLC_RD_HIGH 31250000
	80	#define CONFIG_LPC32XX_NAND_MLC_RD_LOW 45454545
	81	#define CONFIG_LPC32XX_NAND_MLC_WR_HIGH 40000000
	82	#define CONFIG_LPC32XX_NAND_MLC_WR_LOW 83333333
	83
	84	/*
	85	* NAND
	86	*/
	87
	88	/* driver configuration */
	89	#define CONFIG_SYS_NAND_SELF_INIT
	90	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	91	#define CONFIG_SYS_MAX_NAND_CHIPS 1
	92	#define CONFIG_SYS_NAND_BASE MLC_NAND_BASE
	93	#define CONFIG_NAND_LPC32XX_MLC
	94
412ae53a AA	95	/*
	96	* GPIO
	97	*/
	98
412ae53a AA	99	#define CONFIG_LPC32XX_GPIO
412ae53a AA	100
412ae53a AA	101	/*
	102	* Environment
	103	*/
	104
412ae53a AA	105	/*
	106	* Boot Linux
	107	*/
	108	#define CONFIG_CMDLINE_TAG
	109	#define CONFIG_SETUP_MEMORY_TAGS
	110	#define CONFIG_INITRD_TAG
	111
412ae53a	112	#define CONFIG_BOOTFILE "uImage"
412ae53a AA	113	#define CONFIG_LOADADDR 0x80008000
	114
	115	/*
	116	* SPL
	117	*/
	118
	119	/* SPL will be executed at offset 0 */
412ae53a AA	120	/* SPL will use SRAM as stack */
412ae53a AA	121	#define CONFIG_SPL_STACK 0x0000FFF8
412ae53a	122	/* Use the framework and generic lib */
412ae53a	123	/* SPL will use serial */
412ae53a	124	/* SPL will load U-Boot from NAND offset 0x40000 */
412ae53a AA	125	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00040000
	126	#define CONFIG_SPL_PAD_TO 0x20000
	127	/* U-Boot will be 0x40000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */
	128	#define CONFIG_SYS_MONITOR_LEN 0x40000 /* actually, MAX size */
	129	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
	130	#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
	131
	132	/*
	133	* Include SoC specific configuration
	134	*/
	135	#include <asm/arch/config.h>
	136
	137	#endif /* __CONFIG_WORK_92105_H__*/