[u-boot.git] / board / softing / vining_2000 / vining_2000.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2016 samtec automotive software & electronics gmbh
 * Copyright (C) 2017-2019 softing automotive electronics gmbH
 *
 * Author: Christoph Fritz <[email protected]>
 */

#include <asm/arch/clock.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/io.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <env.h>
#include <linux/sizes.h>
#include <common.h>
#include <fsl_esdhc_imx.h>
#include <mmc.h>
#include <i2c.h>
#include <miiphy.h>
#include <netdev.h>
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>
#include <usb.h>
#include <usb/ehci-ci.h>
#include <pwm.h>
#include <wait_bit.h>

DECLARE_GLOBAL_DATA_PTR;

#define UART_PAD_CTRL  (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP |	\
	PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |	\
	PAD_CTL_SRE_FAST)

#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PKE |	\
	PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm |		\
	PAD_CTL_SRE_FAST)

#define ENET_CLK_PAD_CTRL  PAD_CTL_DSE_34ohm

#define ENET_RX_PAD_CTRL  (PAD_CTL_PKE |			\
	PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_HIGH |		\
	PAD_CTL_SRE_FAST)

#define I2C_PAD_CTRL  (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP |	\
	PAD_CTL_PKE | PAD_CTL_ODE | PAD_CTL_SPEED_MED |		\
	PAD_CTL_DSE_40ohm)

#define USDHC_CLK_PAD_CTRL  (PAD_CTL_HYS | PAD_CTL_SPEED_MED |	\
	PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST)

#define USDHC_PAD_CTRL  (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP |	\
	PAD_CTL_PKE |  PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm |	\
	PAD_CTL_SRE_FAST)

#define USDHC_RESET_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP |	\
	PAD_CTL_PKE |  PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm)

#define GPIO_PAD_CTRL  (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP |	\
	PAD_CTL_PKE)

int dram_init(void)
{
	gd->ram_size = imx_ddr_size();

	return 0;
}

static iomux_v3_cfg_t const fec1_pads[] = {
	MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
	MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
	MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
	MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL) |
		MUX_MODE_SION,
	/* LAN8720 PHY Reset */
	MX6_PAD_RGMII1_TD3__GPIO5_IO_9 | MUX_PAD_CTRL(NO_PAD_CTRL),
};

static iomux_v3_cfg_t const pwm_led_pads[] = {
	MX6_PAD_RGMII2_RD2__PWM2_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* green */
	MX6_PAD_RGMII2_TD2__PWM6_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* red */
	MX6_PAD_RGMII2_RD3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* blue */
};

#define PHY_RESET IMX_GPIO_NR(5, 9)

int board_eth_init(bd_t *bis)
{
	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
	int ret;
	unsigned char eth1addr[6];

	/* just to get secound mac address */
	imx_get_mac_from_fuse(1, eth1addr);
	if (!env_get("eth1addr") && is_valid_ethaddr(eth1addr))
		eth_env_set_enetaddr("eth1addr", eth1addr);

	imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));

	/*
	 * Generate phy reference clock via pin IOMUX ENET_REF_CLK1/2 by erasing
	 * ENET1/2_TX_CLK_DIR gpr1[14:13], so that reference clock is driven by
	 * ref_enetpll0/1 and enable ENET1/2_TX_CLK output driver.
	 */
	clrsetbits_le32(&iomuxc_regs->gpr[1],
			IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK |
			IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK,
			IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK |
			IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);

	ret = enable_fec_anatop_clock(0, ENET_50MHZ);
	if (ret)
		goto eth_fail;

	/* reset phy */
	gpio_request(PHY_RESET, "PHY-reset");
	gpio_direction_output(PHY_RESET, 0);
	mdelay(16);
	gpio_set_value(PHY_RESET, 1);
	mdelay(1);

	ret = fecmxc_initialize_multi(bis, 0, CONFIG_FEC_MXC_PHYADDR,
					IMX_FEC_BASE);
	if (ret)
		goto eth_fail;

	return ret;

eth_fail:
	printf("FEC MXC: %s:failed (%i)\n", __func__, ret);
	gpio_set_value(PHY_RESET, 0);
	return ret;
}

#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
/* I2C1 for PMIC */
static struct i2c_pads_info i2c_pad_info1 = {
	.scl = {
		.i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
		.gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
		.gp = IMX_GPIO_NR(1, 0),
	},
	.sda = {
		.i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
		.gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
		.gp = IMX_GPIO_NR(1, 1),
	},
};

static struct pmic *pfuze_init(unsigned char i2cbus)
{
	struct pmic *p;
	int ret;
	u32 reg;

	ret = power_pfuze100_init(i2cbus);
	if (ret)
		return NULL;

	p = pmic_get("PFUZE100");
	ret = pmic_probe(p);
	if (ret)
		return NULL;

	pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
	printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);

	/* Set SW1AB stanby volage to 0.975V */
	pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
	reg &= ~SW1x_STBY_MASK;
	reg |= SW1x_0_975V;
	pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);

	/* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
	pmic_reg_read(p, PFUZE100_SW1ABCONF, &reg);
	reg &= ~SW1xCONF_DVSSPEED_MASK;
	reg |= SW1xCONF_DVSSPEED_4US;
	pmic_reg_write(p, PFUZE100_SW1ABCONF, reg);

	/* Set SW1C standby voltage to 0.975V */
	pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg);
	reg &= ~SW1x_STBY_MASK;
	reg |= SW1x_0_975V;
	pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);

	/* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
	pmic_reg_read(p, PFUZE100_SW1CCONF, &reg);
	reg &= ~SW1xCONF_DVSSPEED_MASK;
	reg |= SW1xCONF_DVSSPEED_4US;
	pmic_reg_write(p, PFUZE100_SW1CCONF, reg);

	return p;
}

static int pfuze_mode_init(struct pmic *p, u32 mode)
{
	unsigned char offset, i, switch_num;
	u32 id;
	int ret;

	pmic_reg_read(p, PFUZE100_DEVICEID, &id);
	id = id & 0xf;

	if (id == 0) {
		switch_num = 6;
		offset = PFUZE100_SW1CMODE;
	} else if (id == 1) {
		switch_num = 4;
		offset = PFUZE100_SW2MODE;
	} else {
		printf("Not supported, id=%d\n", id);
		return -EINVAL;
	}

	ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode);
	if (ret < 0) {
		printf("Set SW1AB mode error!\n");
		return ret;
	}

	for (i = 0; i < switch_num - 1; i++) {
		ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode);
		if (ret < 0) {
			printf("Set switch 0x%x mode error!\n",
			       offset + i * SWITCH_SIZE);
			return ret;
		}
	}

	return ret;
}

int power_init_board(void)
{
	struct pmic *p;
	int ret;

	p = pfuze_init(I2C_PMIC);
	if (!p)
		return -ENODEV;

	ret = pfuze_mode_init(p, APS_PFM);
	if (ret < 0)
		return ret;

	return 0;
}

#ifdef CONFIG_USB_EHCI_MX6
static iomux_v3_cfg_t const usb_otg_pads[] = {
	/* OGT1 */
	MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
	MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
	/* OTG2 */
	MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
};

static void setup_iomux_usb(void)
{
	imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
					 ARRAY_SIZE(usb_otg_pads));
}

int board_usb_phy_mode(int port)
{
	if (port == 1)
		return USB_INIT_HOST;
	else
		return usb_phy_mode(port);
}
#endif

#ifdef CONFIG_PWM_IMX
static int set_pwm_leds(void)
{
	int ret;

	imx_iomux_v3_setup_multiple_pads(pwm_led_pads,
					 ARRAY_SIZE(pwm_led_pads));
	/* enable backlight PWM 2, green LED */
	ret = pwm_init(1, 0, 0);
	if (ret)
		goto error;
	/* duty cycle 200ns, period: 8000ns */
	ret = pwm_config(1, 200, 8000);
	if (ret)
		goto error;
	ret = pwm_enable(1);
	if (ret)
		goto error;

	/* enable backlight PWM 1, blue LED */
	ret = pwm_init(0, 0, 0);
	if (ret)
		goto error;
	/* duty cycle 200ns, period: 8000ns */
	ret = pwm_config(0, 200, 8000);
	if (ret)
		goto error;
	ret = pwm_enable(0);
	if (ret)
		goto error;

	/* enable backlight PWM 6, red LED */
	ret = pwm_init(5, 0, 0);
	if (ret)
		goto error;
	/* duty cycle 200ns, period: 8000ns */
	ret = pwm_config(5, 200, 8000);
	if (ret)
		goto error;
	ret = pwm_enable(5);

error:
	return ret;
}
#else
static int set_pwm_leds(void)
{
	return 0;
}
#endif

#define ADCx_HC0        0x00
#define ADCx_HS         0x08
#define ADCx_HS_C0      BIT(0)
#define ADCx_R0         0x0c
#define ADCx_CFG        0x14
#define ADCx_CFG_SWMODE 0x308
#define ADCx_GC         0x18
#define ADCx_GC_CAL     BIT(7)

static int read_adc(u32 *val)
{
	int ret;
	void __iomem *b = map_physmem(ADC1_BASE_ADDR, 0x100, MAP_NOCACHE);

	/* use software mode */
	writel(ADCx_CFG_SWMODE, b + ADCx_CFG);

	/* start auto calibration */
	setbits_le32(b + ADCx_GC, ADCx_GC_CAL);
	ret = wait_for_bit_le32(b + ADCx_GC, ADCx_GC_CAL, ADCx_GC_CAL, 10, 0);
	if (ret)
		goto adc_exit;

	/* start conversion */
	writel(0, b + ADCx_HC0);

	/* wait for conversion */
	ret = wait_for_bit_le32(b + ADCx_HS, ADCx_HS_C0, ADCx_HS_C0, 10, 0);
	if (ret)
		goto adc_exit;

	/* read result */
	*val = readl(b + ADCx_R0);

adc_exit:
	if (ret)
		printf("ADC failure (ret=%i)\n", ret);
	unmap_physmem(b, MAP_NOCACHE);
	return ret;
}

#define VAL_UPPER	2498
#define VAL_LOWER	1550

static int set_pin_state(void)
{
	u32 val;
	int ret;

	ret = read_adc(&val);
	if (ret)
		return ret;

	if (val >= VAL_UPPER)
		env_set("pin_state", "connected");
	else if (val < VAL_UPPER && val > VAL_LOWER)
		env_set("pin_state", "open");
	else
		env_set("pin_state", "button");

	return ret;
}

int board_late_init(void)
{
	int ret;

	ret = set_pwm_leds();
	if (ret)
		return ret;

	ret = set_pin_state();

	return ret;
}

int board_early_init_f(void)
{
	setup_iomux_usb();

	return 0;
}

int board_init(void)
{
	/* Address of boot parameters */
	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

#ifdef CONFIG_SYS_I2C_MXC
	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
#endif

	return 0;
}

int checkboard(void)
{
	puts("Board: VIN|ING 2000\n");

	return 0;
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
730d2544 CF	2	/*
730d2544 CF	3	* Copyright (C) 2016 samtec automotive software & electronics gmbh
4c05e966	4	* Copyright (C) 2017-2019 softing automotive electronics gmbH
730d2544 CF	5	*
730d2544 CF	6	* Author: Christoph Fritz <[email protected]>
730d2544 CF	7	*/
	8
	9	#include <asm/arch/clock.h>
	10	#include <asm/arch/crm_regs.h>
	11	#include <asm/arch/iomux.h>
	12	#include <asm/arch/imx-regs.h>
	13	#include <asm/arch/mx6-pins.h>
	14	#include <asm/arch/sys_proto.h>
	15	#include <asm/gpio.h>
552a848e	16	#include <asm/mach-imx/iomux-v3.h>
730d2544	17	#include <asm/io.h>
552a848e	18	#include <asm/mach-imx/mxc_i2c.h>
9fb625ce	19	#include <env.h>
730d2544 CF	20	#include <linux/sizes.h>
730d2544 CF	21	#include <common.h>
e37ac717	22	#include <fsl_esdhc_imx.h>
730d2544 CF	23	#include <mmc.h>
	24	#include <i2c.h>
	25	#include <miiphy.h>
	26	#include <netdev.h>
	27	#include <power/pmic.h>
	28	#include <power/pfuze100_pmic.h>
	29	#include <usb.h>
	30	#include <usb/ehci-ci.h>
	31	#include <pwm.h>
	32	#include <wait_bit.h>
	33
	34	DECLARE_GLOBAL_DATA_PTR;
	35
	36	#define UART_PAD_CTRL (PAD_CTL_HYS \| PAD_CTL_PUS_100K_UP \| \
	37	PAD_CTL_PKE \| PAD_CTL_SPEED_MED \| PAD_CTL_DSE_40ohm \| \
	38	PAD_CTL_SRE_FAST)
	39
	40	#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP \| PAD_CTL_PKE \| \
	41	PAD_CTL_SPEED_HIGH \| PAD_CTL_DSE_48ohm \| \
	42	PAD_CTL_SRE_FAST)
	43
	44	#define ENET_CLK_PAD_CTRL PAD_CTL_DSE_34ohm
	45
	46	#define ENET_RX_PAD_CTRL (PAD_CTL_PKE \| \
	47	PAD_CTL_PUS_100K_DOWN \| PAD_CTL_SPEED_HIGH \| \
	48	PAD_CTL_SRE_FAST)
	49
	50	#define I2C_PAD_CTRL (PAD_CTL_HYS \| PAD_CTL_PUS_100K_UP \| \
	51	PAD_CTL_PKE \| PAD_CTL_ODE \| PAD_CTL_SPEED_MED \| \
	52	PAD_CTL_DSE_40ohm)
	53
	54	#define USDHC_CLK_PAD_CTRL (PAD_CTL_HYS \| PAD_CTL_SPEED_MED \| \
	55	PAD_CTL_DSE_80ohm \| PAD_CTL_SRE_FAST)
	56
	57	#define USDHC_PAD_CTRL (PAD_CTL_HYS \| PAD_CTL_PUS_47K_UP \| \
	58	PAD_CTL_PKE \| PAD_CTL_SPEED_MED \| PAD_CTL_DSE_80ohm \| \
	59	PAD_CTL_SRE_FAST)
	60
d5786308 CF	61	#define USDHC_RESET_CTRL (PAD_CTL_HYS \| PAD_CTL_PUS_47K_UP \| \
	62	PAD_CTL_PKE \| PAD_CTL_SPEED_MED \| PAD_CTL_DSE_80ohm)
	63
730d2544 CF	64	#define GPIO_PAD_CTRL (PAD_CTL_HYS \| PAD_CTL_PUS_100K_UP \| \
	65	PAD_CTL_PKE)
	66
	67	int dram_init(void)
	68	{
	69	gd->ram_size = imx_ddr_size();
	70
	71	return 0;
	72	}
	73
730d2544 CF	74	static iomux_v3_cfg_t const fec1_pads[] = {
	75	MX6_PAD_ENET1_MDC__ENET1_MDC \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	76	MX6_PAD_ENET1_MDIO__ENET1_MDIO \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	77	MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 \| MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
	78	MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 \| MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
	79	MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	80	MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	81	MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN \| MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
	82	MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	83	MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 \| MUX_PAD_CTRL(ENET_CLK_PAD_CTRL) \|
	84	MUX_MODE_SION,
	85	/* LAN8720 PHY Reset */
	86	MX6_PAD_RGMII1_TD3__GPIO5_IO_9 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	87	};
	88
	89	static iomux_v3_cfg_t const pwm_led_pads[] = {
	90	MX6_PAD_RGMII2_RD2__PWM2_OUT \| MUX_PAD_CTRL(NO_PAD_CTRL), /* green */
	91	MX6_PAD_RGMII2_TD2__PWM6_OUT \| MUX_PAD_CTRL(NO_PAD_CTRL), /* red */
	92	MX6_PAD_RGMII2_RD3__PWM1_OUT \| MUX_PAD_CTRL(NO_PAD_CTRL), /* blue */
	93	};
	94
730d2544 CF	95	#define PHY_RESET IMX_GPIO_NR(5, 9)
	96
	97	int board_eth_init(bd_t *bis)
	98	{
	99	struct iomuxc iomuxc_regs = (struct iomuxc )IOMUXC_BASE_ADDR;
	100	int ret;
	101	unsigned char eth1addr[6];
	102
	103	/* just to get secound mac address */
	104	imx_get_mac_from_fuse(1, eth1addr);
00caae6d	105	if (!env_get("eth1addr") && is_valid_ethaddr(eth1addr))
fd1e959e	106	eth_env_set_enetaddr("eth1addr", eth1addr);
730d2544 CF	107
	108	imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
	109
	110	/*
	111	* Generate phy reference clock via pin IOMUX ENET_REF_CLK1/2 by erasing
	112	* ENET1/2_TX_CLK_DIR gpr1[14:13], so that reference clock is driven by
	113	* ref_enetpll0/1 and enable ENET1/2_TX_CLK output driver.
	114	*/
	115	clrsetbits_le32(&iomuxc_regs->gpr[1],
	116	IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK \|
	117	IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK,
	118	IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK \|
	119	IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
	120
	121	ret = enable_fec_anatop_clock(0, ENET_50MHZ);
	122	if (ret)
	123	goto eth_fail;
	124
	125	/* reset phy */
0e0d38f4	126	gpio_request(PHY_RESET, "PHY-reset");
730d2544 CF	127	gpio_direction_output(PHY_RESET, 0);
	128	mdelay(16);
	129	gpio_set_value(PHY_RESET, 1);
	130	mdelay(1);
	131
	132	ret = fecmxc_initialize_multi(bis, 0, CONFIG_FEC_MXC_PHYADDR,
	133	IMX_FEC_BASE);
	134	if (ret)
	135	goto eth_fail;
	136
	137	return ret;
	138
	139	eth_fail:
	140	printf("FEC MXC: %s:failed (%i)\n", __func__, ret);
	141	gpio_set_value(PHY_RESET, 0);
	142	return ret;
	143	}
	144
	145	#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
	146	/* I2C1 for PMIC */
	147	static struct i2c_pads_info i2c_pad_info1 = {
	148	.scl = {
	149	.i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL \| PC,
	150	.gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 \| PC,
	151	.gp = IMX_GPIO_NR(1, 0),
	152	},
	153	.sda = {
	154	.i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA \| PC,
	155	.gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 \| PC,
	156	.gp = IMX_GPIO_NR(1, 1),
	157	},
	158	};
	159
	160	static struct pmic *pfuze_init(unsigned char i2cbus)
	161	{
	162	struct pmic *p;
	163	int ret;
	164	u32 reg;
	165
	166	ret = power_pfuze100_init(i2cbus);
	167	if (ret)
	168	return NULL;
	169
	170	p = pmic_get("PFUZE100");
	171	ret = pmic_probe(p);
	172	if (ret)
	173	return NULL;
	174
	175	pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
	176	printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
	177
	178	/* Set SW1AB stanby volage to 0.975V */
	179	pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
	180	reg &= ~SW1x_STBY_MASK;
	181	reg \|= SW1x_0_975V;
	182	pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
	183
	184	/* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
	185	pmic_reg_read(p, PFUZE100_SW1ABCONF, &reg);
	186	reg &= ~SW1xCONF_DVSSPEED_MASK;
	187	reg \|= SW1xCONF_DVSSPEED_4US;
	188	pmic_reg_write(p, PFUZE100_SW1ABCONF, reg);
	189
	190	/* Set SW1C standby voltage to 0.975V */
191	pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg);
192	reg &= ~SW1x_STBY_MASK;
193	reg \|= SW1x_0_975V;
194	pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
195
196	/* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
197	pmic_reg_read(p, PFUZE100_SW1CCONF, &reg);
198	reg &= ~SW1xCONF_DVSSPEED_MASK;
199	reg \|= SW1xCONF_DVSSPEED_4US;
200	pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
201
202	return p;
203	}
204
205	static int pfuze_mode_init(struct pmic *p, u32 mode)
206	{
207	unsigned char offset, i, switch_num;
208	u32 id;
209	int ret;
210
211	pmic_reg_read(p, PFUZE100_DEVICEID, &id);
212	id = id & 0xf;
213
214	if (id == 0) {
215	switch_num = 6;
216	offset = PFUZE100_SW1CMODE;
217	} else if (id == 1) {
218	switch_num = 4;
219	offset = PFUZE100_SW2MODE;
220	} else {
221	printf("Not supported, id=%d\n", id);
222	return -EINVAL;
223	}
224
225	ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode);
226	if (ret < 0) {
227	printf("Set SW1AB mode error!\n");
228	return ret;
229	}
230
231	for (i = 0; i < switch_num - 1; i++) {
232	ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode);
233	if (ret < 0) {
234	printf("Set switch 0x%x mode error!\n",
235	offset + i * SWITCH_SIZE);
236	return ret;
237	}
238	}
239
240	return ret;
241	}
242
243	int power_init_board(void)
244	{
245	struct pmic *p;
246	int ret;
247
248	p = pfuze_init(I2C_PMIC);
249	if (!p)
250	return -ENODEV;
251
252	ret = pfuze_mode_init(p, APS_PFM);
253	if (ret < 0)
254	return ret;
255
256	return 0;
257	}
258
259	#ifdef CONFIG_USB_EHCI_MX6
260	static iomux_v3_cfg_t const usb_otg_pads[] = {
261	/* OGT1 */
262	MX6_PAD_GPIO1_IO09__USB_OTG1_PWR \| MUX_PAD_CTRL(NO_PAD_CTRL),
263	MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID \| MUX_PAD_CTRL(NO_PAD_CTRL),
264	/* OTG2 */
265	MX6_PAD_GPIO1_IO12__USB_OTG2_PWR \| MUX_PAD_CTRL(NO_PAD_CTRL)
266	};
267
268	static void setup_iomux_usb(void)
269	{
270	imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
271	ARRAY_SIZE(usb_otg_pads));
272	}
273
274	int board_usb_phy_mode(int port)
275	{
276	if (port == 1)
277	return USB_INIT_HOST;
278	else
279	return usb_phy_mode(port);
280	}
281	#endif
282
283	#ifdef CONFIG_PWM_IMX
284	static int set_pwm_leds(void)
285	{
286	int ret;
287
288	imx_iomux_v3_setup_multiple_pads(pwm_led_pads,
289	ARRAY_SIZE(pwm_led_pads));
290	/* enable backlight PWM 2, green LED */
291	ret = pwm_init(1, 0, 0);
292	if (ret)
293	goto error;
294	/* duty cycle 200ns, period: 8000ns */
295	ret = pwm_config(1, 200, 8000);
296	if (ret)
297	goto error;
298	ret = pwm_enable(1);
299	if (ret)
300	goto error;
301
302	/* enable backlight PWM 1, blue LED */
303	ret = pwm_init(0, 0, 0);
304	if (ret)
305	goto error;
306	/* duty cycle 200ns, period: 8000ns */
307	ret = pwm_config(0, 200, 8000);
308	if (ret)
309	goto error;
310	ret = pwm_enable(0);
311	if (ret)
312	goto error;
313
314	/* enable backlight PWM 6, red LED */
315	ret = pwm_init(5, 0, 0);
316	if (ret)
317	goto error;
318	/* duty cycle 200ns, period: 8000ns */
319	ret = pwm_config(5, 200, 8000);
320	if (ret)
321	goto error;
322	ret = pwm_enable(5);
323
324	error:
325	return ret;
326	}
327	#else
328	static int set_pwm_leds(void)
329	{
330	return 0;
331	}
332	#endif
333
334	#define ADCx_HC0 0x00
335	#define ADCx_HS 0x08
336	#define ADCx_HS_C0 BIT(0)
337	#define ADCx_R0 0x0c
338	#define ADCx_CFG 0x14
339	#define ADCx_CFG_SWMODE 0x308
340	#define ADCx_GC 0x18
341	#define ADCx_GC_CAL BIT(7)
342
343	static int read_adc(u32 *val)
344	{
345	int ret;
346	void __iomem *b = map_physmem(ADC1_BASE_ADDR, 0x100, MAP_NOCACHE);
347
348	/* use software mode */
349	writel(ADCx_CFG_SWMODE, b + ADCx_CFG);
350
351	/* start auto calibration */
352	setbits_le32(b + ADCx_GC, ADCx_GC_CAL);
48263504	353	ret = wait_for_bit_le32(b + ADCx_GC, ADCx_GC_CAL, ADCx_GC_CAL, 10, 0);
730d2544 CF	354	if (ret)
	355	goto adc_exit;
	356
	357	/* start conversion */
	358	writel(0, b + ADCx_HC0);
	359
	360	/* wait for conversion */
48263504	361	ret = wait_for_bit_le32(b + ADCx_HS, ADCx_HS_C0, ADCx_HS_C0, 10, 0);
730d2544 CF	362	if (ret)
	363	goto adc_exit;
	364
	365	/* read result */
	366	*val = readl(b + ADCx_R0);
	367
	368	adc_exit:
	369	if (ret)
	370	printf("ADC failure (ret=%i)\n", ret);
	371	unmap_physmem(b, MAP_NOCACHE);
	372	return ret;
	373	}
	374
	375	#define VAL_UPPER 2498
	376	#define VAL_LOWER 1550
	377
	378	static int set_pin_state(void)
	379	{
	380	u32 val;
	381	int ret;
	382
	383	ret = read_adc(&val);
	384	if (ret)
	385	return ret;
	386
	387	if (val >= VAL_UPPER)
382bee57	388	env_set("pin_state", "connected");
730d2544	389	else if (val < VAL_UPPER && val > VAL_LOWER)
382bee57	390	env_set("pin_state", "open");
730d2544	391	else
382bee57	392	env_set("pin_state", "button");
730d2544 CF	393
	394	return ret;
	395	}
	396
	397	int board_late_init(void)
	398	{
	399	int ret;
	400
	401	ret = set_pwm_leds();
	402	if (ret)
	403	return ret;
	404
	405	ret = set_pin_state();
	406
	407	return ret;
	408	}
	409
	410	int board_early_init_f(void)
	411	{
730d2544 CF	412	setup_iomux_usb();
	413
	414	return 0;
	415	}
	416
730d2544 CF	417	int board_init(void)
	418	{
	419	/* Address of boot parameters */
	420	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
	421
	422	#ifdef CONFIG_SYS_I2C_MXC
	423	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
	424	#endif
	425
	426	return 0;
	427	}
	428
	429	int checkboard(void)
	430	{
	431	puts("Board: VIN\|ING 2000\n");
	432
	433	return 0;
	434	}