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1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | /* | |
47d7e3b5 | 3 | * Copyright (C) 2020, Sean Anderson <[email protected]> |
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4 | * Copyright (C) 2018, Bin Meng <[email protected]> |
5 | * | |
6 | * U-Boot syscon driver for SiFive's Core Local Interruptor (CLINT). | |
7 | * The CLINT block holds memory-mapped control and status registers | |
8 | * associated with software and timer interrupts. | |
9 | */ | |
10 | ||
11 | #include <common.h> | |
12 | #include <dm.h> | |
644a3cd7 | 13 | #include <asm/io.h> |
47d7e3b5 | 14 | #include <asm/smp.h> |
61b29b82 | 15 | #include <linux/err.h> |
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16 | |
17 | /* MSIP registers */ | |
18 | #define MSIP_REG(base, hart) ((ulong)(base) + (hart) * 4) | |
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19 | |
20 | DECLARE_GLOBAL_DATA_PTR; | |
21 | ||
e5ca9a75 | 22 | int riscv_init_ipi(void) |
644a3cd7 | 23 | { |
e5ca9a75 SA |
24 | int ret; |
25 | struct udevice *dev; | |
26 | ||
27 | ret = uclass_get_device_by_driver(UCLASS_TIMER, | |
65e25bea | 28 | DM_DRIVER_GET(sifive_clint), &dev); |
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29 | if (ret) |
30 | return ret; | |
a0018fc8 | 31 | |
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32 | gd->arch.clint = dev_read_addr_ptr(dev); |
33 | if (!gd->arch.clint) | |
34 | return -EINVAL; | |
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35 | |
36 | return 0; | |
37 | } | |
38 | ||
e5ca9a75 | 39 | int riscv_send_ipi(int hart) |
644a3cd7 | 40 | { |
e5ca9a75 | 41 | writel(1, (void __iomem *)MSIP_REG(gd->arch.clint, hart)); |
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42 | |
43 | return 0; | |
44 | } | |
45 | ||
e5ca9a75 | 46 | int riscv_clear_ipi(int hart) |
644a3cd7 | 47 | { |
e5ca9a75 | 48 | writel(0, (void __iomem *)MSIP_REG(gd->arch.clint, hart)); |
40686c39 SA |
49 | |
50 | return 0; | |
51 | } | |
644a3cd7 | 52 | |
e5ca9a75 | 53 | int riscv_get_ipi(int hart, int *pending) |
40686c39 | 54 | { |
e5ca9a75 | 55 | *pending = readl((void __iomem *)MSIP_REG(gd->arch.clint, hart)); |
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56 | |
57 | return 0; | |
58 | } |