projects / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 02cd449f WG |
1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* | |
| 3 | * Copyright (C) 2020 MediaTek Inc. | |
| 4 | * | |
| 5 | * Author: Weijie Gao <[email protected]> | |
| 6 | */ | |
| 7 | ||
| 8 | #include <common.h> | |
| 9 | #include <clk.h> | |
| 10 | #include <dm.h> | |
| 11 | #include <dm/uclass.h> | |
| 12 | #include <dt-bindings/clock/mt7628-clk.h> | |
| 13 | #include <linux/io.h> | |
| 14 | #include "mt7628.h" | |
| 15 | ||
| 16 | DECLARE_GLOBAL_DATA_PTR; | |
| 17 | ||
| 18 | static void set_init_timer_freq(void) | |
| 19 | { | |
| 20 | void __iomem *sysc; | |
| 21 | u32 bs, val, timer_freq_post; | |
| 22 | ||
| 23 | sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE); | |
| 24 | ||
| 25 | /* We can't use the clk driver as the DM has not been initialized yet */ | |
| 26 | bs = readl(sysc + SYSCTL_SYSCFG0_REG); | |
| 27 | if ((bs & XTAL_FREQ_SEL) == XTAL_25MHZ) { | |
| 28 | gd->arch.timer_freq = 25000000; | |
| 29 | timer_freq_post = 575000000; | |
| 30 | } else { | |
| 31 | gd->arch.timer_freq = 40000000; | |
| 32 | timer_freq_post = 580000000; | |
| 33 | } | |
| 34 | ||
| 35 | val = readl(sysc + SYSCTL_CLKCFG0_REG); | |
| 36 | if (!(val & (CPU_PLL_FROM_BBP | CPU_PLL_FROM_XTAL))) | |
| 37 | gd->arch.timer_freq = timer_freq_post; | |
| 38 | } | |
| 39 | ||
| 40 | void mt7628_init(void) | |
| 41 | { | |
| 42 | set_init_timer_freq(); | |
| 43 | ||
| 44 | mt7628_ddr_init(); | |
| 45 | } | |
| 46 | ||
| 47 | int print_cpuinfo(void) | |
| 48 | { | |
| 49 | void __iomem *sysc; | |
| 50 | struct udevice *clkdev; | |
| 51 | u32 val, ver, eco, pkg, ddr, chipmode, ee; | |
| 52 | ulong cpu_clk, bus_clk, xtal_clk, timer_freq; | |
| 53 | struct clk clk; | |
| 54 | int ret; | |
| 55 | ||
| 56 | sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE); | |
| 57 | ||
| 58 | val = readl(sysc + SYSCTL_CHIP_REV_ID_REG); | |
| 59 | ver = (val & VER_M) >> VER_S; | |
| 60 | eco = (val & ECO_M) >> ECO_S; | |
| 61 | pkg = !!(val & PKG_ID); | |
| 62 | ||
| 63 | val = readl(sysc + SYSCTL_SYSCFG0_REG); | |
| 64 | ddr = val & DRAM_TYPE; | |
| 65 | chipmode = (val & CHIP_MODE_M) >> CHIP_MODE_S; | |
| 66 | ||
| 67 | val = readl(sysc + SYSCTL_EFUSE_CFG_REG); | |
| 68 | ee = val & EFUSE_MT7688; | |
| 69 | ||
| 70 | printf("CPU: MediaTek MT%u%c ver:%u eco:%u\n", | |
| 71 | ee ? 7688 : 7628, pkg ? 'A' : 'K', ver, eco); | |
| 72 | ||
| 73 | printf("Boot: DDR%s, SPI-NOR %u-Byte Addr, CPU clock from %s\n", | |
| 74 | ddr ? "" : "2", chipmode & 0x01 ? 4 : 3, | |
| 75 | chipmode & 0x02 ? "XTAL" : "CPLL"); | |
| 76 | ||
| 65e25bea | 77 | ret = uclass_get_device_by_driver(UCLASS_CLK, DM_DRIVER_GET(mt7628_clk), |
| 02cd449f WG |
78 | &clkdev); |
| 79 | if (ret) | |
| 80 | return ret; | |
| 81 | ||
| 82 | clk.dev = clkdev; | |
| 83 | ||
| 84 | clk.id = CLK_CPU; | |
| 85 | cpu_clk = clk_get_rate(&clk); | |
| 86 | ||
| 87 | clk.id = CLK_SYS; | |
| 88 | bus_clk = clk_get_rate(&clk); | |
| 89 | ||
| 90 | clk.id = CLK_XTAL; | |
| 91 | xtal_clk = clk_get_rate(&clk); | |
| 92 | ||
| 93 | clk.id = CLK_MIPS_CNT; | |
| 94 | timer_freq = clk_get_rate(&clk); | |
| 95 | ||
| 96 | /* Set final timer frequency */ | |
| 97 | if (timer_freq) | |
| 98 | gd->arch.timer_freq = timer_freq; | |
| 99 | ||
| 100 | printf("Clock: CPU: %luMHz, Bus: %luMHz, XTAL: %luMHz\n", | |
| 101 | cpu_clk / 1000000, bus_clk / 1000000, xtal_clk / 1000000); | |
| 102 | ||
| 103 | return 0; | |
| 104 | } | |
| 105 | ||
| 106 | ulong notrace get_tbclk(void) | |
| 107 | { | |
| 108 | return gd->arch.timer_freq; | |
| 109 | } |