projects / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| def2fc05 FP |
1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* | |
| 3 | * Copyright (C) 2018 MediaTek Inc. | |
| 4 | * Copyright (C) 2019 BayLibre, SAS | |
| 5 | * Author: Fabien Parent <[email protected]> | |
| 6 | */ | |
| 7 | ||
| 8 | #include <clk.h> | |
| 9 | #include <common.h> | |
| 9a3b4ceb | 10 | #include <cpu_func.h> |
| def2fc05 FP |
11 | #include <dm.h> |
| 12 | #include <fdtdec.h> | |
| 691d719d | 13 | #include <init.h> |
| def2fc05 FP |
14 | #include <ram.h> |
| 15 | #include <asm/arch/misc.h> | |
| 16 | #include <asm/armv8/mmu.h> | |
| 90526e9f | 17 | #include <asm/cache.h> |
| def2fc05 FP |
18 | #include <asm/sections.h> |
| 19 | #include <dm/uclass.h> | |
| def2fc05 FP |
20 | #include <dt-bindings/clock/mt8516-clk.h> |
| 21 | ||
| 22 | DECLARE_GLOBAL_DATA_PTR; | |
| 23 | ||
| def2fc05 FP |
24 | int dram_init(void) |
| 25 | { | |
| 26 | int ret; | |
| 27 | ||
| 28 | ret = fdtdec_setup_memory_banksize(); | |
| 29 | if (ret) | |
| 30 | return ret; | |
| 31 | ||
| 32 | return fdtdec_setup_mem_size_base(); | |
| 33 | } | |
| 34 | ||
| 35 | int dram_init_banksize(void) | |
| 36 | { | |
| 37 | gd->bd->bi_dram[0].start = gd->ram_base; | |
| 38 | gd->bd->bi_dram[0].size = gd->ram_size; | |
| 39 | ||
| 40 | return 0; | |
| 41 | } | |
| 42 | ||
| 43 | int mtk_pll_early_init(void) | |
| 44 | { | |
| 45 | unsigned long pll_rates[] = { | |
| 46 | [CLK_APMIXED_ARMPLL] = 1300000000, | |
| 47 | [CLK_APMIXED_MAINPLL] = 1501000000, | |
| 48 | [CLK_APMIXED_UNIVPLL] = 1248000000, | |
| 49 | [CLK_APMIXED_MMPLL] = 380000000, | |
| 50 | }; | |
| 51 | struct udevice *dev; | |
| 52 | int ret, i; | |
| 53 | ||
| 54 | ret = uclass_get_device_by_driver(UCLASS_CLK, | |
| 65e25bea | 55 | DM_DRIVER_GET(mtk_clk_apmixedsys), &dev); |
| def2fc05 FP |
56 | if (ret) |
| 57 | return ret; | |
| 58 | ||
| 59 | /* configure default rate then enable apmixedsys */ | |
| 60 | for (i = 0; i < ARRAY_SIZE(pll_rates); i++) { | |
| 61 | struct clk clk = { .id = i, .dev = dev }; | |
| 62 | ||
| 63 | ret = clk_set_rate(&clk, pll_rates[i]); | |
| 64 | if (ret) | |
| 65 | return ret; | |
| 66 | ||
| 67 | ret = clk_enable(&clk); | |
| 68 | if (ret) | |
| 69 | return ret; | |
| 70 | } | |
| 71 | ||
| 72 | return 0; | |
| 73 | } | |
| 74 | ||
| 75 | int mtk_soc_early_init(void) | |
| 76 | { | |
| 77 | int ret; | |
| 78 | ||
| 79 | /* initialize early clocks */ | |
| 80 | ret = mtk_pll_early_init(); | |
| 81 | if (ret) | |
| 82 | return ret; | |
| 83 | ||
| 84 | return 0; | |
| 85 | } | |
| 86 | ||
| 87 | void reset_cpu(ulong addr) | |
| 88 | { | |
| 47f30aaa | 89 | psci_system_reset(); |
| def2fc05 FP |
90 | } |
| 91 | ||
| 92 | int print_cpuinfo(void) | |
| 93 | { | |
| 94 | printf("CPU: MediaTek MT8516\n"); | |
| 95 | return 0; | |
| 96 | } | |
| 97 | ||
| 98 | static struct mm_region mt8516_mem_map[] = { | |
| 99 | { | |
| 100 | /* DDR */ | |
| 101 | .virt = 0x40000000UL, | |
| 102 | .phys = 0x40000000UL, | |
| 103 | .size = 0x20000000UL, | |
| 104 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, | |
| 105 | }, { | |
| 106 | .virt = 0x00000000UL, | |
| 107 | .phys = 0x00000000UL, | |
| 108 | .size = 0x20000000UL, | |
| 109 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
| 110 | PTE_BLOCK_NON_SHARE | | |
| 111 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
| 112 | }, { | |
| 113 | 0, | |
| 114 | } | |
| 115 | }; | |
| 116 | struct mm_region *mem_map = mt8516_mem_map; |