[u-boot.git] / drivers / clk / clk-uclass.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2015 Google, Inc
 * Written by Simon Glass <[email protected]>
 * Copyright (c) 2016, NVIDIA CORPORATION.
 * Copyright (c) 2018, Theobroma Systems Design und Consulting GmbH
 */

#include <common.h>
#include <clk.h>
#include <clk-uclass.h>
#include <dm.h>
#include <dm/read.h>
#include <dt-structs.h>
#include <errno.h>

static inline const struct clk_ops *clk_dev_ops(struct udevice *dev)
{
	return (const struct clk_ops *)dev->driver->ops;
}

#if CONFIG_IS_ENABLED(OF_CONTROL)
# if CONFIG_IS_ENABLED(OF_PLATDATA)
int clk_get_by_index_platdata(struct udevice *dev, int index,
			      struct phandle_1_arg *cells, struct clk *clk)
{
	int ret;

	if (index != 0)
		return -ENOSYS;
	ret = uclass_get_device(UCLASS_CLK, 0, &clk->dev);
	if (ret)
		return ret;
	clk->id = cells[0].arg[0];

	return 0;
}
# else
static int clk_of_xlate_default(struct clk *clk,
				struct ofnode_phandle_args *args)
{
	debug("%s(clk=%p)\n", __func__, clk);

	if (args->args_count > 1) {
		debug("Invaild args_count: %d\n", args->args_count);
		return -EINVAL;
	}

	if (args->args_count)
		clk->id = args->args[0];
	else
		clk->id = 0;

	return 0;
}

static int clk_get_by_indexed_prop(struct udevice *dev, const char *prop_name,
				   int index, struct clk *clk)
{
	int ret;
	struct ofnode_phandle_args args;
	struct udevice *dev_clk;
	const struct clk_ops *ops;

	debug("%s(dev=%p, index=%d, clk=%p)\n", __func__, dev, index, clk);

	assert(clk);
	clk->dev = NULL;

	ret = dev_read_phandle_with_args(dev, prop_name, "#clock-cells", 0,
					 index, &args);
	if (ret) {
		debug("%s: fdtdec_parse_phandle_with_args failed: err=%d\n",
		      __func__, ret);
		return ret;
	}

	ret = uclass_get_device_by_ofnode(UCLASS_CLK, args.node, &dev_clk);
	if (ret) {
		debug("%s: uclass_get_device_by_of_offset failed: err=%d\n",
		      __func__, ret);
		return ret;
	}

	clk->dev = dev_clk;

	ops = clk_dev_ops(dev_clk);

	if (ops->of_xlate)
		ret = ops->of_xlate(clk, &args);
	else
		ret = clk_of_xlate_default(clk, &args);
	if (ret) {
		debug("of_xlate() failed: %d\n", ret);
		return ret;
	}

	return clk_request(dev_clk, clk);
}

int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
{
	return clk_get_by_indexed_prop(dev, "clocks", index, clk);
}

int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk)
{
	int i, ret, err, count;
	
	bulk->count = 0;

	count = dev_count_phandle_with_args(dev, "clocks", "#clock-cells");
	if (count < 1)
		return count;

	bulk->clks = devm_kcalloc(dev, count, sizeof(struct clk), GFP_KERNEL);
	if (!bulk->clks)
		return -ENOMEM;

	for (i = 0; i < count; i++) {
		ret = clk_get_by_index(dev, i, &bulk->clks[i]);
		if (ret < 0)
			goto bulk_get_err;

		++bulk->count;
	}

	return 0;

bulk_get_err:
	err = clk_release_all(bulk->clks, bulk->count);
	if (err)
		debug("%s: could release all clocks for %p\n",
		      __func__, dev);

	return ret;
}

static int clk_set_default_parents(struct udevice *dev)
{
	struct clk clk, parent_clk;
	int index;
	int num_parents;
	int ret;

	num_parents = dev_count_phandle_with_args(dev, "assigned-clock-parents",
						  "#clock-cells");
	if (num_parents < 0) {
		debug("%s: could not read assigned-clock-parents for %p\n",
		      __func__, dev);
		return 0;
	}

	for (index = 0; index < num_parents; index++) {
		ret = clk_get_by_indexed_prop(dev, "assigned-clock-parents",
					      index, &parent_clk);
		/* If -ENOENT, this is a no-op entry */
		if (ret == -ENOENT)
			continue;

		if (ret) {
			debug("%s: could not get parent clock %d for %s\n",
			      __func__, index, dev_read_name(dev));
			return ret;
		}

		ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
					      index, &clk);
		if (ret) {
			debug("%s: could not get assigned clock %d for %s\n",
			      __func__, index, dev_read_name(dev));
			return ret;
		}

		ret = clk_set_parent(&clk, &parent_clk);

		/*
		 * Not all drivers may support clock-reparenting (as of now).
		 * Ignore errors due to this.
		 */
		if (ret == -ENOSYS)
			continue;

		if (ret) {
			debug("%s: failed to reparent clock %d for %s\n",
			      __func__, index, dev_read_name(dev));
			return ret;
		}
	}

	return 0;
}

static int clk_set_default_rates(struct udevice *dev)
{
	struct clk clk;
	int index;
	int num_rates;
	int size;
	int ret = 0;
	u32 *rates = NULL;

	size = dev_read_size(dev, "assigned-clock-rates");
	if (size < 0)
		return 0;

	num_rates = size / sizeof(u32);
	rates = calloc(num_rates, sizeof(u32));
	if (!rates)
		return -ENOMEM;

	ret = dev_read_u32_array(dev, "assigned-clock-rates", rates, num_rates);
	if (ret)
		goto fail;

	for (index = 0; index < num_rates; index++) {
		/* If 0 is passed, this is a no-op */
		if (!rates[index])
			continue;

		ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
					      index, &clk);
		if (ret) {
			debug("%s: could not get assigned clock %d for %s\n",
			      __func__, index, dev_read_name(dev));
			continue;
		}

		ret = clk_set_rate(&clk, rates[index]);
		if (ret < 0) {
			debug("%s: failed to set rate on clock %d for %s\n",
			      __func__, index, dev_read_name(dev));
			break;
		}
	}

fail:
	free(rates);
	return ret;
}

int clk_set_defaults(struct udevice *dev)
{
	int ret;

	/* If this is running pre-reloc state, don't take any action. */
	if (!(gd->flags & GD_FLG_RELOC))
		return 0;

	debug("%s(%s)\n", __func__, dev_read_name(dev));

	ret = clk_set_default_parents(dev);
	if (ret)
		return ret;

	ret = clk_set_default_rates(dev);
	if (ret < 0)
		return ret;

	return 0;
}
# endif /* OF_PLATDATA */

int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk)
{
	int index;

	debug("%s(dev=%p, name=%s, clk=%p)\n", __func__, dev, name, clk);
	clk->dev = NULL;

	index = dev_read_stringlist_search(dev, "clock-names", name);
	if (index < 0) {
		debug("fdt_stringlist_search() failed: %d\n", index);
		return index;
	}

	return clk_get_by_index(dev, index, clk);
}

int clk_release_all(struct clk *clk, int count)
{
	int i, ret;

	for (i = 0; i < count; i++) {
		debug("%s(clk[%d]=%p)\n", __func__, i, &clk[i]);

		/* check if clock has been previously requested */
		if (!clk[i].dev)
			continue;

		ret = clk_disable(&clk[i]);
		if (ret && ret != -ENOSYS)
			return ret;

		ret = clk_free(&clk[i]);
		if (ret && ret != -ENOSYS)
			return ret;
	}

	return 0;
}

#endif /* OF_CONTROL */

int clk_request(struct udevice *dev, struct clk *clk)
{
	const struct clk_ops *ops = clk_dev_ops(dev);

	debug("%s(dev=%p, clk=%p)\n", __func__, dev, clk);

	clk->dev = dev;

	if (!ops->request)
		return 0;

	return ops->request(clk);
}

int clk_free(struct clk *clk)
{
	const struct clk_ops *ops = clk_dev_ops(clk->dev);

	debug("%s(clk=%p)\n", __func__, clk);

	if (!ops->free)
		return 0;

	return ops->free(clk);
}

ulong clk_get_rate(struct clk *clk)
{
	const struct clk_ops *ops = clk_dev_ops(clk->dev);

	debug("%s(clk=%p)\n", __func__, clk);

	if (!ops->get_rate)
		return -ENOSYS;

	return ops->get_rate(clk);
}

ulong clk_set_rate(struct clk *clk, ulong rate)
{
	const struct clk_ops *ops = clk_dev_ops(clk->dev);

	debug("%s(clk=%p, rate=%lu)\n", __func__, clk, rate);

	if (!ops->set_rate)
		return -ENOSYS;

	return ops->set_rate(clk, rate);
}

int clk_set_parent(struct clk *clk, struct clk *parent)
{
	const struct clk_ops *ops = clk_dev_ops(clk->dev);

	debug("%s(clk=%p, parent=%p)\n", __func__, clk, parent);

	if (!ops->set_parent)
		return -ENOSYS;

	return ops->set_parent(clk, parent);
}

int clk_enable(struct clk *clk)
{
	const struct clk_ops *ops = clk_dev_ops(clk->dev);

	debug("%s(clk=%p)\n", __func__, clk);

	if (!ops->enable)
		return -ENOSYS;

	return ops->enable(clk);
}

int clk_enable_bulk(struct clk_bulk *bulk)
{
	int i, ret;

	for (i = 0; i < bulk->count; i++) {
		ret = clk_enable(&bulk->clks[i]);
		if (ret < 0 && ret != -ENOSYS)
			return ret;
	}

	return 0;
}

int clk_disable(struct clk *clk)
{
	const struct clk_ops *ops = clk_dev_ops(clk->dev);

	debug("%s(clk=%p)\n", __func__, clk);

	if (!ops->disable)
		return -ENOSYS;

	return ops->disable(clk);
}

int clk_disable_bulk(struct clk_bulk *bulk)
{
	int i, ret;

	for (i = 0; i < bulk->count; i++) {
		ret = clk_disable(&bulk->clks[i]);
		if (ret < 0 && ret != -ENOSYS)
			return ret;
	}

	return 0;
}

UCLASS_DRIVER(clk) = {
	.id		= UCLASS_CLK,
	.name		= "clk",
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
f26c8a8e SG	2	/*
	3	* Copyright (C) 2015 Google, Inc
	4	* Written by Simon Glass <[email protected]>
135aa950	5	* Copyright (c) 2016, NVIDIA CORPORATION.
f4fcba5c	6	* Copyright (c) 2018, Theobroma Systems Design und Consulting GmbH
f26c8a8e SG	7	*/
	8
	9	#include <common.h>
	10	#include <clk.h>
135aa950	11	#include <clk-uclass.h>
f26c8a8e	12	#include <dm.h>
f4fcba5c	13	#include <dm/read.h>
7423daa6	14	#include <dt-structs.h>
f26c8a8e	15	#include <errno.h>
f26c8a8e	16
268453be	17	static inline const struct clk_ops clk_dev_ops(struct udevice dev)
f26c8a8e	18	{
268453be	19	return (const struct clk_ops *)dev->driver->ops;
f26c8a8e SG	20	}
f26c8a8e SG	21
135aa950	22	#if CONFIG_IS_ENABLED(OF_CONTROL)
7423daa6 SG	23	# if CONFIG_IS_ENABLED(OF_PLATDATA)
7423daa6 SG	24	int clk_get_by_index_platdata(struct udevice *dev, int index,
0d15463c	25	struct phandle_1_arg cells, struct clk clk)
7423daa6 SG	26	{
	27	int ret;
	28
	29	if (index != 0)
	30	return -ENOSYS;
	31	ret = uclass_get_device(UCLASS_CLK, 0, &clk->dev);
	32	if (ret)
	33	return ret;
bc79617f	34	clk->id = cells[0].arg[0];
7423daa6 SG	35
	36	return 0;
	37	}
	38	# else
135aa950	39	static int clk_of_xlate_default(struct clk *clk,
a4e0ef50	40	struct ofnode_phandle_args *args)
f26c8a8e	41	{
135aa950	42	debug("%s(clk=%p)\n", __func__, clk);
f26c8a8e	43
135aa950 SW	44	if (args->args_count > 1) {
	45	debug("Invaild args_count: %d\n", args->args_count);
	46	return -EINVAL;
	47	}
f26c8a8e	48
135aa950 SW	49	if (args->args_count)
	50	clk->id = args->args[0];
	51	else
	52	clk->id = 0;
f26c8a8e	53
135aa950	54	return 0;
f26c8a8e SG	55	}
f26c8a8e SG	56
95f9a7e5 PT	57	static int clk_get_by_indexed_prop(struct udevice dev, const char prop_name,
95f9a7e5 PT	58	int index, struct clk *clk)
e70cc438	59	{
e70cc438	60	int ret;
aa9bb094	61	struct ofnode_phandle_args args;
135aa950	62	struct udevice *dev_clk;
268453be	63	const struct clk_ops *ops;
135aa950 SW	64
135aa950 SW	65	debug("%s(dev=%p, index=%d, clk=%p)\n", __func__, dev, index, clk);
e70cc438	66
135aa950	67	assert(clk);
82a8a669 PC	68	clk->dev = NULL;
82a8a669 PC	69
95f9a7e5	70	ret = dev_read_phandle_with_args(dev, prop_name, "#clock-cells", 0,
268453be	71	index, &args);
e70cc438 SG	72	if (ret) {
	73	debug("%s: fdtdec_parse_phandle_with_args failed: err=%d\n",
	74	__func__, ret);
	75	return ret;
	76	}
	77
aa9bb094	78	ret = uclass_get_device_by_ofnode(UCLASS_CLK, args.node, &dev_clk);
e70cc438 SG	79	if (ret) {
	80	debug("%s: uclass_get_device_by_of_offset failed: err=%d\n",
	81	__func__, ret);
	82	return ret;
	83	}
3f56b132 WY	84
	85	clk->dev = dev_clk;
	86
135aa950 SW	87	ops = clk_dev_ops(dev_clk);
	88
	89	if (ops->of_xlate)
aa9bb094	90	ret = ops->of_xlate(clk, &args);
135aa950	91	else
aa9bb094	92	ret = clk_of_xlate_default(clk, &args);
135aa950 SW	93	if (ret) {
	94	debug("of_xlate() failed: %d\n", ret);
	95	return ret;
	96	}
	97
	98	return clk_request(dev_clk, clk);
	99	}
95f9a7e5 PT	100
	101	int clk_get_by_index(struct udevice dev, int index, struct clk clk)
	102	{
	103	return clk_get_by_indexed_prop(dev, "clocks", index, clk);
	104	}
f4fcba5c	105
a855be87 NA	106	int clk_get_bulk(struct udevice dev, struct clk_bulk bulk)
	107	{
	108	int i, ret, err, count;
	109
	110	bulk->count = 0;
	111
	112	count = dev_count_phandle_with_args(dev, "clocks", "#clock-cells");
721881c4 NA	113	if (count < 1)
721881c4 NA	114	return count;
a855be87 NA	115
	116	bulk->clks = devm_kcalloc(dev, count, sizeof(struct clk), GFP_KERNEL);
	117	if (!bulk->clks)
	118	return -ENOMEM;
	119
	120	for (i = 0; i < count; i++) {
	121	ret = clk_get_by_index(dev, i, &bulk->clks[i]);
	122	if (ret < 0)
	123	goto bulk_get_err;
	124
	125	++bulk->count;
	126	}
	127
	128	return 0;
	129
	130	bulk_get_err:
	131	err = clk_release_all(bulk->clks, bulk->count);
	132	if (err)
	133	debug("%s: could release all clocks for %p\n",
	134	__func__, dev);
	135
	136	return ret;
	137	}
	138
f4fcba5c PT	139	static int clk_set_default_parents(struct udevice *dev)
	140	{
	141	struct clk clk, parent_clk;
	142	int index;
	143	int num_parents;
	144	int ret;
	145
	146	num_parents = dev_count_phandle_with_args(dev, "assigned-clock-parents",
	147	"#clock-cells");
	148	if (num_parents < 0) {
	149	debug("%s: could not read assigned-clock-parents for %p\n",
	150	__func__, dev);
	151	return 0;
	152	}
	153
	154	for (index = 0; index < num_parents; index++) {
	155	ret = clk_get_by_indexed_prop(dev, "assigned-clock-parents",
	156	index, &parent_clk);
d64caaf7 NA	157	/* If -ENOENT, this is a no-op entry */
	158	if (ret == -ENOENT)
	159	continue;
	160
f4fcba5c PT	161	if (ret) {
	162	debug("%s: could not get parent clock %d for %s\n",
	163	__func__, index, dev_read_name(dev));
	164	return ret;
	165	}
	166
	167	ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
	168	index, &clk);
	169	if (ret) {
	170	debug("%s: could not get assigned clock %d for %s\n",
	171	__func__, index, dev_read_name(dev));
	172	return ret;
	173	}
	174
	175	ret = clk_set_parent(&clk, &parent_clk);
	176
	177	/*
	178	* Not all drivers may support clock-reparenting (as of now).
	179	* Ignore errors due to this.
	180	*/
	181	if (ret == -ENOSYS)
	182	continue;
	183
	184	if (ret) {
	185	debug("%s: failed to reparent clock %d for %s\n",
	186	__func__, index, dev_read_name(dev));
	187	return ret;
	188	}
	189	}
	190
	191	return 0;
	192	}
	193
	194	static int clk_set_default_rates(struct udevice *dev)
	195	{
	196	struct clk clk;
	197	int index;
	198	int num_rates;
	199	int size;
	200	int ret = 0;
	201	u32 *rates = NULL;
	202
	203	size = dev_read_size(dev, "assigned-clock-rates");
	204	if (size < 0)
	205	return 0;
	206
	207	num_rates = size / sizeof(u32);
	208	rates = calloc(num_rates, sizeof(u32));
	209	if (!rates)
	210	return -ENOMEM;
	211
	212	ret = dev_read_u32_array(dev, "assigned-clock-rates", rates, num_rates);
	213	if (ret)
	214	goto fail;
	215
	216	for (index = 0; index < num_rates; index++) {
d64caaf7 NA	217	/* If 0 is passed, this is a no-op */
	218	if (!rates[index])
	219	continue;
	220
f4fcba5c PT	221	ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
	222	index, &clk);
	223	if (ret) {
	224	debug("%s: could not get assigned clock %d for %s\n",
	225	__func__, index, dev_read_name(dev));
	226	continue;
	227	}
	228
	229	ret = clk_set_rate(&clk, rates[index]);
	230	if (ret < 0) {
	231	debug("%s: failed to set rate on clock %d for %s\n",
	232	__func__, index, dev_read_name(dev));
	233	break;
	234	}
	235	}
	236
	237	fail:
	238	free(rates);
	239	return ret;
	240	}
	241
	242	int clk_set_defaults(struct udevice *dev)
	243	{
	244	int ret;
	245
	246	/* If this is running pre-reloc state, don't take any action. */
	247	if (!(gd->flags & GD_FLG_RELOC))
	248	return 0;
	249
	250	debug("%s(%s)\n", __func__, dev_read_name(dev));
	251
	252	ret = clk_set_default_parents(dev);
	253	if (ret)
	254	return ret;
	255
	256	ret = clk_set_default_rates(dev);
	257	if (ret < 0)
	258	return ret;
	259
	260	return 0;
	261	}
9e0758b7	262	# endif /* OF_PLATDATA */
135aa950 SW	263
	264	int clk_get_by_name(struct udevice dev, const char name, struct clk *clk)
	265	{
	266	int index;
	267
	268	debug("%s(dev=%p, name=%s, clk=%p)\n", __func__, dev, name, clk);
82a8a669	269	clk->dev = NULL;
135aa950	270
aa9bb094	271	index = dev_read_stringlist_search(dev, "clock-names", name);
135aa950	272	if (index < 0) {
b02e4044	273	debug("fdt_stringlist_search() failed: %d\n", index);
135aa950 SW	274	return index;
	275	}
	276
	277	return clk_get_by_index(dev, index, clk);
e70cc438	278	}
b108d8a0 PC	279
	280	int clk_release_all(struct clk *clk, int count)
	281	{
	282	int i, ret;
	283
	284	for (i = 0; i < count; i++) {
	285	debug("%s(clk[%d]=%p)\n", __func__, i, &clk[i]);
	286
	287	/* check if clock has been previously requested */
	288	if (!clk[i].dev)
	289	continue;
	290
	291	ret = clk_disable(&clk[i]);
	292	if (ret && ret != -ENOSYS)
	293	return ret;
	294
	295	ret = clk_free(&clk[i]);
	296	if (ret && ret != -ENOSYS)
	297	return ret;
	298	}
	299
	300	return 0;
	301	}
	302
7423daa6	303	#endif /* OF_CONTROL */
135aa950 SW	304
	305	int clk_request(struct udevice dev, struct clk clk)
	306	{
268453be	307	const struct clk_ops *ops = clk_dev_ops(dev);
135aa950 SW	308
	309	debug("%s(dev=%p, clk=%p)\n", __func__, dev, clk);
	310
	311	clk->dev = dev;
	312
	313	if (!ops->request)
	314	return 0;
	315
	316	return ops->request(clk);
	317	}
	318
	319	int clk_free(struct clk *clk)
	320	{
268453be	321	const struct clk_ops *ops = clk_dev_ops(clk->dev);
135aa950 SW	322
	323	debug("%s(clk=%p)\n", __func__, clk);
	324
	325	if (!ops->free)
	326	return 0;
	327
	328	return ops->free(clk);
	329	}
	330
	331	ulong clk_get_rate(struct clk *clk)
	332	{
268453be	333	const struct clk_ops *ops = clk_dev_ops(clk->dev);
135aa950 SW	334
	335	debug("%s(clk=%p)\n", __func__, clk);
	336
	337	if (!ops->get_rate)
	338	return -ENOSYS;
	339
	340	return ops->get_rate(clk);
	341	}
	342
	343	ulong clk_set_rate(struct clk *clk, ulong rate)
	344	{
268453be	345	const struct clk_ops *ops = clk_dev_ops(clk->dev);
135aa950 SW	346
	347	debug("%s(clk=%p, rate=%lu)\n", __func__, clk, rate);
	348
	349	if (!ops->set_rate)
	350	return -ENOSYS;
	351
	352	return ops->set_rate(clk, rate);
	353	}
	354
f7d1046d PT	355	int clk_set_parent(struct clk clk, struct clk parent)
	356	{
	357	const struct clk_ops *ops = clk_dev_ops(clk->dev);
	358
	359	debug("%s(clk=%p, parent=%p)\n", __func__, clk, parent);
	360
	361	if (!ops->set_parent)
	362	return -ENOSYS;
	363
	364	return ops->set_parent(clk, parent);
	365	}
	366
135aa950 SW	367	int clk_enable(struct clk *clk)
135aa950 SW	368	{
268453be	369	const struct clk_ops *ops = clk_dev_ops(clk->dev);
135aa950 SW	370
	371	debug("%s(clk=%p)\n", __func__, clk);
	372
	373	if (!ops->enable)
	374	return -ENOSYS;
	375
	376	return ops->enable(clk);
	377	}
	378
a855be87 NA	379	int clk_enable_bulk(struct clk_bulk *bulk)
	380	{
	381	int i, ret;
	382
	383	for (i = 0; i < bulk->count; i++) {
	384	ret = clk_enable(&bulk->clks[i]);
	385	if (ret < 0 && ret != -ENOSYS)
	386	return ret;
	387	}
	388
	389	return 0;
	390	}
	391
135aa950 SW	392	int clk_disable(struct clk *clk)
135aa950 SW	393	{
268453be	394	const struct clk_ops *ops = clk_dev_ops(clk->dev);
135aa950 SW	395
	396	debug("%s(clk=%p)\n", __func__, clk);
	397
	398	if (!ops->disable)
	399	return -ENOSYS;
	400
	401	return ops->disable(clk);
	402	}
e70cc438	403
a855be87 NA	404	int clk_disable_bulk(struct clk_bulk *bulk)
	405	{
	406	int i, ret;
	407
	408	for (i = 0; i < bulk->count; i++) {
	409	ret = clk_disable(&bulk->clks[i]);
	410	if (ret < 0 && ret != -ENOSYS)
	411	return ret;
	412	}
	413
	414	return 0;
	415	}
	416
f26c8a8e SG	417	UCLASS_DRIVER(clk) = {
	418	.id = UCLASS_CLK,
	419	.name = "clk",
	420	};