[u-boot.git] / include / configs / IVMS8.h

/*
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, [email protected].
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC860		1	/* This is a MPC860 CPU		*/
#define CONFIG_IVMS8		1	/* ...on a IVMS8 board		*/

#if defined (CONFIG_IVMS8_16M)
# define CONFIG_IDENT_STRING     " IVMS8"
#elif defined (CONFIG_IVMS8_32M)
# define CONFIG_IDENT_STRING     " IVMS8_128"
#elif defined (CONFIG_IVMS8_64M)
# define CONFIG_IDENT_STRING     " IVMS8_256"
#endif

#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
#undef	CONFIG_8xx_CONS_SMC2
#undef	CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE		115200

#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
#define CONFIG_8xx_GCLK_FREQ    50331648

#define	CONFIG_SHOW_BOOT_PROGRESS 1	/* Show boot progress on LEDs	*/

#if 0
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
#else
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
#endif
#define CONFIG_BOOTCOMMAND	"bootp" /* autoboot command		*/

#define CONFIG_BOOTARGS		"root=/dev/nfs rw "			\
				"nfsroot=10.0.0.2:/opt/eldk/ppc_8xx "	\
				"nfsaddrs=10.0.0.99:10.0.0.2"

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_IDE


#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION

#define CONFIG_BOOTP_MASK \
    ((CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) & ~CONFIG_BOOTP_GATEWAY)

/*
 * Miscellaneous configurable options
 */
#define	CFG_LONGHELP			/* undef to save memory		*/
#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define	CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x00100000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x00F00000	/* 1 ... 15MB in DRAM	*/

#define	CFG_LOAD_ADDR		0x00100000	/* default load address	*/

#define	CFG_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/

#define CFG_PB_SDRAM_CLKE	0x00008000		/* PB 16	*/
#define CFG_PB_ETH_POWERDOWN	0x00010000		/* PB 15	*/
#define CFG_PB_IDE_MOTOR	0x00020000		/* PB 14	*/

#define CFG_PC_ETH_RESET	((ushort)0x0010)	/* PC 11	*/
#define CFG_PC_IDE_RESET	((ushort)0x0020)	/* PC 10	*/

#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/

#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CFG_IMMR		0xFFF00000 /* was: 0xFF000000 */

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CFG_INIT_RAM_ADDR	CFG_IMMR
#if defined (CONFIG_IVMS8_16M)
# define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
#elif defined (CONFIG_IVMS8_32M)
# define	CFG_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
#elif defined (CONFIG_IVMS8_64M)
# define	CFG_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
#endif

#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define	CFG_SDRAM_BASE		0x00000000
#define CFG_FLASH_BASE		0xFF000000
#ifdef	DEBUG
#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#else
#define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
#endif
#define CFG_MONITOR_BASE	CFG_FLASH_BASE
#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define	CFG_ENV_IS_IN_FLASH	1
#define	CFG_ENV_OFFSET		0x7A000	/*   Offset   of Environment Sector	*/
#define	CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
# if defined (CONFIG_IVMS8_16M)
#   define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#  elif defined (CONFIG_IVMS8_32M)
#   define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWP)
#  elif defined (CONFIG_IVMS8_64M)
#   define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWP)
#  endif
#else
# define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
/* EARB, DBGC and DBPC are initialised by the HCW */
/* => 0x000000C0 */
#define CFG_SIUMCR	(SIUMCR_BSC | SIUMCR_GB5E)

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CFG_PISCR	(PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit, set PLL multiplication factor !
 */
/* 0x00B0C0C0 */
#define CFG_PLPRCR							\
		(	(11 << PLPRCR_MF_SHIFT) |			\
			PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/	\
			/*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL |		\
			PLPRCR_CSR   | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/	\
		)

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF11
/* 0x01800014 */
#define CFG_SCCR	(SCCR_COM01	| /*SCCR_TBS|*/		\
			 SCCR_RTDIV	|   SCCR_RTSEL	  |	\
			 /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/ 	\
			 SCCR_EBDF00	|   SCCR_DFSYNC00 |	\
			 SCCR_DFBRG00	|   SCCR_DFNL000  |	\
			 SCCR_DFNH000	|   SCCR_DFLCD101 |	\
			 SCCR_DFALCD00)

/*-----------------------------------------------------------------------
 * RTCSC - Real-Time Clock Status and Control Register		11-27
 *-----------------------------------------------------------------------
 */
/* 0x00C3 */
#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)


/*-----------------------------------------------------------------------
 * RCCR - RISC Controller Configuration Register		19-4
 *-----------------------------------------------------------------------
 */
/* TIMEP=2 */
#define CFG_RCCR 0x0200

/*-----------------------------------------------------------------------
 * RMDS - RISC Microcode Development Support Control Register
 *-----------------------------------------------------------------------
 */
#define CFG_RMDS 0

/*-----------------------------------------------------------------------
 *
 * Interrupt Levels
 *-----------------------------------------------------------------------
 */
#define CFG_CPM_INTERRUPT	13	/* SIU_LEVEL6	*/

/*-----------------------------------------------------------------------
 * PCMCIA stuff
 *-----------------------------------------------------------------------
 *
 */
#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )

/*-----------------------------------------------------------------------
 * IDE/ATA stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_IDE_8xx_DIRECT	1	/* PCMCIA interface required	*/
#define CONFIG_IDE_RESET	1	/* reset for ide supported	*/

#define CFG_IDE_MAXBUS		1	/* The IVMS8 has only 1 IDE bus	*/
#define CFG_IDE_MAXDEVICE	1	/*    ... and only 1 IDE device	*/

#define CFG_ATA_BASE_ADDR	0xFE100000
#define CFG_ATA_IDE0_OFFSET	0x0000
#undef	CFG_ATA_IDE1_OFFSET		/* only one IDE bus available	*/

#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
#define CFG_ATA_REG_OFFSET	0x0080	/* Offset for normal register accesses	*/
#define CFG_ATA_ALT_OFFSET	0x0100	/* Offset for alternate registers	*/

/*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
#define CFG_DER	0

/*
 * Init Memory Controller:
 *
 * BR0 and OR0 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0xFF000000	/* FLASH bank #0	*/

/* used to re-map FLASH both when starting from SRAM or FLASH:
 * restrict access enough to keep SRAM working (if any)
 * but not too much to meddle with FLASH accesses
 */
/* EPROMs are 512kb */
#define CFG_REMAP_OR_AM		0xFFF80000	/* OR addr mask */
#define CFG_PRELIM_OR_AM	0xFFF80000	/* OR addr mask */

/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
#define CFG_OR_TIMING_FLASH	(/* OR_CSNT_SAM | */ OR_ACS_DIV4 | OR_BI | \
				 OR_SCY_5_CLK | OR_EHTR)

#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
/* 16 bit, bank valid */
#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )

/*
 * BR1/OR1 - ELIC SACCO bank  @ 0xFE000000
 *
 * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1
 */
#define ELIC_SACCO_BASE		0xFE000000
#define ELIC_SACCO_OR_AM	0xFFFF8000
#define ELIC_SACCO_TIMING	0x00000F26

#define CFG_OR1	(ELIC_SACCO_OR_AM | ELIC_SACCO_TIMING)
#define CFG_BR1	((ELIC_SACCO_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )

/*
 * BR2/OR2 - ELIC EPIC bank   @ 0xFE008000
 *
 * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1
 */
#define ELIC_EPIC_BASE		0xFE008000
#define ELIC_EPIC_OR_AM		0xFFFF8000
#define ELIC_EPIC_TIMING	0x00000F26

#define CFG_OR2 (ELIC_EPIC_OR_AM | ELIC_EPIC_TIMING)
#define CFG_BR2	((ELIC_EPIC_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )

/*
 * BR3/OR3: SDRAM
 *
 * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
 */
#define SDRAM_BASE3_PRELIM	0x00000000	/* SDRAM bank */
#define SDRAM_PRELIM_OR_AM	0xF8000000	/* map max. 128 MB */
#define SDRAM_TIMING		0x00000A00	/* SDRAM-Timing */

#define SDRAM_MAX_SIZE		0x04000000	/* max 64 MB SDRAM */

#define CFG_OR3_PRELIM	(SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V )

/*
 * BR4/OR4: not used
 */

/*
 * BR5/OR5: SHARC ADSP-2165L
 *
 * AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0
 */
#define SHARC_BASE		0xFE400000
#define SHARC_OR_AM		0xFFC00000
#define SHARC_TIMING		0x00000700

#define CFG_OR5	(SHARC_OR_AM | SHARC_TIMING )
#define CFG_BR5	((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V )

/*
 * Memory Periodic Timer Prescaler
 */

/* periodic timer for refresh */
#define CFG_MBMR_PTB	204

/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/

/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
#if defined (CONFIG_IVMS8_16M)
 #define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
#elif defined (CONFIG_IVMS8_32M)
#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
#elif defined (CONFIG_IVMS8_64M)
#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV8		/* setting for 1 bank	*/
#endif


/*
 * MBMR settings for SDRAM
 */

#if defined (CONFIG_IVMS8_16M)
 /* 8 column SDRAM */
# define CFG_MBMR_8COL	((CFG_MBMR_PTB << MBMR_PTB_SHIFT)  | \
 			 MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 |	\
 			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)
#elif defined (CONFIG_IVMS8_32M)
/* 128 MBit SDRAM */
#define CFG_MBMR_8COL	((CFG_MBMR_PTB << MBMR_PTB_SHIFT)  | \
			 MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 |	\
			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)
#elif defined (CONFIG_IVMS8_64M)
/* 128 MBit SDRAM */
#define CFG_MBMR_8COL	((CFG_MBMR_PTB << MBMR_PTB_SHIFT)  | \
			 MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 |	\
			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)

#endif

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

#endif	/* __CONFIG_H */
Commit	Line	Data
0f8c9768 WD	1	/*
	2	* (C) Copyright 2000
	3	* Wolfgang Denk, DENX Software Engineering, [email protected].
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* board/config.h - configuration options, board specific
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/*
	32	* High Level Configuration Options
	33	* (easy to change)
	34	*/
	35
	36	#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
	37	#define CONFIG_IVMS8 1 /* ...on a IVMS8 board */
	38
	39	#if defined (CONFIG_IVMS8_16M)
	40	# define CONFIG_IDENT_STRING " IVMS8"
	41	#elif defined (CONFIG_IVMS8_32M)
	42	# define CONFIG_IDENT_STRING " IVMS8_128"
	43	#elif defined (CONFIG_IVMS8_64M)
	44	# define CONFIG_IDENT_STRING " IVMS8_256"
	45	#endif
	46
	47	#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
	48	#undef CONFIG_8xx_CONS_SMC2
	49	#undef CONFIG_8xx_CONS_NONE
	50	#define CONFIG_BAUDRATE 115200
	51
	52	#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
	53	#define CONFIG_8xx_GCLK_FREQ 50331648
	54
	55	#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */
	56
	57	#if 0
	58	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
	59	#else
	60	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	61	#endif
	62	#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
	63
	64	#define CONFIG_BOOTARGS "root=/dev/nfs rw " \
65	"nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \
66	"nfsaddrs=10.0.0.99:10.0.0.2"
67
68	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
69	#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
70
71	#undef CONFIG_WATCHDOG /* watchdog disabled */
72
73	#define CONFIG_STATUS_LED 1 /* Status LED enabled */
74
348f258f JL	75	/*
	76	* Command line configuration.
	77	*/
	78	#include <config_cmd_default.h>
	79
	80	#define CONFIG_CMD_IDE
	81
	82
0f8c9768 WD	83	#define CONFIG_MAC_PARTITION
	84	#define CONFIG_DOS_PARTITION
	85
	86	#define CONFIG_BOOTP_MASK \
	87	((CONFIG_BOOTP_DEFAULT \| CONFIG_BOOTP_BOOTFILESIZE) & ~CONFIG_BOOTP_GATEWAY)
	88
0f8c9768 WD	89	/*
	90	* Miscellaneous configurable options
	91	*/
	92	#define CFG_LONGHELP /* undef to save memory */
	93	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
348f258f	94	#if defined(CONFIG_CMD_KGDB)
0f8c9768 WD	95	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	96	#else
	97	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	98	#endif
	99	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	100	#define CFG_MAXARGS 16 /* max number of command args */
	101	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	102
	103	#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
	104	#define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
	105
	106	#define CFG_LOAD_ADDR 0x00100000 /* default load address */
	107
	108	#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
	109
	110	#define CFG_PB_SDRAM_CLKE 0x00008000 /* PB 16 */
	111	#define CFG_PB_ETH_POWERDOWN 0x00010000 /* PB 15 */
	112	#define CFG_PB_IDE_MOTOR 0x00020000 /* PB 14 */
	113
	114	#define CFG_PC_ETH_RESET ((ushort)0x0010) /* PC 11 */
	115	#define CFG_PC_IDE_RESET ((ushort)0x0020) /* PC 10 */
	116
	117	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	118
	119	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	120
	121	/*
	122	* Low Level Configuration Settings
	123	* (address mappings, register initial values, etc.)
	124	* You should know what you are doing if you make changes here.
	125	*/
	126	/*-----------------------------------------------------------------------
	127	* Internal Memory Mapped Register
	128	*/
	129	#define CFG_IMMR 0xFFF00000 /* was: 0xFF000000 */
	130
	131	/*-----------------------------------------------------------------------
	132	* Definitions for initial stack pointer and data area (in DPRAM)
	133	*/
	134	#define CFG_INIT_RAM_ADDR CFG_IMMR
	135	#if defined (CONFIG_IVMS8_16M)
	136	# define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
	137	#elif defined (CONFIG_IVMS8_32M)
	138	# define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */
	139	#elif defined (CONFIG_IVMS8_64M)
	140	# define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */
	141	#endif
	142
	143	#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
	144	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	145	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	146
	147	/*-----------------------------------------------------------------------
	148	* Start addresses for the final memory configuration
	149	* (Set up by the startup code)
	150	* Please note that CFG_SDRAM_BASE _must_ start at 0
	151	*/
	152	#define CFG_SDRAM_BASE 0x00000000
	153	#define CFG_FLASH_BASE 0xFF000000
	154	#ifdef DEBUG
	155	#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	156	#else
	157	#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
	158	#endif
159	#define CFG_MONITOR_BASE CFG_FLASH_BASE
160	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
161
162	/*
163	* For booting Linux, the board info and command line data
164	* have to be in the first 8 MB of memory, since this is
165	* the maximum mapped by the Linux kernel during initialization.
166	*/
167	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
168	/*-----------------------------------------------------------------------
169	* FLASH organization
170	*/
171	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
172	#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
173
174	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
175	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
176
177	#define CFG_ENV_IS_IN_FLASH 1
178	#define CFG_ENV_OFFSET 0x7A000 /* Offset of Environment Sector */
179	#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
180	/*-----------------------------------------------------------------------
181	* Cache Configuration
182	*/
183	#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
348f258f	184	#if defined(CONFIG_CMD_KGDB)
0f8c9768 WD	185	#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
	186	#endif
	187
	188	/*-----------------------------------------------------------------------
	189	* SYPCR - System Protection Control 11-9
	190	* SYPCR can only be written once after reset!
	191	*-----------------------------------------------------------------------
	192	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	193	*/
	194	#if defined(CONFIG_WATCHDOG)
	195	# if defined (CONFIG_IVMS8_16M)
	196	# define CFG_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
	197	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
	198	# elif defined (CONFIG_IVMS8_32M)
	199	# define CFG_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
	200	SYPCR_SWE \| SYPCR_SWP)
	201	# elif defined (CONFIG_IVMS8_64M)
	202	# define CFG_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
	203	SYPCR_SWE \| SYPCR_SWP)
	204	# endif
	205	#else
	206	# define CFG_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| SYPCR_SWP)
	207	#endif
	208
	209	/*-----------------------------------------------------------------------
	210	* SIUMCR - SIU Module Configuration 11-6
	211	*-----------------------------------------------------------------------
	212	* PCMCIA config., multi-function pin tri-state
	213	*/
	214	/* EARB, DBGC and DBPC are initialised by the HCW */
	215	/* => 0x000000C0 */
	216	#define CFG_SIUMCR (SIUMCR_BSC \| SIUMCR_GB5E)
	217
	218	/*-----------------------------------------------------------------------
	219	* TBSCR - Time Base Status and Control 11-26
	220	*-----------------------------------------------------------------------
	221	* Clear Reference Interrupt Status, Timebase freezing enabled
	222	*/
	223	#define CFG_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBF)
	224
	225	/*-----------------------------------------------------------------------
	226	* PISCR - Periodic Interrupt Status and Control 11-31
	227	*-----------------------------------------------------------------------
	228	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	229	*/
	230	#define CFG_PISCR (PISCR_PS \| PISCR_PITF)
	231
	232	/*-----------------------------------------------------------------------
	233	* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
	234	*-----------------------------------------------------------------------
	235	* Reset PLL lock status sticky bit, timer expired status bit and timer
	236	* interrupt status bit, set PLL multiplication factor !
	237	*/
	238	/* 0x00B0C0C0 */
	239	#define CFG_PLPRCR \
	240	( (11 << PLPRCR_MF_SHIFT) \| \
	241	PLPRCR_SPLSS \| PLPRCR_TEXPS \| /PLPRCR_TMIST\|/ \
	242	/PLPRCR_CSRC\|/ PLPRCR_LPM_NORMAL \| \
	243	PLPRCR_CSR \| PLPRCR_LOLRE /\|PLPRCR_FIOPD/ \
	244	)
	245
	246	/*-----------------------------------------------------------------------
	247	* SCCR - System Clock and reset Control Register 15-27
	248	*-----------------------------------------------------------------------
249	* Set clock output, timebase and RTC source and divider,
250	* power management and some other internal clocks
251	*/
252	#define SCCR_MASK SCCR_EBDF11
253	/* 0x01800014 */
254	#define CFG_SCCR (SCCR_COM01 \| /SCCR_TBS\|/ \
255	SCCR_RTDIV \| SCCR_RTSEL \| \
256	/SCCR_CRQEN\|/ /SCCR_PRQEN\|/ \
257	SCCR_EBDF00 \| SCCR_DFSYNC00 \| \
258	SCCR_DFBRG00 \| SCCR_DFNL000 \| \
259	SCCR_DFNH000 \| SCCR_DFLCD101 \| \
260	SCCR_DFALCD00)
261
262	/*-----------------------------------------------------------------------
263	* RTCSC - Real-Time Clock Status and Control Register 11-27
264	*-----------------------------------------------------------------------
265	*/
266	/* 0x00C3 */
267	#define CFG_RTCSC (RTCSC_SEC \| RTCSC_ALR \| RTCSC_RTF\| RTCSC_RTE)
268
269
270	/*-----------------------------------------------------------------------
271	* RCCR - RISC Controller Configuration Register 19-4
272	*-----------------------------------------------------------------------
273	*/
274	/* TIMEP=2 */
275	#define CFG_RCCR 0x0200
276
277	/*-----------------------------------------------------------------------
278	* RMDS - RISC Microcode Development Support Control Register
279	*-----------------------------------------------------------------------
280	*/
281	#define CFG_RMDS 0
282
283	/*-----------------------------------------------------------------------
284	*
285	* Interrupt Levels
286	*-----------------------------------------------------------------------
287	*/
288	#define CFG_CPM_INTERRUPT 13 /* SIU_LEVEL6 */
289
290	/*-----------------------------------------------------------------------
291	* PCMCIA stuff
292	*-----------------------------------------------------------------------
293	*
294	*/
295	#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
296	#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
297	#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
298	#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
299	#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
300	#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
301	#define CFG_PCMCIA_IO_ADDR (0xEC000000)
302	#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
303
304	/*-----------------------------------------------------------------------
305	* IDE/ATA stuff
306	*-----------------------------------------------------------------------
307	*/
308	#define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */
309	#define CONFIG_IDE_RESET 1 /* reset for ide supported */
310
311	#define CFG_IDE_MAXBUS 1 /* The IVMS8 has only 1 IDE bus */
312	#define CFG_IDE_MAXDEVICE 1 /* ... and only 1 IDE device */
313
314	#define CFG_ATA_BASE_ADDR 0xFE100000
315	#define CFG_ATA_IDE0_OFFSET 0x0000
316	#undef CFG_ATA_IDE1_OFFSET /* only one IDE bus available */
317
318	#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
319	#define CFG_ATA_REG_OFFSET 0x0080 /* Offset for normal register accesses */
320	#define CFG_ATA_ALT_OFFSET 0x0100 /* Offset for alternate registers */
321
322	/*-----------------------------------------------------------------------
323	*
324	*-----------------------------------------------------------------------
325	*
326	*/
0f8c9768 WD	327	#define CFG_DER 0
	328
	329	/*
	330	* Init Memory Controller:
	331	*
	332	* BR0 and OR0 (FLASH)
	333	*/
	334
	335	#define FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank #0 */
	336
	337	/* used to re-map FLASH both when starting from SRAM or FLASH:
	338	* restrict access enough to keep SRAM working (if any)
	339	* but not too much to meddle with FLASH accesses
	340	*/
	341	/* EPROMs are 512kb */
	342	#define CFG_REMAP_OR_AM 0xFFF80000 /* OR addr mask */
	343	#define CFG_PRELIM_OR_AM 0xFFF80000 /* OR addr mask */
	344
	345	/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
	346	#define CFG_OR_TIMING_FLASH (/* OR_CSNT_SAM \| */ OR_ACS_DIV4 \| OR_BI \| \
	347	OR_SCY_5_CLK \| OR_EHTR)
	348
	349	#define CFG_OR0_REMAP (CFG_REMAP_OR_AM \| CFG_OR_TIMING_FLASH)
	350	#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM \| CFG_OR_TIMING_FLASH)
	351	/* 16 bit, bank valid */
	352	#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) \| BR_PS_16 \| BR_V )
	353
	354	/*
	355	* BR1/OR1 - ELIC SACCO bank @ 0xFE000000
	356	*
	357	* AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1
	358	*/
	359	#define ELIC_SACCO_BASE 0xFE000000
	360	#define ELIC_SACCO_OR_AM 0xFFFF8000
	361	#define ELIC_SACCO_TIMING 0x00000F26
	362
	363	#define CFG_OR1 (ELIC_SACCO_OR_AM \| ELIC_SACCO_TIMING)
	364	#define CFG_BR1 ((ELIC_SACCO_BASE & BR_BA_MSK) \| BR_PS_8 \| BR_V )
	365
	366	/*
	367	* BR2/OR2 - ELIC EPIC bank @ 0xFE008000
	368	*
	369	* AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1
	370	*/
	371	#define ELIC_EPIC_BASE 0xFE008000
	372	#define ELIC_EPIC_OR_AM 0xFFFF8000
	373	#define ELIC_EPIC_TIMING 0x00000F26
	374
	375	#define CFG_OR2 (ELIC_EPIC_OR_AM \| ELIC_EPIC_TIMING)
	376	#define CFG_BR2 ((ELIC_EPIC_BASE & BR_BA_MSK) \| BR_PS_8 \| BR_V )
	377
	378	/*
	379	* BR3/OR3: SDRAM
	380	*
	381	* Multiplexed addresses, GPL5 output to GPL5_A (don't care)
	382	*/
	383	#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */
	384	#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */
	385	#define SDRAM_TIMING 0x00000A00 /* SDRAM-Timing */
	386
	387	#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */
	388
	389	#define CFG_OR3_PRELIM (SDRAM_PRELIM_OR_AM \| SDRAM_TIMING )
	390	#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) \| BR_MS_UPMB \| BR_V )
391
392	/*
393	* BR4/OR4: not used
394	*/
395
396	/*
397	* BR5/OR5: SHARC ADSP-2165L
398	*
399	* AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0
400	*/
401	#define SHARC_BASE 0xFE400000
402	#define SHARC_OR_AM 0xFFC00000
403	#define SHARC_TIMING 0x00000700
404
405	#define CFG_OR5 (SHARC_OR_AM \| SHARC_TIMING )
406	#define CFG_BR5 ((SHARC_BASE & BR_BA_MSK) \| BR_PS_32 \| BR_MS_UPMA \| BR_V )
407
408	/*
409	* Memory Periodic Timer Prescaler
410	*/
411
412	/* periodic timer for refresh */
2535d602	413	#define CFG_MBMR_PTB 204
0f8c9768 WD	414
	415	/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
	416	#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
	417	#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
	418
	419	/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
	420	#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
	421	#if defined (CONFIG_IVMS8_16M)
	422	#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
	423	#elif defined (CONFIG_IVMS8_32M)
	424	#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
	425	#elif defined (CONFIG_IVMS8_64M)
	426	#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV8 /* setting for 1 bank */
	427	#endif
	428
	429
	430	/*
	431	* MBMR settings for SDRAM
	432	*/
	433
	434	#if defined (CONFIG_IVMS8_16M)
	435	/* 8 column SDRAM */
2535d602 WD	436	# define CFG_MBMR_8COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) \| \
	437	MBMR_AMB_TYPE_0 \| MBMR_DSB_1_CYCL \| MBMR_G0CLB_A11 \| \
	438	MBMR_RLFB_1X \| MBMR_WLFB_1X \| MBMR_TLFB_4X)
0f8c9768 WD	439	#elif defined (CONFIG_IVMS8_32M)
0f8c9768 WD	440	/* 128 MBit SDRAM */
2535d602 WD	441	#define CFG_MBMR_8COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) \| \
	442	MBMR_AMB_TYPE_1 \| MBMR_DSB_1_CYCL \| MBMR_G0CLB_A10 \| \
	443	MBMR_RLFB_1X \| MBMR_WLFB_1X \| MBMR_TLFB_4X)
0f8c9768 WD	444	#elif defined (CONFIG_IVMS8_64M)
0f8c9768 WD	445	/* 128 MBit SDRAM */
2535d602 WD	446	#define CFG_MBMR_8COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) \| \
	447	MBMR_AMB_TYPE_1 \| MBMR_DSB_1_CYCL \| MBMR_G0CLB_A10 \| \
	448	MBMR_RLFB_1X \| MBMR_WLFB_1X \| MBMR_TLFB_4X)
0f8c9768 WD	449
	450	#endif
	451
	452	/*
	453	* Internal Definitions
	454	*
	455	* Boot Flags
	456	*/
	457	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	458	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	459
	460	#endif /* __CONFIG_H */