[u-boot.git] / arch / arm / dts / socfpga_agilex.dtsi

// SPDX-License-Identifier:     GPL-2.0
/*
 * Copyright (C) 2019-2023 Intel Corporation <www.intel.com>
 */

/dts-v1/;
#include <dt-bindings/reset/altr,rst-mgr-s10.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/agilex-clock.h>

/ {
	compatible = "intel,socfpga-agilex";
	#address-cells = <2>;
	#size-cells = <2>;

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		service_reserved: svcbuffer@0 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x0 0x0 0x2000000>;
			alignment = <0x1000>;
			no-map;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			enable-method = "psci";
			reg = <0x0>;
		};

		cpu1: cpu@1 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			enable-method = "psci";
			reg = <0x1>;
		};

		cpu2: cpu@2 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			enable-method = "psci";
			reg = <0x2>;
		};

		cpu3: cpu@3 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			enable-method = "psci";
			reg = <0x3>;
		};
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <0 170 4>,
			     <0 171 4>,
			     <0 172 4>,
			     <0 173 4>;
		interrupt-affinity = <&cpu0>,
				     <&cpu1>,
				     <&cpu2>,
				     <&cpu3>;
		interrupt-parent = <&intc>;
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	intc: intc@fffc1000 {
		compatible = "arm,gic-400", "arm,cortex-a15-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x0 0xfffc1000 0x0 0x1000>,
		      <0x0 0xfffc2000 0x0 0x2000>,
		      <0x0 0xfffc4000 0x0 0x2000>,
		      <0x0 0xfffc6000 0x0 0x2000>;
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		device_type = "soc";
		interrupt-parent = <&intc>;
		ranges = <0 0 0 0xffffffff>;

		base_fpga_region {
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			compatible = "fpga-region";
			fpga-mgr = <&fpga_mgr>;
		};

		clkmgr: clock-controller@ffd10000 {
			compatible = "intel,agilex-clkmgr";
			reg = <0xffd10000 0x1000>;
			#clock-cells = <1>;
		};

		clocks {
			cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
				#clock-cells = <0>;
				compatible = "fixed-clock";
			};

			cb_intosc_ls_clk: cb-intosc-ls-clk {
				#clock-cells = <0>;
				compatible = "fixed-clock";
			};

			f2s_free_clk: f2s-free-clk {
				#clock-cells = <0>;
				compatible = "fixed-clock";
			};

			osc1: osc1 {
				#clock-cells = <0>;
				compatible = "fixed-clock";
			};

			qspi_clk: qspi-clk {
				#clock-cells = <0>;
				compatible = "fixed-clock";
				clock-frequency = <200000000>;
			};
		};
		gmac0: ethernet@ff800000 {
			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
			reg = <0xff800000 0x2000>;
			interrupts = <0 90 4>;
			interrupt-names = "macirq";
			mac-address = [00 00 00 00 00 00];
			resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
			reset-names = "stmmaceth", "stmmaceth-ocp";
			tx-fifo-depth = <16384>;
			rx-fifo-depth = <16384>;
			snps,multicast-filter-bins = <256>;
			iommus = <&smmu 1>;
			altr,sysmgr-syscon = <&sysmgr 0x44 0>;
			clocks = <&clkmgr AGILEX_EMAC0_CLK>;
			clock-names = "stmmaceth";
			status = "disabled";
		};

		gmac1: ethernet@ff802000 {
			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
			reg = <0xff802000 0x2000>;
			interrupts = <0 91 4>;
			interrupt-names = "macirq";
			mac-address = [00 00 00 00 00 00];
			resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
			reset-names = "stmmaceth", "stmmaceth-ocp";
			tx-fifo-depth = <16384>;
			rx-fifo-depth = <16384>;
			snps,multicast-filter-bins = <256>;
			iommus = <&smmu 2>;
			altr,sysmgr-syscon = <&sysmgr 0x48 8>;
			clocks = <&clkmgr AGILEX_EMAC1_CLK>;
			clock-names = "stmmaceth";
			status = "disabled";
		};

		gmac2: ethernet@ff804000 {
			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
			reg = <0xff804000 0x2000>;
			interrupts = <0 92 4>;
			interrupt-names = "macirq";
			mac-address = [00 00 00 00 00 00];
			resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
			reset-names = "stmmaceth", "stmmaceth-ocp";
			tx-fifo-depth = <16384>;
			rx-fifo-depth = <16384>;
			snps,multicast-filter-bins = <256>;
			iommus = <&smmu 3>;
			altr,sysmgr-syscon = <&sysmgr 0x4c 16>;
			clocks = <&clkmgr AGILEX_EMAC2_CLK>;
			clock-names = "stmmaceth";
			status = "disabled";
		};

		gpio0: gpio@ffc03200 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,dw-apb-gpio";
			reg = <0xffc03200 0x100>;
			resets = <&rst GPIO0_RESET>;
			status = "disabled";

			porta: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <24>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <0 110 4>;
			};
		};

		gpio1: gpio@ffc03300 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,dw-apb-gpio";
			reg = <0xffc03300 0x100>;
			resets = <&rst GPIO1_RESET>;
			status = "disabled";

			portb: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <24>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <0 111 4>;
			};
		};

		i2c0: i2c@ffc02800 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0xffc02800 0x100>;
			interrupts = <0 103 4>;
			resets = <&rst I2C0_RESET>;
			clocks = <&clkmgr AGILEX_L4_SP_CLK>;
			status = "disabled";
		};

		i2c1: i2c@ffc02900 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0xffc02900 0x100>;
			interrupts = <0 104 4>;
			resets = <&rst I2C1_RESET>;
			clocks = <&clkmgr AGILEX_L4_SP_CLK>;
			status = "disabled";
		};

		i2c2: i2c@ffc02a00 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0xffc02a00 0x100>;
			interrupts = <0 105 4>;
			resets = <&rst I2C2_RESET>;
			clocks = <&clkmgr AGILEX_L4_SP_CLK>;
			status = "disabled";
		};

		i2c3: i2c@ffc02b00 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0xffc02b00 0x100>;
			interrupts = <0 106 4>;
			resets = <&rst I2C3_RESET>;
			clocks = <&clkmgr AGILEX_L4_SP_CLK>;
			status = "disabled";
		};

		i2c4: i2c@ffc02c00 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0xffc02c00 0x100>;
			interrupts = <0 107 4>;
			resets = <&rst I2C4_RESET>;
			clocks = <&clkmgr AGILEX_L4_SP_CLK>;
			status = "disabled";
		};

		mmc: dwmmc0@ff808000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "altr,socfpga-dw-mshc";
			reg = <0xff808000 0x1000>;
			interrupts = <0 96 4>;
			fifo-depth = <0x400>;
			resets = <&rst SDMMC_RESET>;
			reset-names = "reset";
			clocks = <&clkmgr AGILEX_L4_MP_CLK>,
				 <&clkmgr AGILEX_SDMMC_CLK>;
			clock-names = "biu", "ciu";
			iommus = <&smmu 5>;
			status = "disabled";
		};

		nand: nand@ffb90000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "altr,socfpga-denali-nand";
			reg = <0xffb90000 0x10000>,
			      <0xffb80000 0x1000>;
			reg-names = "nand_data", "denali_reg";
			interrupts = <0 97 4>;
			resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>;
			status = "disabled";
		};

		ocram: sram@ffe00000 {
			compatible = "mmio-sram";
			reg = <0xffe00000 0x40000>;
		};

		pdma: pdma@ffda0000 {
			compatible = "arm,pl330", "arm,primecell";
			reg = <0xffda0000 0x1000>;
			interrupts = <0 81 4>,
				     <0 82 4>,
				     <0 83 4>,
				     <0 84 4>,
				     <0 85 4>,
				     <0 86 4>,
				     <0 87 4>,
				     <0 88 4>,
				     <0 89 4>;
			#dma-cells = <1>;
			#dma-channels = <8>;
			#dma-requests = <32>;
			resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
			reset-names = "dma", "dma-ocp";
			clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
			clock-names = "apb_pclk";
		};

		rst: rstmgr@ffd11000 {
			#reset-cells = <1>;
			compatible = "altr,stratix10-rst-mgr";
			reg = <0xffd11000 0x100>;
		};

		smmu: iommu@fa000000 {
			compatible = "arm,mmu-500", "arm,smmu-v2";
			reg = <0xfa000000 0x40000>;
			#global-interrupts = <2>;
			#iommu-cells = <1>;
			interrupt-parent = <&intc>;
			interrupts = <0 128 4>,	/* Global Secure Fault */
				<0 129 4>, /* Global Non-secure Fault */
				/* Non-secure Context Interrupts (32) */
				<0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>,
				<0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>,
				<0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>,
				<0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>,
				<0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>,
				<0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>,
				<0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>,
				<0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>;
			stream-match-mask = <0x7ff0>;
			status = "disabled";
		};

		spi0: spi@ffda4000 {
			compatible = "intel,agilex-spi",
				     "snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0xffda4000 0x1000>;
			interrupts = <0 99 4>;
			resets = <&rst SPIM0_RESET>;
			reg-io-width = <4>;
			num-cs = <4>;
			clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
			status = "disabled";
		};

		spi1: spi@ffda5000 {
			compatible = "intel,agilex-spi",
				     "snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0xffda5000 0x1000>;
			interrupts = <0 100 4>;
			resets = <&rst SPIM1_RESET>;
			reg-io-width = <4>;
			num-cs = <4>;
			clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
			status = "disabled";
		};

		sysmgr: sysmgr@ffd12000 {
			compatible = "altr,sys-mgr-s10","altr,sys-mgr";
			reg = <0xffd12000 0x500>;
		};

		/* Local timer */
		timer {
			compatible = "arm,armv8-timer";
			interrupts = <1 13 0xf08>,
				     <1 14 0xf08>,
				     <1 11 0xf08>,
				     <1 10 0xf08>;
		};

		timer0: timer0@ffc03000 {
			compatible = "snps,dw-apb-timer";
			interrupts = <0 113 4>;
			reg = <0xffc03000 0x100>;
			clocks = <&clkmgr AGILEX_L4_SP_CLK>;
			clock-names = "timer";
		};

		timer1: timer1@ffc03100 {
			compatible = "snps,dw-apb-timer";
			interrupts = <0 114 4>;
			reg = <0xffc03100 0x100>;
			clocks = <&clkmgr AGILEX_L4_SP_CLK>;
			clock-names = "timer";
		};

		timer2: timer2@ffd00000 {
			compatible = "snps,dw-apb-timer";
			interrupts = <0 115 4>;
			reg = <0xffd00000 0x100>;
			clocks = <&clkmgr AGILEX_L4_SP_CLK>;
			clock-names = "timer";
		};

		timer3: timer3@ffd00100 {
			compatible = "snps,dw-apb-timer";
			interrupts = <0 116 4>;
			reg = <0xffd00100 0x100>;
			clocks = <&clkmgr AGILEX_L4_SP_CLK>;
			clock-names = "timer";
		};

		uart0: serial0@ffc02000 {
			compatible = "snps,dw-apb-uart";
			reg = <0xffc02000 0x100>;
			interrupts = <0 108 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			resets = <&rst UART0_RESET>;
			status = "disabled";
			clocks = <&clkmgr AGILEX_L4_SP_CLK>;
			clock-frequency = <100000000>;
		};

		uart1: serial1@ffc02100 {
			compatible = "snps,dw-apb-uart";
			reg = <0xffc02100 0x100>;
			interrupts = <0 109 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			resets = <&rst UART1_RESET>;
			clocks = <&clkmgr AGILEX_L4_SP_CLK>;
			status = "disabled";
		};

		usbphy0: usbphy@0 {
			#phy-cells = <0>;
			compatible = "usb-nop-xceiv";
			status = "okay";
		};

		usb0: usb@ffb00000 {
			compatible = "snps,dwc2";
			reg = <0xffb00000 0x40000>;
			interrupts = <0 93 4>;
			phys = <&usbphy0>;
			phy-names = "usb2-phy";
			resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
			reset-names = "dwc2", "dwc2-ecc";
			clocks = <&clkmgr AGILEX_USB_CLK>;
			iommus = <&smmu 6>;
			status = "disabled";
		};

		usb1: usb@ffb40000 {
			compatible = "snps,dwc2";
			reg = <0xffb40000 0x40000>;
			interrupts = <0 94 4>;
			phys = <&usbphy0>;
			phy-names = "usb2-phy";
			resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
			reset-names = "dwc2", "dwc2-ecc";
			iommus = <&smmu 7>;
			clocks = <&clkmgr AGILEX_USB_CLK>;
			status = "disabled";
		};

		watchdog0: watchdog@ffd00200 {
			compatible = "snps,dw-wdt";
			reg = <0xffd00200 0x100>;
			interrupts = <0 117 4>;
			resets = <&rst WATCHDOG0_RESET>;
			clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
			status = "disabled";
		};

		watchdog1: watchdog@ffd00300 {
			compatible = "snps,dw-wdt";
			reg = <0xffd00300 0x100>;
			interrupts = <0 118 4>;
			resets = <&rst WATCHDOG1_RESET>;
			clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
			status = "disabled";
		};

		watchdog2: watchdog@ffd00400 {
			compatible = "snps,dw-wdt";
			reg = <0xffd00400 0x100>;
			interrupts = <0 125 4>;
			resets = <&rst WATCHDOG2_RESET>;
			clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
			status = "disabled";
		};

		watchdog3: watchdog@ffd00500 {
			compatible = "snps,dw-wdt";
			reg = <0xffd00500 0x100>;
			interrupts = <0 126 4>;
			resets = <&rst WATCHDOG3_RESET>;
			clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
			status = "disabled";
		};

		sdr: sdr@f8011100 {
			compatible = "altr,sdr-ctl", "syscon";
			reg = <0xf8011100 0xc0>;
		};

		eccmgr {
			compatible = "altr,socfpga-s10-ecc-manager",
				     "altr,socfpga-a10-ecc-manager";
			altr,sysmgr-syscon = <&sysmgr>;
			#address-cells = <1>;
			#size-cells = <1>;
			interrupts = <0 15 4>;
			interrupt-controller;
			#interrupt-cells = <2>;
			ranges;

			sdramedac {
				compatible = "altr,sdram-edac-s10";
				altr,sdr-syscon = <&sdr>;
				interrupts = <16 4>;
			};

			ocram-ecc@ff8cc000 {
				compatible = "altr,socfpga-s10-ocram-ecc",
					     "altr,socfpga-a10-ocram-ecc";
				reg = <0xff8cc000 0x100>;
				altr,ecc-parent = <&ocram>;
				interrupts = <1 4>;
			};

			usb0-ecc@ff8c4000 {
				compatible = "altr,socfpga-s10-usb-ecc",
					     "altr,socfpga-usb-ecc";
				reg = <0xff8c4000 0x100>;
				altr,ecc-parent = <&usb0>;
				interrupts = <2 4>;
			};

			emac0-rx-ecc@ff8c0000 {
				compatible = "altr,socfpga-s10-eth-mac-ecc",
					     "altr,socfpga-eth-mac-ecc";
				reg = <0xff8c0000 0x100>;
				altr,ecc-parent = <&gmac0>;
				interrupts = <4 4>;
			};

			emac0-tx-ecc@ff8c0400 {
				compatible = "altr,socfpga-s10-eth-mac-ecc",
					     "altr,socfpga-eth-mac-ecc";
				reg = <0xff8c0400 0x100>;
				altr,ecc-parent = <&gmac0>;
				interrupts = <5 4>;
			};

			sdmmca-ecc@ff8c8c00 {
				compatible = "altr,socfpga-s10-sdmmc-ecc",
					     "altr,socfpga-sdmmc-ecc";
				reg = <0xff8c8c00 0x100>;
				altr,ecc-parent = <&mmc>;
				interrupts = <14 4>,
					     <15 4>;
			};
		};

		qspi: spi@ff8d2000 {
			compatible = "cdns,qspi-nor";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0xff8d2000 0x100>,
			      <0xff900000 0x100000>;
			interrupts = <0 3 4>;
			cdns,fifo-depth = <128>;
			cdns,fifo-width = <4>;
			cdns,trigger-address = <0x00000000>;
			clocks = <&qspi_clk>;

			status = "disabled";
		};

		firmware {
			svc {
				compatible = "intel,stratix10-svc";
				method = "smc";
				memory-region = <&service_reserved>;

				fpga_mgr: fpga-mgr {
					compatible = "intel,stratix10-soc-fpga-mgr";
				};
			};
		};
	};
};
Commit	Line	Data
fb386282 LFT	1	// SPDX-License-Identifier: GPL-2.0
fb386282 LFT	2	/*
3c9bb8fb	3	* Copyright (C) 2019-2023 Intel Corporation <www.intel.com>
fb386282 LFT	4	*/
	5
	6	/dts-v1/;
	7	#include <dt-bindings/reset/altr,rst-mgr-s10.h>
	8	#include <dt-bindings/gpio/gpio.h>
	9	#include <dt-bindings/clock/agilex-clock.h>
	10
	11	/ {
	12	compatible = "intel,socfpga-agilex";
	13	#address-cells = <2>;
	14	#size-cells = <2>;
	15
	16	reserved-memory {
	17	#address-cells = <2>;
	18	#size-cells = <2>;
	19	ranges;
	20
	21	service_reserved: svcbuffer@0 {
	22	compatible = "shared-dma-pool";
3c9bb8fb	23	reg = <0x0 0x0 0x0 0x2000000>;
fb386282 LFT	24	alignment = <0x1000>;
	25	no-map;
	26	};
	27	};
	28
	29	cpus {
	30	#address-cells = <1>;
	31	#size-cells = <0>;
	32
	33	cpu0: cpu@0 {
	34	compatible = "arm,cortex-a53";
	35	device_type = "cpu";
	36	enable-method = "psci";
	37	reg = <0x0>;
	38	};
	39
	40	cpu1: cpu@1 {
	41	compatible = "arm,cortex-a53";
	42	device_type = "cpu";
	43	enable-method = "psci";
	44	reg = <0x1>;
	45	};
	46
	47	cpu2: cpu@2 {
	48	compatible = "arm,cortex-a53";
	49	device_type = "cpu";
	50	enable-method = "psci";
	51	reg = <0x2>;
	52	};
	53
	54	cpu3: cpu@3 {
	55	compatible = "arm,cortex-a53";
	56	device_type = "cpu";
	57	enable-method = "psci";
	58	reg = <0x3>;
	59	};
	60	};
	61
	62	pmu {
	63	compatible = "arm,armv8-pmuv3";
	64	interrupts = <0 170 4>,
	65	<0 171 4>,
	66	<0 172 4>,
	67	<0 173 4>;
	68	interrupt-affinity = <&cpu0>,
	69	<&cpu1>,
	70	<&cpu2>,
	71	<&cpu3>;
	72	interrupt-parent = <&intc>;
	73	};
	74
	75	psci {
	76	compatible = "arm,psci-0.2";
	77	method = "smc";
	78	};
	79
	80	intc: intc@fffc1000 {
	81	compatible = "arm,gic-400", "arm,cortex-a15-gic";
	82	#interrupt-cells = <3>;
	83	interrupt-controller;
	84	reg = <0x0 0xfffc1000 0x0 0x1000>,
	85	<0x0 0xfffc2000 0x0 0x2000>,
	86	<0x0 0xfffc4000 0x0 0x2000>,
	87	<0x0 0xfffc6000 0x0 0x2000>;
88	};
89
90	soc {
91	#address-cells = <1>;
92	#size-cells = <1>;
93	compatible = "simple-bus";
94	device_type = "soc";
95	interrupt-parent = <&intc>;
96	ranges = <0 0 0 0xffffffff>;
97
98	base_fpga_region {
99	#address-cells = <0x1>;
100	#size-cells = <0x1>;
101	compatible = "fpga-region";
102	fpga-mgr = <&fpga_mgr>;
103	};
104
105	clkmgr: clock-controller@ffd10000 {
106	compatible = "intel,agilex-clkmgr";
107	reg = <0xffd10000 0x1000>;
108	#clock-cells = <1>;
109	};
110
111	clocks {
112	cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
113	#clock-cells = <0>;
114	compatible = "fixed-clock";
115	};
116
117	cb_intosc_ls_clk: cb-intosc-ls-clk {
118	#clock-cells = <0>;
119	compatible = "fixed-clock";
120	};
121
122	f2s_free_clk: f2s-free-clk {
123	#clock-cells = <0>;
124	compatible = "fixed-clock";
125	};
126
127	osc1: osc1 {
128	#clock-cells = <0>;
129	compatible = "fixed-clock";
130	};
131
132	qspi_clk: qspi-clk {
133	#clock-cells = <0>;
134	compatible = "fixed-clock";
135	clock-frequency = <200000000>;
136	};
137	};
138	gmac0: ethernet@ff800000 {
139	compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
140	reg = <0xff800000 0x2000>;
141	interrupts = <0 90 4>;
142	interrupt-names = "macirq";
143	mac-address = [00 00 00 00 00 00];
144	resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
145	reset-names = "stmmaceth", "stmmaceth-ocp";
146	tx-fifo-depth = <16384>;
147	rx-fifo-depth = <16384>;
148	snps,multicast-filter-bins = <256>;
149	iommus = <&smmu 1>;
150	altr,sysmgr-syscon = <&sysmgr 0x44 0>;
151	clocks = <&clkmgr AGILEX_EMAC0_CLK>;
152	clock-names = "stmmaceth";
153	status = "disabled";
154	};
155
156	gmac1: ethernet@ff802000 {
157	compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
158	reg = <0xff802000 0x2000>;
159	interrupts = <0 91 4>;
160	interrupt-names = "macirq";
161	mac-address = [00 00 00 00 00 00];
162	resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
163	reset-names = "stmmaceth", "stmmaceth-ocp";
164	tx-fifo-depth = <16384>;
165	rx-fifo-depth = <16384>;
166	snps,multicast-filter-bins = <256>;
167	iommus = <&smmu 2>;
168	altr,sysmgr-syscon = <&sysmgr 0x48 8>;
169	clocks = <&clkmgr AGILEX_EMAC1_CLK>;
170	clock-names = "stmmaceth";
171	status = "disabled";
172	};
173
174	gmac2: ethernet@ff804000 {
175	compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
176	reg = <0xff804000 0x2000>;
177	interrupts = <0 92 4>;
178	interrupt-names = "macirq";
179	mac-address = [00 00 00 00 00 00];
180	resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
181	reset-names = "stmmaceth", "stmmaceth-ocp";
182	tx-fifo-depth = <16384>;
183	rx-fifo-depth = <16384>;
184	snps,multicast-filter-bins = <256>;
185	iommus = <&smmu 3>;
186	altr,sysmgr-syscon = <&sysmgr 0x4c 16>;
187	clocks = <&clkmgr AGILEX_EMAC2_CLK>;
188	clock-names = "stmmaceth";
189	status = "disabled";
190	};
191
192	gpio0: gpio@ffc03200 {
193	#address-cells = <1>;
194	#size-cells = <0>;
195	compatible = "snps,dw-apb-gpio";
196	reg = <0xffc03200 0x100>;
197	resets = <&rst GPIO0_RESET>;
198	status = "disabled";
199
200	porta: gpio-controller@0 {
201	compatible = "snps,dw-apb-gpio-port";
202	gpio-controller;
203	#gpio-cells = <2>;
204	snps,nr-gpios = <24>;
205	reg = <0>;
206	interrupt-controller;
207	#interrupt-cells = <2>;
208	interrupts = <0 110 4>;
209	};
210	};
211
212	gpio1: gpio@ffc03300 {
213	#address-cells = <1>;
214	#size-cells = <0>;
215	compatible = "snps,dw-apb-gpio";
216	reg = <0xffc03300 0x100>;
217	resets = <&rst GPIO1_RESET>;
218	status = "disabled";
219
220	portb: gpio-controller@0 {
221	compatible = "snps,dw-apb-gpio-port";
222	gpio-controller;
223	#gpio-cells = <2>;
224	snps,nr-gpios = <24>;
225	reg = <0>;
226	interrupt-controller;
227	#interrupt-cells = <2>;
228	interrupts = <0 111 4>;
229	};
230	};
231
232	i2c0: i2c@ffc02800 {
233	#address-cells = <1>;
234	#size-cells = <0>;
235	compatible = "snps,designware-i2c";
236	reg = <0xffc02800 0x100>;
237	interrupts = <0 103 4>;
238	resets = <&rst I2C0_RESET>;
239	clocks = <&clkmgr AGILEX_L4_SP_CLK>;
240	status = "disabled";
241	};
242
243	i2c1: i2c@ffc02900 {
244	#address-cells = <1>;
245	#size-cells = <0>;
246	compatible = "snps,designware-i2c";
247	reg = <0xffc02900 0x100>;
248	interrupts = <0 104 4>;
249	resets = <&rst I2C1_RESET>;
250	clocks = <&clkmgr AGILEX_L4_SP_CLK>;
251	status = "disabled";
252	};
253
254	i2c2: i2c@ffc02a00 {
255	#address-cells = <1>;
256	#size-cells = <0>;
257	compatible = "snps,designware-i2c";
258	reg = <0xffc02a00 0x100>;
259	interrupts = <0 105 4>;
260	resets = <&rst I2C2_RESET>;
261	clocks = <&clkmgr AGILEX_L4_SP_CLK>;
262	status = "disabled";
263	};
264
265	i2c3: i2c@ffc02b00 {
266	#address-cells = <1>;
267	#size-cells = <0>;
268	compatible = "snps,designware-i2c";
269	reg = <0xffc02b00 0x100>;
270	interrupts = <0 106 4>;
271	resets = <&rst I2C3_RESET>;
272	clocks = <&clkmgr AGILEX_L4_SP_CLK>;
273	status = "disabled";
274	};
275
276	i2c4: i2c@ffc02c00 {
277	#address-cells = <1>;
278	#size-cells = <0>;
279	compatible = "snps,designware-i2c";
280	reg = <0xffc02c00 0x100>;
281	interrupts = <0 107 4>;
282	resets = <&rst I2C4_RESET>;
283	clocks = <&clkmgr AGILEX_L4_SP_CLK>;
284	status = "disabled";
285	};
286
287	mmc: dwmmc0@ff808000 {
288	#address-cells = <1>;
289	#size-cells = <0>;
290	compatible = "altr,socfpga-dw-mshc";
291	reg = <0xff808000 0x1000>;
292	interrupts = <0 96 4>;
293	fifo-depth = <0x400>;
294	resets = <&rst SDMMC_RESET>;
295	reset-names = "reset";
296	clocks = <&clkmgr AGILEX_L4_MP_CLK>,
297	<&clkmgr AGILEX_SDMMC_CLK>;
298	clock-names = "biu", "ciu";
299	iommus = <&smmu 5>;
300	status = "disabled";
301	};
302
303	nand: nand@ffb90000 {
304	#address-cells = <1>;
305	#size-cells = <0>;
306	compatible = "altr,socfpga-denali-nand";
307	reg = <0xffb90000 0x10000>,
308	<0xffb80000 0x1000>;
309	reg-names = "nand_data", "denali_reg";
310	interrupts = <0 97 4>;
311	resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>;
312	status = "disabled";
313	};
314
315	ocram: sram@ffe00000 {
316	compatible = "mmio-sram";
317	reg = <0xffe00000 0x40000>;
318	};
319
320	pdma: pdma@ffda0000 {
321	compatible = "arm,pl330", "arm,primecell";
322	reg = <0xffda0000 0x1000>;
323	interrupts = <0 81 4>,
324	<0 82 4>,
325	<0 83 4>,
326	<0 84 4>,
327	<0 85 4>,
328	<0 86 4>,
329	<0 87 4>,
330	<0 88 4>,
331	<0 89 4>;
332	#dma-cells = <1>;
333	#dma-channels = <8>;
334	#dma-requests = <32>;
335	resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
336	reset-names = "dma", "dma-ocp";
337	clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
338	clock-names = "apb_pclk";
339	};
340
341	rst: rstmgr@ffd11000 {
342	#reset-cells = <1>;
343	compatible = "altr,stratix10-rst-mgr";
344	reg = <0xffd11000 0x100>;
345	};
346
347	smmu: iommu@fa000000 {
348	compatible = "arm,mmu-500", "arm,smmu-v2";
349	reg = <0xfa000000 0x40000>;
350	#global-interrupts = <2>;
351	#iommu-cells = <1>;
352	interrupt-parent = <&intc>;
353	interrupts = <0 128 4>, /* Global Secure Fault */
354	<0 129 4>, /* Global Non-secure Fault */
355	/* Non-secure Context Interrupts (32) */
356	<0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>,
357	<0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>,
358	<0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>,
359	<0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>,
360	<0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>,
361	<0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>,
362	<0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>,
363	<0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>;
364	stream-match-mask = <0x7ff0>;
365	status = "disabled";
366	};
367
368	spi0: spi@ffda4000 {
237e5880 SA	369	compatible = "intel,agilex-spi",
237e5880 SA	370	"snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi";
fb386282 LFT	371	#address-cells = <1>;
	372	#size-cells = <0>;
	373	reg = <0xffda4000 0x1000>;
	374	interrupts = <0 99 4>;
	375	resets = <&rst SPIM0_RESET>;
	376	reg-io-width = <4>;
	377	num-cs = <4>;
	378	clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
	379	status = "disabled";
	380	};
	381
	382	spi1: spi@ffda5000 {
237e5880 SA	383	compatible = "intel,agilex-spi",
237e5880 SA	384	"snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi";
fb386282 LFT	385	#address-cells = <1>;
	386	#size-cells = <0>;
	387	reg = <0xffda5000 0x1000>;
	388	interrupts = <0 100 4>;
	389	resets = <&rst SPIM1_RESET>;
	390	reg-io-width = <4>;
	391	num-cs = <4>;
	392	clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
	393	status = "disabled";
	394	};
	395
	396	sysmgr: sysmgr@ffd12000 {
	397	compatible = "altr,sys-mgr-s10","altr,sys-mgr";
	398	reg = <0xffd12000 0x500>;
	399	};
	400
	401	/* Local timer */
	402	timer {
	403	compatible = "arm,armv8-timer";
	404	interrupts = <1 13 0xf08>,
	405	<1 14 0xf08>,
	406	<1 11 0xf08>,
	407	<1 10 0xf08>;
	408	};
	409
	410	timer0: timer0@ffc03000 {
	411	compatible = "snps,dw-apb-timer";
	412	interrupts = <0 113 4>;
	413	reg = <0xffc03000 0x100>;
	414	clocks = <&clkmgr AGILEX_L4_SP_CLK>;
	415	clock-names = "timer";
	416	};
	417
	418	timer1: timer1@ffc03100 {
	419	compatible = "snps,dw-apb-timer";
	420	interrupts = <0 114 4>;
	421	reg = <0xffc03100 0x100>;
	422	clocks = <&clkmgr AGILEX_L4_SP_CLK>;
	423	clock-names = "timer";
	424	};
	425
	426	timer2: timer2@ffd00000 {
	427	compatible = "snps,dw-apb-timer";
	428	interrupts = <0 115 4>;
	429	reg = <0xffd00000 0x100>;
	430	clocks = <&clkmgr AGILEX_L4_SP_CLK>;
	431	clock-names = "timer";
	432	};
	433
	434	timer3: timer3@ffd00100 {
	435	compatible = "snps,dw-apb-timer";
	436	interrupts = <0 116 4>;
	437	reg = <0xffd00100 0x100>;
	438	clocks = <&clkmgr AGILEX_L4_SP_CLK>;
	439	clock-names = "timer";
	440	};
	441
	442	uart0: serial0@ffc02000 {
	443	compatible = "snps,dw-apb-uart";
	444	reg = <0xffc02000 0x100>;
	445	interrupts = <0 108 4>;
	446	reg-shift = <2>;
	447	reg-io-width = <4>;
	448	resets = <&rst UART0_RESET>;
449	status = "disabled";
450	clocks = <&clkmgr AGILEX_L4_SP_CLK>;
451	clock-frequency = <100000000>;
452	};
453
454	uart1: serial1@ffc02100 {
455	compatible = "snps,dw-apb-uart";
456	reg = <0xffc02100 0x100>;
457	interrupts = <0 109 4>;
458	reg-shift = <2>;
459	reg-io-width = <4>;
460	resets = <&rst UART1_RESET>;
461	clocks = <&clkmgr AGILEX_L4_SP_CLK>;
462	status = "disabled";
463	};
464
465	usbphy0: usbphy@0 {
466	#phy-cells = <0>;
467	compatible = "usb-nop-xceiv";
468	status = "okay";
469	};
470
471	usb0: usb@ffb00000 {
472	compatible = "snps,dwc2";
473	reg = <0xffb00000 0x40000>;
474	interrupts = <0 93 4>;
475	phys = <&usbphy0>;
476	phy-names = "usb2-phy";
477	resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
478	reset-names = "dwc2", "dwc2-ecc";
479	clocks = <&clkmgr AGILEX_USB_CLK>;
480	iommus = <&smmu 6>;
481	status = "disabled";
482	};
483
484	usb1: usb@ffb40000 {
485	compatible = "snps,dwc2";
486	reg = <0xffb40000 0x40000>;
487	interrupts = <0 94 4>;
488	phys = <&usbphy0>;
489	phy-names = "usb2-phy";
490	resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
491	reset-names = "dwc2", "dwc2-ecc";
492	iommus = <&smmu 7>;
493	clocks = <&clkmgr AGILEX_USB_CLK>;
494	status = "disabled";
495	};
496
497	watchdog0: watchdog@ffd00200 {
498	compatible = "snps,dw-wdt";
499	reg = <0xffd00200 0x100>;
500	interrupts = <0 117 4>;
501	resets = <&rst WATCHDOG0_RESET>;
502	clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
503	status = "disabled";
504	};
505
506	watchdog1: watchdog@ffd00300 {
507	compatible = "snps,dw-wdt";
508	reg = <0xffd00300 0x100>;
509	interrupts = <0 118 4>;
510	resets = <&rst WATCHDOG1_RESET>;
511	clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
512	status = "disabled";
513	};
514
515	watchdog2: watchdog@ffd00400 {
516	compatible = "snps,dw-wdt";
517	reg = <0xffd00400 0x100>;
518	interrupts = <0 125 4>;
519	resets = <&rst WATCHDOG2_RESET>;
520	clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
521	status = "disabled";
522	};
523
524	watchdog3: watchdog@ffd00500 {
525	compatible = "snps,dw-wdt";
526	reg = <0xffd00500 0x100>;
527	interrupts = <0 126 4>;
528	resets = <&rst WATCHDOG3_RESET>;
529	clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
530	status = "disabled";
531	};
532
533	sdr: sdr@f8011100 {
534	compatible = "altr,sdr-ctl", "syscon";
535	reg = <0xf8011100 0xc0>;
536	};
537
538	eccmgr {
539	compatible = "altr,socfpga-s10-ecc-manager",
540	"altr,socfpga-a10-ecc-manager";
541	altr,sysmgr-syscon = <&sysmgr>;
542	#address-cells = <1>;
543	#size-cells = <1>;
544	interrupts = <0 15 4>;
545	interrupt-controller;
546	#interrupt-cells = <2>;
547	ranges;
548
549	sdramedac {
550	compatible = "altr,sdram-edac-s10";
551	altr,sdr-syscon = <&sdr>;
552	interrupts = <16 4>;
553	};
554
555	ocram-ecc@ff8cc000 {
556	compatible = "altr,socfpga-s10-ocram-ecc",
557	"altr,socfpga-a10-ocram-ecc";
558	reg = <0xff8cc000 0x100>;
559	altr,ecc-parent = <&ocram>;
560	interrupts = <1 4>;
561	};
562
563	usb0-ecc@ff8c4000 {
564	compatible = "altr,socfpga-s10-usb-ecc",
565	"altr,socfpga-usb-ecc";
566	reg = <0xff8c4000 0x100>;
567	altr,ecc-parent = <&usb0>;
568	interrupts = <2 4>;
569	};
570
571	emac0-rx-ecc@ff8c0000 {
572	compatible = "altr,socfpga-s10-eth-mac-ecc",
573	"altr,socfpga-eth-mac-ecc";
574	reg = <0xff8c0000 0x100>;
575	altr,ecc-parent = <&gmac0>;
576	interrupts = <4 4>;
577	};
578
579	emac0-tx-ecc@ff8c0400 {
580	compatible = "altr,socfpga-s10-eth-mac-ecc",
581	"altr,socfpga-eth-mac-ecc";
582	reg = <0xff8c0400 0x100>;
583	altr,ecc-parent = <&gmac0>;
584	interrupts = <5 4>;
585	};
586
587	sdmmca-ecc@ff8c8c00 {
588	compatible = "altr,socfpga-s10-sdmmc-ecc",
589	"altr,socfpga-sdmmc-ecc";
590	reg = <0xff8c8c00 0x100>;
591	altr,ecc-parent = <&mmc>;
592	interrupts = <14 4>,
593	<15 4>;
594	};
595	};
596
597	qspi: spi@ff8d2000 {
598	compatible = "cdns,qspi-nor";
599	#address-cells = <1>;
600	#size-cells = <0>;
601	reg = <0xff8d2000 0x100>,
602	<0xff900000 0x100000>;
603	interrupts = <0 3 4>;
604	cdns,fifo-depth = <128>;
605	cdns,fifo-width = <4>;
606	cdns,trigger-address = <0x00000000>;
607	clocks = <&qspi_clk>;
608
609	status = "disabled";
610	};
611
612	firmware {
613	svc {
614	compatible = "intel,stratix10-svc";
615	method = "smc";
616	memory-region = <&service_reserved>;
617
618	fpga_mgr: fpga-mgr {
619	compatible = "intel,stratix10-soc-fpga-mgr";
620	};
621	};
622	};
623	};
624	};