[u-boot.git] / arch / arm / dts / mt7988.dtsi

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2022 MediaTek Inc.
 * Author: Sam Shih <[email protected]>
 */

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mt7988-clk.h>
#include <dt-bindings/reset/mt7988-reset.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/mt65xx.h>
#include <dt-bindings/phy/phy.h>

/ {
	compatible = "mediatek,mt7988-rfb";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a73";
			reg = <0x0>;
			mediatek,hwver = <&hwver>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a73";
			reg = <0x1>;
			mediatek,hwver = <&hwver>;
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a73";
			reg = <0x2>;
			mediatek,hwver = <&hwver>;
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a73";
			reg = <0x3>;
			mediatek,hwver = <&hwver>;
		};
	};

	system_clk: dummy40m {
		compatible = "fixed-clock";
		clock-frequency = <40000000>;
		#clock-cells = <0>;
	};

	spi_clk: dummy208m {
		compatible = "fixed-clock";
		clock-frequency = <208000000>;
		#clock-cells = <0>;
	};

	hwver: hwver {
		compatible = "mediatek,hwver", "syscon";
		reg = <0 0x8000000 0 0x1000>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupt-parent = <&gic>;
		clock-frequency = <13000000>;
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
	};

	watchdog: watchdog@1001c000 {
		compatible = "mediatek,mt7622-wdt",
			     "mediatek,mt6589-wdt",
			     "syscon";
		reg = <0 0x1001c000 0 0x1000>;
		interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
		#reset-cells = <1>;
	};

	gic: interrupt-controller@c000000 {
		compatible = "arm,gic-v3";
		#interrupt-cells = <3>;
		interrupt-parent = <&gic>;
		interrupt-controller;
		reg = <0 0x0c000000 0 0x40000>,  /* GICD */
		      <0 0x0c080000 0 0x200000>; /* GICR */
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
	};

	apmixedsys: apmixedsys@1001e000 {
		compatible = "mediatek,mt7988-fixed-plls", "syscon";
		reg = <0 0x1001e000 0 0x1000>;
		#clock-cells = <1>;
	};

	topckgen: topckgen@1001b000 {
		compatible = "mediatek,mt7988-topckgen", "syscon";
		reg = <0 0x1001b000 0 0x1000>;
		clock-parent = <&apmixedsys>;
		#clock-cells = <1>;
	};

	pinctrl: pinctrl@1001f000 {
		compatible = "mediatek,mt7988-pinctrl";
		reg = <0 0x1001f000 0 0x1000>,
		      <0 0x11c10000 0 0x1000>,
		      <0 0x11d00000 0 0x1000>,
		      <0 0x11d20000 0 0x1000>,
		      <0 0x11e00000 0 0x1000>,
		      <0 0x11f00000 0 0x1000>,
		      <0 0x1000b000 0 0x1000>;
		reg-names = "gpio_base", "iocfg_tr_base", "iocfg_br_base",
			    "iocfg_rb_base", "iocfg_lb_base", "iocfg_tl_base",
			    "eint";
		gpio: gpio-controller {
			gpio-controller;
			#gpio-cells = <2>;
		};
	};

	sgmiisys0: syscon@10060000 {
		compatible = "mediatek,mt7988-sgmiisys_0", "syscon";
		reg = <0 0x10060000 0 0x1000>;
		clock-parent = <&topckgen>;
		#clock-cells = <1>;
	};

	sgmiisys1: syscon@10070000 {
		compatible = "mediatek,mt7988-sgmiisys_1", "syscon";
		reg = <0 0x10070000 0 0x1000>;
		clock-parent = <&topckgen>;
		#clock-cells = <1>;
	};

	usxgmiisys0: syscon@10080000 {
		compatible = "mediatek,mt7988-usxgmiisys_0", "syscon";
		reg = <0 0x10080000 0 0x1000>;
		clock-parent = <&topckgen>;
		#clock-cells = <1>;
	};

	usxgmiisys1: syscon@10081000 {
		compatible = "mediatek,mt7988-usxgmiisys_1", "syscon";
		reg = <0 0x10081000 0 0x1000>;
		clock-parent = <&topckgen>;
		#clock-cells = <1>;
	};

	dummy_clk: dummy12m {
		compatible = "fixed-clock";
		clock-frequency = <12000000>;
		#clock-cells = <0>;
		/* must need this line, or uart uanable to get dummy_clk */
		bootph-all;
	};

	xhci1: xhci@11200000 {
		compatible = "mediatek,mt7988-xhci",
			     "mediatek,mtk-xhci";
		reg = <0 0x11200000 0 0x2e00>,
		      <0 0x11203e00 0 0x0100>;
		reg-names = "mac", "ippc";
		interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
		phys = <&tphyu2port0 PHY_TYPE_USB2>,
		       <&tphyu3port0 PHY_TYPE_USB3>;
		clocks = <&dummy_clk>,
			 <&dummy_clk>,
			 <&dummy_clk>,
			 <&dummy_clk>,
			 <&dummy_clk>;
		clock-names = "sys_ck",
			      "xhci_ck",
			      "ref_ck",
			      "mcu_ck",
			      "dma_ck";
		#address-cells = <2>;
		#size-cells = <2>;
		status = "okay";
	};

	usbtphy: usb-phy@11c50000 {
		compatible = "mediatek,mt7988",
			     "mediatek,generic-tphy-v2";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		status = "okay";

		tphyu2port0: usb-phy@11c50000 {
			reg = <0 0x11c50000 0 0x700>;
			clocks = <&dummy_clk>;
			clock-names = "ref";
			#phy-cells = <1>;
			status = "okay";
		};

		tphyu3port0: usb-phy@11c50700 {
			reg = <0 0x11c50700 0 0x900>;
			clocks = <&dummy_clk>;
			clock-names = "ref";
			#phy-cells = <1>;
			mediatek,usb3-pll-ssc-delta;
			mediatek,usb3-pll-ssc-delta1;
			status = "okay";
		};
	};

	xfi_pextp0: syscon@11f20000 {
		compatible = "mediatek,mt7988-xfi_pextp_0", "syscon";
		reg = <0 0x11f20000 0 0x10000>;
		clock-parent = <&topckgen>;
		#clock-cells = <1>;
	};

	xfi_pextp1: syscon@11f30000 {
		compatible = "mediatek,mt7988-xfi_pextp_1", "syscon";
		reg = <0 0x11f30000 0 0x10000>;
		clock-parent = <&topckgen>;
		#clock-cells = <1>;
	};

	xfi_pll: syscon@11f40000 {
		compatible = "mediatek,mt7988-xfi_pll", "syscon";
		reg = <0 0x11f40000 0 0x1000>;
		clock-parent = <&topckgen>;
		#clock-cells = <1>;
	};

	topmisc: topmisc@11d10000 {
		compatible = "mediatek,mt7988-topmisc", "syscon",
			     "mediatek,mt7988-power-controller";
		reg = <0 0x11d10000 0 0x10000>;
		clock-parent = <&topckgen>;
		#clock-cells = <1>;
	};

	infracfg: infracfg@10001000 {
		compatible = "mediatek,mt7988-infracfg", "syscon";
		reg = <0 0x10001000 0 0x1000>;
		clock-parent = <&topckgen>;
		#clock-cells = <1>;
	};

	uart0: serial@11000000 {
		compatible = "mediatek,hsuart";
		reg = <0 0x11000000 0 0x100>;
		interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&infracfg CLK_INFRA_52M_UART0_CK>;
		assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
				  <&infracfg CLK_INFRA_MUX_UART0_SEL>;
		assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
					 <&topckgen CLK_TOP_UART_SEL>;
		status = "disabled";
	};

	uart1: serial@11000100 {
		compatible = "mediatek,hsuart";
		reg = <0 0x11000100 0 0x100>;
		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&infracfg CLK_INFRA_52M_UART1_CK>;
		assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
				  <&infracfg CLK_INFRA_MUX_UART1_SEL>;
		assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
					 <&topckgen CLK_TOP_UART_SEL>;
		status = "disabled";
	};

	uart2: serial@11000200 {
		compatible = "mediatek,hsuart";
		reg = <0 0x11000200 0 0x100>;
		interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&infracfg CLK_INFRA_52M_UART2_CK>;
		assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
				  <&infracfg CLK_INFRA_MUX_UART2_SEL>;
		assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
					 <&topckgen CLK_TOP_UART_SEL>;
		status = "disabled";
	};

	i2c0: i2c@11003000 {
		compatible = "mediatek,mt7988-i2c",
			     "mediatek,mt7981-i2c";
		reg = <0 0x11003000 0 0x1000>,
		      <0 0x10217080 0 0x80>;
		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
		clock-div = <1>;
		clocks = <&infracfg CLK_INFRA_I2C_BCK>,
			 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
		clock-names = "main", "dma";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c1: i2c@11004000 {
		compatible = "mediatek,mt7988-i2c",
			     "mediatek,mt7981-i2c";
		reg = <0 0x11004000 0 0x1000>,
		      <0 0x10217100 0 0x80>;
		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
		clock-div = <1>;
		clocks = <&infracfg CLK_INFRA_I2C_BCK>,
			 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
		clock-names = "main", "dma";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c2: i2c@11005000 {
		compatible = "mediatek,mt7988-i2c",
			     "mediatek,mt7981-i2c";
		reg = <0 0x11005000 0 0x1000>,
		      <0 0x10217180 0 0x80>;
		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
		clock-div = <1>;
		clocks = <&infracfg CLK_INFRA_I2C_BCK>,
			 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
		clock-names = "main", "dma";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	pwm: pwm@10048000 {
		compatible = "mediatek,mt7988-pwm";
		reg = <0 0x10048000 0 0x1000>;
		#pwm-cells = <2>;
		clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>,
			 <&infracfg CLK_INFRA_66M_PWM_HCK>,
			 <&infracfg CLK_INFRA_66M_PWM_CK1>,
			 <&infracfg CLK_INFRA_66M_PWM_CK2>,
			 <&infracfg CLK_INFRA_66M_PWM_CK3>,
			 <&infracfg CLK_INFRA_66M_PWM_CK4>,
			 <&infracfg CLK_INFRA_66M_PWM_CK5>,
			 <&infracfg CLK_INFRA_66M_PWM_CK6>,
			 <&infracfg CLK_INFRA_66M_PWM_CK7>,
			 <&infracfg CLK_INFRA_66M_PWM_CK8>;
		clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
			      "pwm4","pwm5","pwm6","pwm7","pwm8";
		status = "disabled";
	};

	snand: snand@11001000 {
		compatible = "mediatek,mt7988-snand",
			     "mediatek,mt7986-snand";
		reg = <0 0x11001000 0 0x1000>,
		      <0 0x11002000 0 0x1000>;
		reg-names = "nfi", "ecc";
		interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&infracfg CLK_INFRA_SPINFI>,
			 <&infracfg CLK_INFRA_NFI>,
			 <&infracfg CLK_INFRA_66M_NFI_HCK>;
		clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
		assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
				  <&topckgen CLK_TOP_NFI1X_SEL>;
		assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D8>,
					 <&topckgen CLK_TOP_MPLL_D8>;
		status = "disabled";
	};

	spi0: spi@1100a000 {
		compatible = "mediatek,ipm-spi";
		reg = <0 0x11007000 0 0x100>;
		clocks = <&spi_clk>,
			 <&spi_clk>;
		clock-names = "sel-clk", "spi-clk";
		interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
		status = "disabled";
	};

	spi1: spi@1100b000 {
		compatible = "mediatek,ipm-spi";
		reg = <0 0x11008000 0 0x100>;
		interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
		status = "disabled";
	};

	spi2: spi@11009000 {
		compatible = "mediatek,ipm-spi";
		reg = <0 0x11009000 0 0x100>;
		clocks = <&spi_clk>,
			 <&spi_clk>;
		clock-names = "sel-clk", "spi-clk";
		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
		status = "disabled";
	};

	mmc0: mmc@11230000 {
		compatible = "mediatek,mt7988-mmc",
			     "mediatek,mt7986-mmc";
		reg = <0 0x11230000 0 0x1000>;
		interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&infracfg CLK_INFRA_MSDC400>,
			 <&infracfg CLK_INFRA_MSDC2_HCK>,
			 <&infracfg CLK_INFRA_133M_MSDC_0_HCK>,
			 <&infracfg CLK_INFRA_66M_MSDC_0_HCK>;
		clock-names = "source", "hclk", "source_cg", "axi_cg";
		status = "disabled";
	};

	ethdma: syscon@15000000 {
		compatible = "mediatek,mt7988-ethdma", "syscon";
		reg = <0 0x15000000 0 0x20000>;
		clock-parent = <&topckgen>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	ethwarp: syscon@15031000 {
		compatible = "mediatek,mt7988-ethwarp", "syscon";
		reg = <0 0x15031000 0 0x1000>;
		clock-parent = <&topckgen>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	eth: ethernet@15100000 {
		compatible = "mediatek,mt7988-eth", "syscon";
		reg = <0 0x15100000 0 0x20000>;
		mediatek,ethsys = <&ethdma>;
		mediatek,sgmiisys = <&sgmiisys0>;
		mediatek,usxgmiisys = <&usxgmiisys0>;
		mediatek,xfi_pextp = <&xfi_pextp0>;
		mediatek,xfi_pll = <&xfi_pll>;
		mediatek,infracfg = <&topmisc>;
		mediatek,toprgu = <&watchdog>;
		resets = <&ethdma ETHDMA_FE_RST>, <&ethwarp ETHWARP_GSW_RST>;
		reset-names = "fe", "mcm";
		#address-cells = <1>;
		#size-cells = <0>;
		mediatek,mcm;
		status = "disabled";
	};
};
Commit	Line	Data
96b381e7 WG	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Copyright (c) 2022 MediaTek Inc.
	4	* Author: Sam Shih <[email protected]>
	5	*/
	6
	7	#include <dt-bindings/interrupt-controller/irq.h>
	8	#include <dt-bindings/interrupt-controller/arm-gic.h>
	9	#include <dt-bindings/clock/mt7988-clk.h>
	10	#include <dt-bindings/reset/mt7988-reset.h>
	11	#include <dt-bindings/gpio/gpio.h>
3b51d5b7	12	#include <dt-bindings/pinctrl/mt65xx.h>
44bab436	13	#include <dt-bindings/phy/phy.h>
96b381e7 WG	14
	15	/ {
	16	compatible = "mediatek,mt7988-rfb";
	17	interrupt-parent = <&gic>;
	18	#address-cells = <2>;
	19	#size-cells = <2>;
	20
	21	cpus {
	22	#address-cells = <1>;
	23	#size-cells = <0>;
	24
	25	cpu0: cpu@0 {
	26	device_type = "cpu";
	27	compatible = "arm,cortex-a73";
	28	reg = <0x0>;
	29	mediatek,hwver = <&hwver>;
	30	};
	31
	32	cpu1: cpu@1 {
	33	device_type = "cpu";
	34	compatible = "arm,cortex-a73";
	35	reg = <0x1>;
	36	mediatek,hwver = <&hwver>;
	37	};
	38
	39	cpu2: cpu@2 {
	40	device_type = "cpu";
	41	compatible = "arm,cortex-a73";
	42	reg = <0x2>;
	43	mediatek,hwver = <&hwver>;
	44	};
	45
	46	cpu3: cpu@3 {
	47	device_type = "cpu";
	48	compatible = "arm,cortex-a73";
	49	reg = <0x3>;
	50	mediatek,hwver = <&hwver>;
	51	};
	52	};
	53
	54	system_clk: dummy40m {
	55	compatible = "fixed-clock";
	56	clock-frequency = <40000000>;
	57	#clock-cells = <0>;
	58	};
	59
	60	spi_clk: dummy208m {
	61	compatible = "fixed-clock";
	62	clock-frequency = <208000000>;
	63	#clock-cells = <0>;
	64	};
	65
	66	hwver: hwver {
	67	compatible = "mediatek,hwver", "syscon";
	68	reg = <0 0x8000000 0 0x1000>;
	69	};
	70
	71	timer {
	72	compatible = "arm,armv8-timer";
	73	interrupt-parent = <&gic>;
	74	clock-frequency = <13000000>;
	75	interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
	76	<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
	77	<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
78	<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
79	};
80
81	watchdog: watchdog@1001c000 {
82	compatible = "mediatek,mt7622-wdt",
83	"mediatek,mt6589-wdt",
84	"syscon";
85	reg = <0 0x1001c000 0 0x1000>;
86	interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
87	#reset-cells = <1>;
88	};
89
90	gic: interrupt-controller@c000000 {
91	compatible = "arm,gic-v3";
92	#interrupt-cells = <3>;
93	interrupt-parent = <&gic>;
94	interrupt-controller;
95	reg = <0 0x0c000000 0 0x40000>, /* GICD */
96	<0 0x0c080000 0 0x200000>; /* GICR */
97	interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
98	};
99
96b381e7 WG	100	apmixedsys: apmixedsys@1001e000 {
	101	compatible = "mediatek,mt7988-fixed-plls", "syscon";
	102	reg = <0 0x1001e000 0 0x1000>;
	103	#clock-cells = <1>;
	104	};
	105
	106	topckgen: topckgen@1001b000 {
	107	compatible = "mediatek,mt7988-topckgen", "syscon";
	108	reg = <0 0x1001b000 0 0x1000>;
	109	clock-parent = <&apmixedsys>;
	110	#clock-cells = <1>;
	111	};
	112
	113	pinctrl: pinctrl@1001f000 {
	114	compatible = "mediatek,mt7988-pinctrl";
	115	reg = <0 0x1001f000 0 0x1000>,
	116	<0 0x11c10000 0 0x1000>,
	117	<0 0x11d00000 0 0x1000>,
	118	<0 0x11d20000 0 0x1000>,
	119	<0 0x11e00000 0 0x1000>,
	120	<0 0x11f00000 0 0x1000>,
	121	<0 0x1000b000 0 0x1000>;
	122	reg-names = "gpio_base", "iocfg_tr_base", "iocfg_br_base",
	123	"iocfg_rb_base", "iocfg_lb_base", "iocfg_tl_base",
	124	"eint";
	125	gpio: gpio-controller {
	126	gpio-controller;
	127	#gpio-cells = <2>;
	128	};
	129	};
	130
	131	sgmiisys0: syscon@10060000 {
	132	compatible = "mediatek,mt7988-sgmiisys_0", "syscon";
	133	reg = <0 0x10060000 0 0x1000>;
	134	clock-parent = <&topckgen>;
	135	#clock-cells = <1>;
	136	};
	137
	138	sgmiisys1: syscon@10070000 {
	139	compatible = "mediatek,mt7988-sgmiisys_1", "syscon";
	140	reg = <0 0x10070000 0 0x1000>;
	141	clock-parent = <&topckgen>;
	142	#clock-cells = <1>;
	143	};
	144
	145	usxgmiisys0: syscon@10080000 {
	146	compatible = "mediatek,mt7988-usxgmiisys_0", "syscon";
	147	reg = <0 0x10080000 0 0x1000>;
	148	clock-parent = <&topckgen>;
	149	#clock-cells = <1>;
	150	};
	151
	152	usxgmiisys1: syscon@10081000 {
	153	compatible = "mediatek,mt7988-usxgmiisys_1", "syscon";
	154	reg = <0 0x10081000 0 0x1000>;
	155	clock-parent = <&topckgen>;
	156	#clock-cells = <1>;
	157	};
	158
44bab436 FW	159	dummy_clk: dummy12m {
	160	compatible = "fixed-clock";
	161	clock-frequency = <12000000>;
	162	#clock-cells = <0>;
	163	/* must need this line, or uart uanable to get dummy_clk */
	164	bootph-all;
	165	};
	166
	167	xhci1: xhci@11200000 {
	168	compatible = "mediatek,mt7988-xhci",
	169	"mediatek,mtk-xhci";
	170	reg = <0 0x11200000 0 0x2e00>,
	171	<0 0x11203e00 0 0x0100>;
	172	reg-names = "mac", "ippc";
	173	interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
	174	phys = <&tphyu2port0 PHY_TYPE_USB2>,
	175	<&tphyu3port0 PHY_TYPE_USB3>;
	176	clocks = <&dummy_clk>,
	177	<&dummy_clk>,
	178	<&dummy_clk>,
	179	<&dummy_clk>,
	180	<&dummy_clk>;
	181	clock-names = "sys_ck",
	182	"xhci_ck",
	183	"ref_ck",
	184	"mcu_ck",
	185	"dma_ck";
	186	#address-cells = <2>;
	187	#size-cells = <2>;
	188	status = "okay";
	189	};
	190
	191	usbtphy: usb-phy@11c50000 {
	192	compatible = "mediatek,mt7988",
	193	"mediatek,generic-tphy-v2";
	194	#address-cells = <2>;
	195	#size-cells = <2>;
	196	ranges;
	197	status = "okay";
	198
	199	tphyu2port0: usb-phy@11c50000 {
	200	reg = <0 0x11c50000 0 0x700>;
	201	clocks = <&dummy_clk>;
	202	clock-names = "ref";
	203	#phy-cells = <1>;
	204	status = "okay";
	205	};
	206
	207	tphyu3port0: usb-phy@11c50700 {
	208	reg = <0 0x11c50700 0 0x900>;
	209	clocks = <&dummy_clk>;
	210	clock-names = "ref";
	211	#phy-cells = <1>;
	212	mediatek,usb3-pll-ssc-delta;
	213	mediatek,usb3-pll-ssc-delta1;
	214	status = "okay";
	215	};
	216	};
	217
96b381e7 WG	218	xfi_pextp0: syscon@11f20000 {
	219	compatible = "mediatek,mt7988-xfi_pextp_0", "syscon";
	220	reg = <0 0x11f20000 0 0x10000>;
	221	clock-parent = <&topckgen>;
	222	#clock-cells = <1>;
	223	};
	224
	225	xfi_pextp1: syscon@11f30000 {
	226	compatible = "mediatek,mt7988-xfi_pextp_1", "syscon";
	227	reg = <0 0x11f30000 0 0x10000>;
	228	clock-parent = <&topckgen>;
	229	#clock-cells = <1>;
	230	};
	231
	232	xfi_pll: syscon@11f40000 {
	233	compatible = "mediatek,mt7988-xfi_pll", "syscon";
	234	reg = <0 0x11f40000 0 0x1000>;
	235	clock-parent = <&topckgen>;
	236	#clock-cells = <1>;
	237	};
	238
	239	topmisc: topmisc@11d10000 {
	240	compatible = "mediatek,mt7988-topmisc", "syscon",
	241	"mediatek,mt7988-power-controller";
	242	reg = <0 0x11d10000 0 0x10000>;
	243	clock-parent = <&topckgen>;
	244	#clock-cells = <1>;
	245	};
	246
ef4a6485	247	infracfg: infracfg@10001000 {
96b381e7 WG	248	compatible = "mediatek,mt7988-infracfg", "syscon";
	249	reg = <0 0x10001000 0 0x1000>;
	250	clock-parent = <&topckgen>;
	251	#clock-cells = <1>;
	252	};
	253
	254	uart0: serial@11000000 {
	255	compatible = "mediatek,hsuart";
	256	reg = <0 0x11000000 0 0x100>;
	257	interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
99c5fa18 CM	258	clocks = <&infracfg CLK_INFRA_52M_UART0_CK>;
	259	assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
	260	<&infracfg CLK_INFRA_MUX_UART0_SEL>;
	261	assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
	262	<&topckgen CLK_TOP_UART_SEL>;
96b381e7 WG	263	status = "disabled";
	264	};
	265
	266	uart1: serial@11000100 {
	267	compatible = "mediatek,hsuart";
	268	reg = <0 0x11000100 0 0x100>;
	269	interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
99c5fa18 CM	270	clocks = <&infracfg CLK_INFRA_52M_UART1_CK>;
	271	assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
	272	<&infracfg CLK_INFRA_MUX_UART1_SEL>;
	273	assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
	274	<&topckgen CLK_TOP_UART_SEL>;
96b381e7 WG	275	status = "disabled";
	276	};
	277
	278	uart2: serial@11000200 {
	279	compatible = "mediatek,hsuart";
	280	reg = <0 0x11000200 0 0x100>;
	281	interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
99c5fa18 CM	282	clocks = <&infracfg CLK_INFRA_52M_UART2_CK>;
	283	assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
	284	<&infracfg CLK_INFRA_MUX_UART2_SEL>;
	285	assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
	286	<&topckgen CLK_TOP_UART_SEL>;
96b381e7 WG	287	status = "disabled";
	288	};
	289
	290	i2c0: i2c@11003000 {
	291	compatible = "mediatek,mt7988-i2c",
	292	"mediatek,mt7981-i2c";
	293	reg = <0 0x11003000 0 0x1000>,
	294	<0 0x10217080 0 0x80>;
	295	interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
	296	clock-div = <1>;
99c5fa18 CM	297	clocks = <&infracfg CLK_INFRA_I2C_BCK>,
99c5fa18 CM	298	<&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
96b381e7 WG	299	clock-names = "main", "dma";
	300	#address-cells = <1>;
	301	#size-cells = <0>;
	302	status = "disabled";
	303	};
	304
	305	i2c1: i2c@11004000 {
	306	compatible = "mediatek,mt7988-i2c",
	307	"mediatek,mt7981-i2c";
	308	reg = <0 0x11004000 0 0x1000>,
	309	<0 0x10217100 0 0x80>;
	310	interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
	311	clock-div = <1>;
99c5fa18 CM	312	clocks = <&infracfg CLK_INFRA_I2C_BCK>,
99c5fa18 CM	313	<&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
96b381e7 WG	314	clock-names = "main", "dma";
	315	#address-cells = <1>;
	316	#size-cells = <0>;
	317	status = "disabled";
	318	};
	319
	320	i2c2: i2c@11005000 {
	321	compatible = "mediatek,mt7988-i2c",
	322	"mediatek,mt7981-i2c";
	323	reg = <0 0x11005000 0 0x1000>,
	324	<0 0x10217180 0 0x80>;
	325	interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
	326	clock-div = <1>;
99c5fa18 CM	327	clocks = <&infracfg CLK_INFRA_I2C_BCK>,
99c5fa18 CM	328	<&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
96b381e7 WG	329	clock-names = "main", "dma";
	330	#address-cells = <1>;
	331	#size-cells = <0>;
	332	status = "disabled";
	333	};
	334
	335	pwm: pwm@10048000 {
	336	compatible = "mediatek,mt7988-pwm";
	337	reg = <0 0x10048000 0 0x1000>;
	338	#pwm-cells = <2>;
99c5fa18 CM	339	clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>,
	340	<&infracfg CLK_INFRA_66M_PWM_HCK>,
	341	<&infracfg CLK_INFRA_66M_PWM_CK1>,
	342	<&infracfg CLK_INFRA_66M_PWM_CK2>,
	343	<&infracfg CLK_INFRA_66M_PWM_CK3>,
	344	<&infracfg CLK_INFRA_66M_PWM_CK4>,
	345	<&infracfg CLK_INFRA_66M_PWM_CK5>,
	346	<&infracfg CLK_INFRA_66M_PWM_CK6>,
	347	<&infracfg CLK_INFRA_66M_PWM_CK7>,
	348	<&infracfg CLK_INFRA_66M_PWM_CK8>;
96b381e7 WG	349	clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
	350	"pwm4","pwm5","pwm6","pwm7","pwm8";
	351	status = "disabled";
	352	};
	353
	354	snand: snand@11001000 {
	355	compatible = "mediatek,mt7988-snand",
	356	"mediatek,mt7986-snand";
	357	reg = <0 0x11001000 0 0x1000>,
	358	<0 0x11002000 0 0x1000>;
	359	reg-names = "nfi", "ecc";
	360	interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
99c5fa18 CM	361	clocks = <&infracfg CLK_INFRA_SPINFI>,
	362	<&infracfg CLK_INFRA_NFI>,
	363	<&infracfg CLK_INFRA_66M_NFI_HCK>;
96b381e7	364	clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
99c5fa18 CM	365	assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
	366	<&topckgen CLK_TOP_NFI1X_SEL>;
	367	assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D8>,
	368	<&topckgen CLK_TOP_MPLL_D8>;
96b381e7 WG	369	status = "disabled";
	370	};
	371
	372	spi0: spi@1100a000 {
	373	compatible = "mediatek,ipm-spi";
	374	reg = <0 0x11007000 0 0x100>;
	375	clocks = <&spi_clk>,
	376	<&spi_clk>;
	377	clock-names = "sel-clk", "spi-clk";
	378	interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
	379	status = "disabled";
	380	};
	381
	382	spi1: spi@1100b000 {
	383	compatible = "mediatek,ipm-spi";
	384	reg = <0 0x11008000 0 0x100>;
	385	interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
	386	status = "disabled";
	387	};
	388
	389	spi2: spi@11009000 {
	390	compatible = "mediatek,ipm-spi";
	391	reg = <0 0x11009000 0 0x100>;
	392	clocks = <&spi_clk>,
	393	<&spi_clk>;
	394	clock-names = "sel-clk", "spi-clk";
	395	interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
	396	status = "disabled";
	397	};
	398
	399	mmc0: mmc@11230000 {
	400	compatible = "mediatek,mt7988-mmc",
	401	"mediatek,mt7986-mmc";
	402	reg = <0 0x11230000 0 0x1000>;
	403	interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
99c5fa18 CM	404	clocks = <&infracfg CLK_INFRA_MSDC400>,
	405	<&infracfg CLK_INFRA_MSDC2_HCK>,
	406	<&infracfg CLK_INFRA_133M_MSDC_0_HCK>,
	407	<&infracfg CLK_INFRA_66M_MSDC_0_HCK>;
96b381e7 WG	408	clock-names = "source", "hclk", "source_cg", "axi_cg";
	409	status = "disabled";
	410	};
	411
	412	ethdma: syscon@15000000 {
	413	compatible = "mediatek,mt7988-ethdma", "syscon";
	414	reg = <0 0x15000000 0 0x20000>;
	415	clock-parent = <&topckgen>;
	416	#clock-cells = <1>;
	417	#reset-cells = <1>;
	418	};
	419
	420	ethwarp: syscon@15031000 {
	421	compatible = "mediatek,mt7988-ethwarp", "syscon";
	422	reg = <0 0x15031000 0 0x1000>;
	423	clock-parent = <&topckgen>;
	424	#clock-cells = <1>;
	425	#reset-cells = <1>;
	426	};
	427
	428	eth: ethernet@15100000 {
	429	compatible = "mediatek,mt7988-eth", "syscon";
	430	reg = <0 0x15100000 0 0x20000>;
	431	mediatek,ethsys = <&ethdma>;
	432	mediatek,sgmiisys = <&sgmiisys0>;
	433	mediatek,usxgmiisys = <&usxgmiisys0>;
	434	mediatek,xfi_pextp = <&xfi_pextp0>;
	435	mediatek,xfi_pll = <&xfi_pll>;
	436	mediatek,infracfg = <&topmisc>;
	437	mediatek,toprgu = <&watchdog>;
	438	resets = <&ethdma ETHDMA_FE_RST>, <&ethwarp ETHWARP_GSW_RST>;
	439	reset-names = "fe", "mcm";
	440	#address-cells = <1>;
	441	#size-cells = <0>;
	442	mediatek,mcm;
	443	status = "disabled";
	444	};
	445	};