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352ed65d JK |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* | |
3 | * IOT2050 M.2 variant, overlay for B-key USB3.0 + E-key PCIE1_LANE0 | |
4 | * Copyright (c) Siemens AG, 2022 | |
5 | * | |
6 | * Authors: | |
7 | * Chao Zeng <[email protected]> | |
8 | * Jan Kiszka <[email protected]> | |
9 | */ | |
10 | ||
11 | /dts-v1/; | |
12 | /plugin/; | |
13 | ||
14 | #include <dt-bindings/phy/phy.h> | |
15 | #include <dt-bindings/gpio/gpio.h> | |
16 | ||
17 | &serdes0 { | |
18 | assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>; | |
19 | }; | |
20 | ||
21 | &pcie0_rc { | |
22 | status = "disabled"; | |
23 | }; | |
24 | ||
25 | &pcie1_rc { | |
26 | pinctrl-names = "default"; | |
27 | pinctrl-0 = <&minipcie_pins_default>; | |
28 | ||
29 | num-lanes = <1>; | |
30 | phys = <&serdes1 PHY_TYPE_PCIE 0>; | |
31 | phy-names = "pcie-phy0"; | |
32 | reset-gpios = <&wkup_gpio0 27 GPIO_ACTIVE_HIGH>; | |
33 | status = "okay"; | |
34 | }; | |
35 | ||
36 | &dwc3_0 { | |
37 | assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ | |
38 | <&k3_clks 151 8>; /* set PIPE3_TXB_CLK to WIZ8B2M4VSB */ | |
39 | phys = <&serdes0 PHY_TYPE_USB3 0>; | |
40 | phy-names = "usb3-phy"; | |
41 | }; | |
42 | ||
43 | &usb0 { | |
44 | maximum-speed = "super-speed"; | |
45 | snps,dis-u1-entry-quirk; | |
46 | snps,dis-u2-entry-quirk; | |
47 | }; |