[u-boot.git] / arch / arm / dts / juno-r2.dts

// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/*
 * ARM Ltd. Juno Platform
 *
 * Copyright (c) 2015 ARM Ltd.
 *
 * This file is licensed under a dual GPLv2 or BSD license.
 */

/dts-v1/;

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "juno-base.dtsi"
#include "juno-cs-r1r2.dtsi"

/ {
	model = "ARM Juno development board (r2)";
	compatible = "arm,juno-r2", "arm,juno", "arm,vexpress";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		serial0 = &soc_uart0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&A72_0>;
				};
				core1 {
					cpu = <&A72_1>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&A53_0>;
				};
				core1 {
					cpu = <&A53_1>;
				};
				core2 {
					cpu = <&A53_2>;
				};
				core3 {
					cpu = <&A53_3>;
				};
			};
		};

		idle-states {
			entry-method = "psci";

			CPU_SLEEP_0: cpu-sleep-0 {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x0010000>;
				local-timer-stop;
				entry-latency-us = <300>;
				exit-latency-us = <1200>;
				min-residency-us = <2000>;
			};

			CLUSTER_SLEEP_0: cluster-sleep-0 {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x1010000>;
				local-timer-stop;
				entry-latency-us = <400>;
				exit-latency-us = <1200>;
				min-residency-us = <2500>;
			};
		};

		A72_0: cpu@0 {
			compatible = "arm,cortex-a72";
			reg = <0x0 0x0>;
			device_type = "cpu";
			enable-method = "psci";
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&A72_L2>;
			clocks = <&scpi_dvfs 0>;
			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <450>;
		};

		A72_1: cpu@1 {
			compatible = "arm,cortex-a72";
			reg = <0x0 0x1>;
			device_type = "cpu";
			enable-method = "psci";
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&A72_L2>;
			clocks = <&scpi_dvfs 0>;
			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <450>;
		};

		A53_0: cpu@100 {
			compatible = "arm,cortex-a53";
			reg = <0x0 0x100>;
			device_type = "cpu";
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&A53_L2>;
			clocks = <&scpi_dvfs 1>;
			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
			capacity-dmips-mhz = <485>;
			dynamic-power-coefficient = <140>;
		};

		A53_1: cpu@101 {
			compatible = "arm,cortex-a53";
			reg = <0x0 0x101>;
			device_type = "cpu";
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&A53_L2>;
			clocks = <&scpi_dvfs 1>;
			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
			capacity-dmips-mhz = <485>;
			dynamic-power-coefficient = <140>;
		};

		A53_2: cpu@102 {
			compatible = "arm,cortex-a53";
			reg = <0x0 0x102>;
			device_type = "cpu";
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&A53_L2>;
			clocks = <&scpi_dvfs 1>;
			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
			capacity-dmips-mhz = <485>;
			dynamic-power-coefficient = <140>;
		};

		A53_3: cpu@103 {
			compatible = "arm,cortex-a53";
			reg = <0x0 0x103>;
			device_type = "cpu";
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&A53_L2>;
			clocks = <&scpi_dvfs 1>;
			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
			capacity-dmips-mhz = <485>;
			dynamic-power-coefficient = <140>;
		};

		A72_L2: l2-cache0 {
			compatible = "cache";
			cache-size = <0x200000>;
			cache-line-size = <64>;
			cache-sets = <2048>;
		};

		A53_L2: l2-cache1 {
			compatible = "cache";
			cache-size = <0x100000>;
			cache-line-size = <64>;
			cache-sets = <1024>;
		};
	};

	pmu-a72 {
		compatible = "arm,cortex-a72-pmu";
		interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&A72_0>,
				     <&A72_1>;
	};

	pmu-a53 {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&A53_0>,
				     <&A53_1>,
				     <&A53_2>,
				     <&A53_3>;
	};
};

&memtimer {
	status = "okay";
};

&pcie_ctlr {
	status = "okay";
};

&smmu_pcie {
	status = "okay";
};

&etm0 {
	cpu = <&A72_0>;
};

&etm1 {
	cpu = <&A72_1>;
};

&etm2 {
	cpu = <&A53_0>;
};

&etm3 {
	cpu = <&A53_1>;
};

&etm4 {
	cpu = <&A53_2>;
};

&etm5 {
	cpu = <&A53_3>;
};

&big_cluster_thermal_zone {
	status = "okay";
};

&little_cluster_thermal_zone {
	status = "okay";
};

&gpu0_thermal_zone {
	status = "okay";
};

&gpu1_thermal_zone {
	status = "okay";
};

&etf0_out_port {
	remote-endpoint = <&csys2_funnel_in_port0>;
};

&replicator_in_port0 {
	remote-endpoint = <&csys2_funnel_out_port>;
};

&csys1_funnel_in_port0 {
	remote-endpoint = <&stm_out_port>;
};

&stm_out_port {
	remote-endpoint = <&csys1_funnel_in_port0>;
};

&cpu_debug0 {
	cpu = <&A72_0>;
};

&cpu_debug1 {
	cpu = <&A72_1>;
};

&cpu_debug2 {
	cpu = <&A53_0>;
};

&cpu_debug3 {
	cpu = <&A53_1>;
};

&cpu_debug4 {
	cpu = <&A53_2>;
};

&cpu_debug5 {
	cpu = <&A53_3>;
};
Commit	Line	Data
aa26948b SG	1	// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
	2	/*
	3	* ARM Ltd. Juno Platform
	4	*
	5	* Copyright (c) 2015 ARM Ltd.
	6	*
	7	* This file is licensed under a dual GPLv2 or BSD license.
	8	*/
	9
	10	/dts-v1/;
	11
	12	#include <dt-bindings/interrupt-controller/arm-gic.h>
	13	#include "juno-base.dtsi"
	14	#include "juno-cs-r1r2.dtsi"
	15
	16	/ {
	17	model = "ARM Juno development board (r2)";
	18	compatible = "arm,juno-r2", "arm,juno", "arm,vexpress";
	19	interrupt-parent = <&gic>;
	20	#address-cells = <2>;
	21	#size-cells = <2>;
	22
	23	aliases {
	24	serial0 = &soc_uart0;
	25	};
	26
	27	chosen {
	28	stdout-path = "serial0:115200n8";
	29	};
	30
	31	psci {
	32	compatible = "arm,psci-0.2";
	33	method = "smc";
	34	};
	35
	36	cpus {
	37	#address-cells = <2>;
	38	#size-cells = <0>;
	39
	40	cpu-map {
	41	cluster0 {
	42	core0 {
	43	cpu = <&A72_0>;
	44	};
	45	core1 {
	46	cpu = <&A72_1>;
	47	};
	48	};
	49
	50	cluster1 {
	51	core0 {
	52	cpu = <&A53_0>;
	53	};
	54	core1 {
	55	cpu = <&A53_1>;
	56	};
	57	core2 {
	58	cpu = <&A53_2>;
	59	};
	60	core3 {
	61	cpu = <&A53_3>;
	62	};
	63	};
	64	};
65
66	idle-states {
67	entry-method = "psci";
68
69	CPU_SLEEP_0: cpu-sleep-0 {
70	compatible = "arm,idle-state";
71	arm,psci-suspend-param = <0x0010000>;
72	local-timer-stop;
73	entry-latency-us = <300>;
74	exit-latency-us = <1200>;
75	min-residency-us = <2000>;
76	};
77
78	CLUSTER_SLEEP_0: cluster-sleep-0 {
79	compatible = "arm,idle-state";
80	arm,psci-suspend-param = <0x1010000>;
81	local-timer-stop;
82	entry-latency-us = <400>;
83	exit-latency-us = <1200>;
84	min-residency-us = <2500>;
85	};
86	};
87
88	A72_0: cpu@0 {
89	compatible = "arm,cortex-a72";
90	reg = <0x0 0x0>;
91	device_type = "cpu";
92	enable-method = "psci";
93	i-cache-size = <0xc000>;
94	i-cache-line-size = <64>;
95	i-cache-sets = <256>;
96	d-cache-size = <0x8000>;
97	d-cache-line-size = <64>;
98	d-cache-sets = <256>;
99	next-level-cache = <&A72_L2>;
100	clocks = <&scpi_dvfs 0>;
101	cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
102	capacity-dmips-mhz = <1024>;
103	dynamic-power-coefficient = <450>;
104	};
105
106	A72_1: cpu@1 {
107	compatible = "arm,cortex-a72";
108	reg = <0x0 0x1>;
109	device_type = "cpu";
110	enable-method = "psci";
111	i-cache-size = <0xc000>;
112	i-cache-line-size = <64>;
113	i-cache-sets = <256>;
114	d-cache-size = <0x8000>;
115	d-cache-line-size = <64>;
116	d-cache-sets = <256>;
117	next-level-cache = <&A72_L2>;
118	clocks = <&scpi_dvfs 0>;
119	cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
120	capacity-dmips-mhz = <1024>;
121	dynamic-power-coefficient = <450>;
122	};
123
124	A53_0: cpu@100 {
125	compatible = "arm,cortex-a53";
126	reg = <0x0 0x100>;
127	device_type = "cpu";
128	enable-method = "psci";
129	i-cache-size = <0x8000>;
130	i-cache-line-size = <64>;
131	i-cache-sets = <256>;
132	d-cache-size = <0x8000>;
133	d-cache-line-size = <64>;
134	d-cache-sets = <128>;
135	next-level-cache = <&A53_L2>;
136	clocks = <&scpi_dvfs 1>;
137	cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
138	capacity-dmips-mhz = <485>;
139	dynamic-power-coefficient = <140>;
140	};
141
142	A53_1: cpu@101 {
143	compatible = "arm,cortex-a53";
144	reg = <0x0 0x101>;
145	device_type = "cpu";
146	enable-method = "psci";
147	i-cache-size = <0x8000>;
148	i-cache-line-size = <64>;
149	i-cache-sets = <256>;
150	d-cache-size = <0x8000>;
151	d-cache-line-size = <64>;
152	d-cache-sets = <128>;
153	next-level-cache = <&A53_L2>;
154	clocks = <&scpi_dvfs 1>;
155	cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
156	capacity-dmips-mhz = <485>;
157	dynamic-power-coefficient = <140>;
158	};
159
160	A53_2: cpu@102 {
161	compatible = "arm,cortex-a53";
162	reg = <0x0 0x102>;
163	device_type = "cpu";
164	enable-method = "psci";
165	i-cache-size = <0x8000>;
166	i-cache-line-size = <64>;
167	i-cache-sets = <256>;
168	d-cache-size = <0x8000>;
169	d-cache-line-size = <64>;
170	d-cache-sets = <128>;
171	next-level-cache = <&A53_L2>;
172	clocks = <&scpi_dvfs 1>;
173	cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
174	capacity-dmips-mhz = <485>;
175	dynamic-power-coefficient = <140>;
176	};
177
178	A53_3: cpu@103 {
179	compatible = "arm,cortex-a53";
180	reg = <0x0 0x103>;
181	device_type = "cpu";
182	enable-method = "psci";
183	i-cache-size = <0x8000>;
184	i-cache-line-size = <64>;
185	i-cache-sets = <256>;
186	d-cache-size = <0x8000>;
187	d-cache-line-size = <64>;
188	d-cache-sets = <128>;
189	next-level-cache = <&A53_L2>;
190	clocks = <&scpi_dvfs 1>;
191	cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
192	capacity-dmips-mhz = <485>;
193	dynamic-power-coefficient = <140>;
194	};
195
196	A72_L2: l2-cache0 {
197	compatible = "cache";
198	cache-size = <0x200000>;
199	cache-line-size = <64>;
200	cache-sets = <2048>;
201	};
202
203	A53_L2: l2-cache1 {
204	compatible = "cache";
205	cache-size = <0x100000>;
206	cache-line-size = <64>;
207	cache-sets = <1024>;
208	};
209	};
210
211	pmu-a72 {
212	compatible = "arm,cortex-a72-pmu";
213	interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
214	<GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
215	interrupt-affinity = <&A72_0>,
216	<&A72_1>;
217	};
218
219	pmu-a53 {
220	compatible = "arm,cortex-a53-pmu";
221	interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
222	<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
223	<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
224	<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
225	interrupt-affinity = <&A53_0>,
226	<&A53_1>,
227	<&A53_2>,
228	<&A53_3>;
229	};
230	};
231
232	&memtimer {
233	status = "okay";
234	};
235
236	&pcie_ctlr {
237	status = "okay";
238	};
239
240	&smmu_pcie {
241	status = "okay";
242	};
243
244	&etm0 {
245	cpu = <&A72_0>;
246	};
247
248	&etm1 {
249	cpu = <&A72_1>;
250	};
251
252	&etm2 {
253	cpu = <&A53_0>;
254	};
255
256	&etm3 {
257	cpu = <&A53_1>;
258	};
259
260	&etm4 {
261	cpu = <&A53_2>;
262	};
263
264	&etm5 {
265	cpu = <&A53_3>;
266	};
267
268	&big_cluster_thermal_zone {
269	status = "okay";
270	};
271
272	&little_cluster_thermal_zone {
273	status = "okay";
274	};
275
276	&gpu0_thermal_zone {
277	status = "okay";
278	};
279
280	&gpu1_thermal_zone {
281	status = "okay";
282	};
283
284	&etf0_out_port {
285	remote-endpoint = <&csys2_funnel_in_port0>;
286	};
287
288	&replicator_in_port0 {
289	remote-endpoint = <&csys2_funnel_out_port>;
290	};
291
292	&csys1_funnel_in_port0 {
293	remote-endpoint = <&stm_out_port>;
294	};
295
296	&stm_out_port {
297	remote-endpoint = <&csys1_funnel_in_port0>;
298	};
299
300	&cpu_debug0 {
301	cpu = <&A72_0>;
302	};
303
304	&cpu_debug1 {
305	cpu = <&A72_1>;
306	};
307
308	&cpu_debug2 {
309	cpu = <&A53_0>;
310	};
311
312	&cpu_debug3 {
313	cpu = <&A53_1>;
314	};
315
316	&cpu_debug4 {
317	cpu = <&A53_2>;
318	};
319
320	&cpu_debug5 {
321	cpu = <&A53_3>;
322	};