[u-boot.git] / arch / arm / dts / armada-8k.dtsi

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2018 - 2021 Marvell International Ltd.
 */
/* Common definitions used by Armada 8K DTs */

/* This defines used to calculate the base address of each CP */
#define CP110_BASE_OFFSET			(0xf2000000)
#define CP110_SPACE_SIZE			(0x02000000)
#define CP110_BASE				(CP110_BASE_OFFSET + \
	((CP110_NUM % 2) * CP110_SPACE_SIZE))

#define CP110_PCIE_MEM_SIZE(iface)	(0xf00000)
#define CP110_PCIEx_CPU_MEM_BASE(iface)		\
	(0xf6000000 + (CP110_NUM % 2) * 0x4000000 + (iface) *  0x1000000)
#define CP110_PCIEx_BUS_MEM_BASE(iface)		\
		(CP110_PCIEx_CPU_MEM_BASE(iface))
#define CP110_PCIE_BUS_MEM_CFG			(0x82000000)
Commit	Line	Data
a0ba97e5 KP	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Copyright (C) 2018 - 2021 Marvell International Ltd.
	4	*/
	5	/* Common definitions used by Armada 8K DTs */
	6
	7	/* This defines used to calculate the base address of each CP */
	8	#define CP110_BASE_OFFSET (0xf2000000)
	9	#define CP110_SPACE_SIZE (0x02000000)
	10	#define CP110_BASE (CP110_BASE_OFFSET + \
	11	((CP110_NUM % 2) * CP110_SPACE_SIZE))
	12
	13	#define CP110_PCIE_MEM_SIZE(iface) (0xf00000)
	14	#define CP110_PCIEx_CPU_MEM_BASE(iface) \
	15	(0xf6000000 + (CP110_NUM % 2) * 0x4000000 + (iface) * 0x1000000)
	16	#define CP110_PCIEx_BUS_MEM_BASE(iface) \
	17	(CP110_PCIEx_CPU_MEM_BASE(iface))
	18	#define CP110_PCIE_BUS_MEM_CFG (0x82000000)