[u-boot.git] / arch / arm / dts / armada-375.dtsi

/*
 * Device Tree Include file for Marvell Armada 375 family SoC
 *
 * Copyright (C) 2014 Marvell
 *
 * Gregory CLEMENT <[email protected]>
 * Thomas Petazzoni <[email protected]>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/phy/phy.h>

#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))

/ {
	model = "Marvell Armada 375 family SoC";
	compatible = "marvell,armada375";

	aliases {
		gpio0 = &gpio0;
		gpio1 = &gpio1;
		gpio2 = &gpio2;
		serial0 = &uart0;
		serial1 = &uart1;
	};

	clocks {
		/* 2 GHz fixed main PLL */
		mainpll: mainpll {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <1000000000>;
		};
		/* 25 MHz reference crystal */
		refclk: oscillator {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <25000000>;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "marvell,armada-375-smp";

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <1>;
		};
	};

	pmu {
		compatible = "arm,cortex-a9-pmu";
		interrupts-extended = <&mpic 3>;
	};

	soc {
		compatible = "marvell,armada375-mbus", "simple-bus";
		#address-cells = <2>;
		#size-cells = <1>;
		controller = <&mbusc>;
		interrupt-parent = <&gic>;
		pcie-mem-aperture = <0xe0000000 0x8000000>;
		pcie-io-aperture  = <0xe8000000 0x100000>;

		bootrom {
			compatible = "marvell,bootrom";
			reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
		};

		devbus-bootcs {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus-cs0 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus-cs1 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus-cs2 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus-cs3 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		internal-regs {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;

			L2: cache-controller@8000 {
				compatible = "arm,pl310-cache";
				reg = <0x8000 0x1000>;
				cache-unified;
				cache-level = <2>;
				arm,double-linefill-incr = <1>;
				arm,double-linefill-wrap = <0>;
				arm,double-linefill = <1>;
				prefetch-data = <1>;
			};

			scu@c000 {
				compatible = "arm,cortex-a9-scu";
				reg = <0xc000 0x58>;
			};

			timer0: timer@c600 {
				compatible = "arm,cortex-a9-twd-timer";
				reg = <0xc600 0x20>;
				interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
				clocks = <&coreclk 2>;
			};

			gic: interrupt-controller@d000 {
				compatible = "arm,cortex-a9-gic";
				#interrupt-cells = <3>;
				#size-cells = <0>;
				interrupt-controller;
				reg = <0xd000 0x1000>,
				      <0xc100 0x100>;
			};

			mdio {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "marvell,orion-mdio";
				reg = <0xc0054 0x4>;
				clocks = <&gateclk 19>;
			};

			/* Network controller */
			ethernet@f0000 {
				compatible = "marvell,armada-375-pp2";
				reg = <0xf0000 0xa000>, /* Packet Processor regs */
				      <0xc0000 0x3060>, /* LMS regs */
				      <0xc4000 0x100>,  /* eth0 regs */
				      <0xc5000 0x100>;  /* eth1 regs */
				clocks = <&gateclk 3>, <&gateclk 19>;
				clock-names = "pp_clk", "gop_clk";
				status = "disabled";

				eth0: eth0@c4000 {
					interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
					port-id = <0>;
					status = "disabled";
				};

				eth1: eth1@c5000 {
					interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
					port-id = <1>;
					status = "disabled";
				};
			};

			rtc@10300 {
				compatible = "marvell,orion-rtc";
				reg = <0x10300 0x20>;
				interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
			};

			spi0: spi@10600 {
				compatible = "marvell,armada-375-spi",
						"marvell,orion-spi";
				reg = <0x10600 0x50>;
				#address-cells = <1>;
				#size-cells = <0>;
				cell-index = <0>;
				interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			spi1: spi@10680 {
				compatible = "marvell,armada-375-spi",
						"marvell,orion-spi";
				reg = <0x10680 0x50>;
				#address-cells = <1>;
				#size-cells = <0>;
				cell-index = <1>;
				interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			i2c0: i2c@11000 {
				compatible = "marvell,mv64xxx-i2c";
				reg = <0x11000 0x20>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
				timeout-ms = <1000>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			i2c1: i2c@11100 {
				compatible = "marvell,mv64xxx-i2c";
				reg = <0x11100 0x20>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
				timeout-ms = <1000>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			uart0: serial@12000 {
				compatible = "snps,dw-apb-uart";
				reg = <0x12000 0x100>;
				reg-shift = <2>;
				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
				reg-io-width = <1>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			uart1: serial@12100 {
				compatible = "snps,dw-apb-uart";
				reg = <0x12100 0x100>;
				reg-shift = <2>;
				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
				reg-io-width = <1>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			pinctrl {
				compatible = "marvell,mv88f6720-pinctrl";
				reg = <0x18000 0x24>;

				i2c0_pins: i2c0-pins {
					marvell,pins = "mpp14",  "mpp15";
					marvell,function = "i2c0";
				};

				i2c1_pins: i2c1-pins {
					marvell,pins = "mpp61",  "mpp62";
					marvell,function = "i2c1";
				};

				nand_pins: nand-pins {
					marvell,pins = "mpp0", "mpp1", "mpp2",
						"mpp3", "mpp4", "mpp5",
						"mpp6", "mpp7", "mpp8",
						"mpp9", "mpp10", "mpp11",
						"mpp12", "mpp13";
					marvell,function = "nand";
				};

				sdio_pins: sdio-pins {
					marvell,pins = "mpp24",  "mpp25", "mpp26",
						     "mpp27", "mpp28", "mpp29";
					marvell,function = "sd";
				};

				spi0_pins: spi0-pins {
					marvell,pins = "mpp0",  "mpp1", "mpp4",
						     "mpp5", "mpp8", "mpp9";
					marvell,function = "spi0";
				};
			};

			gpio0: gpio@18100 {
				compatible = "marvell,orion-gpio";
				reg = <0x18100 0x40>;
				ngpios = <32>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
			};

			gpio1: gpio@18140 {
				compatible = "marvell,orion-gpio";
				reg = <0x18140 0x40>;
				ngpios = <32>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
			};

			gpio2: gpio@18180 {
				compatible = "marvell,orion-gpio";
				reg = <0x18180 0x40>;
				ngpios = <3>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
			};

			systemc: system-controller@18200 {
				compatible = "marvell,armada-375-system-controller";
				reg = <0x18200 0x100>;
				#reset-cells = <2>;
			};

			gateclk: clock-gating-control@18220 {
				compatible = "marvell,armada-375-gating-clock";
				reg = <0x18220 0x4>;
				clocks = <&coreclk 0>;
				#clock-cells = <1>;
			};

			usbcluster: usb-cluster@18400 {
				compatible = "marvell,armada-375-usb-cluster";
				reg = <0x18400 0x4>;
				#phy-cells = <1>;
			};

			mbusc: mbus-controller@20000 {
				compatible = "marvell,mbus-controller";
				reg = <0x20000 0x100>, <0x20180 0x20>;
			};

			mpic: interrupt-controller@20a00 {
				compatible = "marvell,mpic";
				reg = <0x20a00 0x2d0>, <0x21070 0x58>;
				#interrupt-cells = <1>;
				#size-cells = <1>;
				interrupt-controller;
				msi-controller;
				interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
			};

			timer1: timer@20300 {
				compatible = "marvell,armada-375-timer", "marvell,armada-370-timer";
				reg = <0x20300 0x30>, <0x21040 0x30>;
				interrupts-extended = <&gic  GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
						      <&gic  GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
						      <&gic  GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
						      <&gic  GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
						      <&mpic 5>,
						      <&mpic 6>;
				clocks = <&coreclk 0>, <&refclk>;
				clock-names = "nbclk", "fixed";
			};

			watchdog@20300 {
				compatible = "marvell,armada-375-wdt";
				reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>;
				clocks = <&coreclk 0>, <&refclk>;
				clock-names = "nbclk", "fixed";
			};

			cpurst@20800 {
				compatible = "marvell,armada-370-cpu-reset";
				reg = <0x20800 0x10>;
			};

			coherency-fabric@21010 {
				compatible = "marvell,armada-375-coherency-fabric";
				reg = <0x21010 0x1c>;
			};

			usb@50000 {
				compatible = "marvell,orion-ehci";
				reg = <0x50000 0x500>;
				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 18>;
				phys = <&usbcluster PHY_TYPE_USB2>;
				phy-names = "usb";
				status = "disabled";
			};

			usb@54000 {
				compatible = "marvell,orion-ehci";
				reg = <0x54000 0x500>;
				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 26>;
				status = "disabled";
			};

			usb3@58000 {
				compatible = "marvell,armada-375-xhci";
				reg = <0x58000 0x20000>,<0x5b880 0x80>;
				interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 16>;
				phys = <&usbcluster PHY_TYPE_USB3>;
				phy-names = "usb";
				status = "disabled";
			};

			xor@60800 {
				compatible = "marvell,orion-xor";
				reg = <0x60800 0x100
				       0x60A00 0x100>;
				clocks = <&gateclk 22>;
				status = "okay";

				xor00 {
					interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
					dmacap,memcpy;
					dmacap,xor;
				};
				xor01 {
					interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
					dmacap,memcpy;
					dmacap,xor;
					dmacap,memset;
				};
			};

			xor@60900 {
				compatible = "marvell,orion-xor";
				reg = <0x60900 0x100
				       0x60b00 0x100>;
				clocks = <&gateclk 23>;
				status = "okay";

				xor10 {
					interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
					dmacap,memcpy;
					dmacap,xor;
				};
				xor11 {
					interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
					dmacap,memcpy;
					dmacap,xor;
					dmacap,memset;
				};
			};

			crypto@90000 {
				compatible = "marvell,armada-375-crypto";
				reg = <0x90000 0x10000>;
				reg-names = "regs";
				interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 30>, <&gateclk 31>,
					 <&gateclk 28>, <&gateclk 29>;
				clock-names = "cesa0", "cesa1",
					      "cesaz0", "cesaz1";
				marvell,crypto-srams = <&crypto_sram0>,
						       <&crypto_sram1>;
				marvell,crypto-sram-size = <0x800>;
			};

			sata@a0000 {
				compatible = "marvell,orion-sata";
				reg = <0xa0000 0x5000>;
				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 14>, <&gateclk 20>;
				clock-names = "0", "1";
				status = "disabled";
			};

			nand@d0000 {
				compatible = "marvell,armada370-nand-controller";
				reg = <0xd0000 0x54>;
				#address-cells = <1>;
				#size-cells = <1>;
				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 11>;
				status = "disabled";
			};

			mvsdio@d4000 {
				compatible = "marvell,orion-sdio";
				reg = <0xd4000 0x200>;
				interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 17>;
				bus-width = <4>;
				cap-sdio-irq;
				cap-sd-highspeed;
				cap-mmc-highspeed;
				status = "disabled";
			};

			thermal@e8078 {
				compatible = "marvell,armada375-thermal";
				reg = <0xe8078 0x4>, <0xe807c 0x8>;
				status = "okay";
			};

			coreclk: mvebu-sar@e8204 {
				compatible = "marvell,armada-375-core-clock";
				reg = <0xe8204 0x04>;
				#clock-cells = <1>;
			};

			coredivclk: corediv-clock@e8250 {
				compatible = "marvell,armada-375-corediv-clock";
				reg = <0xe8250 0xc>;
				#clock-cells = <1>;
				clocks = <&mainpll>;
				clock-output-names = "nand";
			};
		};

		pciec: pcie@82000000 {
			compatible = "marvell,armada-370-pcie";
			status = "disabled";
			device_type = "pci";

			#address-cells = <3>;
			#size-cells = <2>;

			msi-parent = <&mpic>;
			bus-range = <0x00 0xff>;

			ranges =
			       <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
				0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
				0x82000000 0x1 0       MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */
				0x81000000 0x1 0       MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO  */
				0x82000000 0x2 0       MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */
				0x81000000 0x2 0       MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO  */>;

			pcie0: pcie@1,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
				reg = <0x0800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 5>;
				resets = <&systemc 0 0>;
				status = "disabled";
			};

			pcie1: pcie@2,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
				reg = <0x1000 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
					  0x81000000 0 0 0x81000000 0x2 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 0>;
				interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <1>;
				clocks = <&gateclk 6>;
				resets = <&systemc 0 1>;
				status = "disabled";
			};

		};

		crypto_sram0: sa-sram0 {
			compatible = "mmio-sram";
			reg = <MBUS_ID(0x09, 0x09) 0 0x800>;
			clocks = <&gateclk 30>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>;
		};

		crypto_sram1: sa-sram1 {
			compatible = "mmio-sram";
			reg = <MBUS_ID(0x09, 0x05) 0 0x800>;
			clocks = <&gateclk 31>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>;
		};
	};
};
Commit	Line	Data
606576d5 SR	1	/*
	2	* Device Tree Include file for Marvell Armada 375 family SoC
	3	*
	4	* Copyright (C) 2014 Marvell
	5	*
	6	* Gregory CLEMENT <[email protected]>
	7	* Thomas Petazzoni <[email protected]>
	8	*
	9	* This file is dual-licensed: you can use it either under the terms
	10	* of the GPL or the X11 license, at your option. Note that this dual
	11	* licensing only applies to this file, and not this project as a
	12	* whole.
	13	*
	14	* a) This file is free software; you can redistribute it and/or
	15	* modify it under the terms of the GNU General Public License as
	16	* published by the Free Software Foundation; either version 2 of the
	17	* License, or (at your option) any later version.
	18	*
	19	* This file is distributed in the hope that it will be useful
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	* GNU General Public License for more details.
	23	*
	24	* Or, alternatively
	25	*
	26	* b) Permission is hereby granted, free of charge, to any person
	27	* obtaining a copy of this software and associated documentation
	28	* files (the "Software"), to deal in the Software without
	29	* restriction, including without limitation the rights to use
	30	* copy, modify, merge, publish, distribute, sublicense, and/or
	31	* sell copies of the Software, and to permit persons to whom the
	32	* Software is furnished to do so, subject to the following
	33	* conditions:
	34	*
	35	* The above copyright notice and this permission notice shall be
	36	* included in all copies or substantial portions of the Software.
	37	*
	38	* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
	39	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	40	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	41	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	42	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
	43	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	44	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	45	* OTHER DEALINGS IN THE SOFTWARE.
	46	*/
	47
	48	#include "skeleton.dtsi"
	49	#include <dt-bindings/interrupt-controller/arm-gic.h>
	50	#include <dt-bindings/interrupt-controller/irq.h>
	51	#include <dt-bindings/phy/phy.h>
	52
	53	#define MBUS_ID(target,attributes) (((target) << 24) \| ((attributes) << 16))
	54
	55	/ {
	56	model = "Marvell Armada 375 family SoC";
	57	compatible = "marvell,armada375";
	58
	59	aliases {
	60	gpio0 = &gpio0;
	61	gpio1 = &gpio1;
	62	gpio2 = &gpio2;
	63	serial0 = &uart0;
	64	serial1 = &uart1;
65	};
66
67	clocks {
68	/* 2 GHz fixed main PLL */
69	mainpll: mainpll {
70	compatible = "fixed-clock";
71	#clock-cells = <0>;
72	clock-frequency = <1000000000>;
73	};
74	/* 25 MHz reference crystal */
75	refclk: oscillator {
76	compatible = "fixed-clock";
77	#clock-cells = <0>;
78	clock-frequency = <25000000>;
79	};
80	};
81
82	cpus {
83	#address-cells = <1>;
84	#size-cells = <0>;
85	enable-method = "marvell,armada-375-smp";
86
87	cpu@0 {
88	device_type = "cpu";
89	compatible = "arm,cortex-a9";
90	reg = <0>;
91	};
92	cpu@1 {
93	device_type = "cpu";
94	compatible = "arm,cortex-a9";
95	reg = <1>;
96	};
97	};
98
99	pmu {
100	compatible = "arm,cortex-a9-pmu";
101	interrupts-extended = <&mpic 3>;
102	};
103
104	soc {
105	compatible = "marvell,armada375-mbus", "simple-bus";
606576d5 SR	106	#address-cells = <2>;
	107	#size-cells = <1>;
	108	controller = <&mbusc>;
	109	interrupt-parent = <&gic>;
	110	pcie-mem-aperture = <0xe0000000 0x8000000>;
	111	pcie-io-aperture = <0xe8000000 0x100000>;
	112
	113	bootrom {
	114	compatible = "marvell,bootrom";
	115	reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
	116	};
	117
	118	devbus-bootcs {
	119	compatible = "marvell,mvebu-devbus";
	120	reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
	121	ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
	122	#address-cells = <1>;
	123	#size-cells = <1>;
	124	clocks = <&coreclk 0>;
	125	status = "disabled";
	126	};
	127
	128	devbus-cs0 {
	129	compatible = "marvell,mvebu-devbus";
	130	reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
	131	ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
	132	#address-cells = <1>;
	133	#size-cells = <1>;
	134	clocks = <&coreclk 0>;
	135	status = "disabled";
	136	};
	137
	138	devbus-cs1 {
	139	compatible = "marvell,mvebu-devbus";
	140	reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
	141	ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
	142	#address-cells = <1>;
	143	#size-cells = <1>;
	144	clocks = <&coreclk 0>;
	145	status = "disabled";
	146	};
	147
	148	devbus-cs2 {
	149	compatible = "marvell,mvebu-devbus";
	150	reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
	151	ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
	152	#address-cells = <1>;
	153	#size-cells = <1>;
	154	clocks = <&coreclk 0>;
	155	status = "disabled";
	156	};
	157
	158	devbus-cs3 {
	159	compatible = "marvell,mvebu-devbus";
	160	reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
	161	ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
	162	#address-cells = <1>;
	163	#size-cells = <1>;
	164	clocks = <&coreclk 0>;
	165	status = "disabled";
	166	};
	167
	168	internal-regs {
	169	compatible = "simple-bus";
606576d5 SR	170	#address-cells = <1>;
	171	#size-cells = <1>;
	172	ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
	173
	174	L2: cache-controller@8000 {
	175	compatible = "arm,pl310-cache";
	176	reg = <0x8000 0x1000>;
	177	cache-unified;
	178	cache-level = <2>;
	179	arm,double-linefill-incr = <1>;
	180	arm,double-linefill-wrap = <0>;
	181	arm,double-linefill = <1>;
	182	prefetch-data = <1>;
	183	};
	184
	185	scu@c000 {
	186	compatible = "arm,cortex-a9-scu";
	187	reg = <0xc000 0x58>;
	188	};
	189
d06ba5cc	190	timer0: timer@c600 {
606576d5 SR	191	compatible = "arm,cortex-a9-twd-timer";
	192	reg = <0xc600 0x20>;
	193	interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING \| GIC_CPU_MASK_SIMPLE(2))>;
	194	clocks = <&coreclk 2>;
	195	};
	196
	197	gic: interrupt-controller@d000 {
	198	compatible = "arm,cortex-a9-gic";
	199	#interrupt-cells = <3>;
	200	#size-cells = <0>;
	201	interrupt-controller;
	202	reg = <0xd000 0x1000>,
	203	<0xc100 0x100>;
	204	};
	205
	206	mdio {
	207	#address-cells = <1>;
	208	#size-cells = <0>;
	209	compatible = "marvell,orion-mdio";
	210	reg = <0xc0054 0x4>;
	211	clocks = <&gateclk 19>;
	212	};
	213
	214	/* Network controller */
	215	ethernet@f0000 {
	216	compatible = "marvell,armada-375-pp2";
	217	reg = <0xf0000 0xa000>, /* Packet Processor regs */
	218	<0xc0000 0x3060>, /* LMS regs */
	219	<0xc4000 0x100>, /* eth0 regs */
	220	<0xc5000 0x100>; /* eth1 regs */
	221	clocks = <&gateclk 3>, <&gateclk 19>;
	222	clock-names = "pp_clk", "gop_clk";
	223	status = "disabled";
	224
	225	eth0: eth0@c4000 {
	226	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	227	port-id = <0>;
	228	status = "disabled";
	229	};
	230
	231	eth1: eth1@c5000 {
	232	interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
	233	port-id = <1>;
	234	status = "disabled";
	235	};
	236	};
	237
	238	rtc@10300 {
	239	compatible = "marvell,orion-rtc";
	240	reg = <0x10300 0x20>;
	241	interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
	242	};
	243
	244	spi0: spi@10600 {
	245	compatible = "marvell,armada-375-spi",
	246	"marvell,orion-spi";
	247	reg = <0x10600 0x50>;
	248	#address-cells = <1>;
	249	#size-cells = <0>;
	250	cell-index = <0>;
	251	interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
	252	clocks = <&coreclk 0>;
	253	status = "disabled";
	254	};
255
256	spi1: spi@10680 {
257	compatible = "marvell,armada-375-spi",
258	"marvell,orion-spi";
259	reg = <0x10680 0x50>;
260	#address-cells = <1>;
261	#size-cells = <0>;
262	cell-index = <1>;
263	interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
264	clocks = <&coreclk 0>;
265	status = "disabled";
266	};
267
268	i2c0: i2c@11000 {
269	compatible = "marvell,mv64xxx-i2c";
270	reg = <0x11000 0x20>;
271	#address-cells = <1>;
272	#size-cells = <0>;
273	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
274	timeout-ms = <1000>;
275	clocks = <&coreclk 0>;
276	status = "disabled";
277	};
278
279	i2c1: i2c@11100 {
280	compatible = "marvell,mv64xxx-i2c";
281	reg = <0x11100 0x20>;
282	#address-cells = <1>;
283	#size-cells = <0>;
284	interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
285	timeout-ms = <1000>;
286	clocks = <&coreclk 0>;
287	status = "disabled";
288	};
289
290	uart0: serial@12000 {
291	compatible = "snps,dw-apb-uart";
292	reg = <0x12000 0x100>;
293	reg-shift = <2>;
294	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
295	reg-io-width = <1>;
296	clocks = <&coreclk 0>;
297	status = "disabled";
298	};
299
300	uart1: serial@12100 {
301	compatible = "snps,dw-apb-uart";
302	reg = <0x12100 0x100>;
303	reg-shift = <2>;
304	interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
305	reg-io-width = <1>;
306	clocks = <&coreclk 0>;
307	status = "disabled";
308	};
309
310	pinctrl {
311	compatible = "marvell,mv88f6720-pinctrl";
312	reg = <0x18000 0x24>;
313
314	i2c0_pins: i2c0-pins {
315	marvell,pins = "mpp14", "mpp15";
316	marvell,function = "i2c0";
317	};
318
319	i2c1_pins: i2c1-pins {
320	marvell,pins = "mpp61", "mpp62";
321	marvell,function = "i2c1";
322	};
323
324	nand_pins: nand-pins {
325	marvell,pins = "mpp0", "mpp1", "mpp2",
326	"mpp3", "mpp4", "mpp5",
327	"mpp6", "mpp7", "mpp8",
328	"mpp9", "mpp10", "mpp11",
329	"mpp12", "mpp13";
330	marvell,function = "nand";
331	};
332
333	sdio_pins: sdio-pins {
334	marvell,pins = "mpp24", "mpp25", "mpp26",
335	"mpp27", "mpp28", "mpp29";
336	marvell,function = "sd";
337	};
338
339	spi0_pins: spi0-pins {
340	marvell,pins = "mpp0", "mpp1", "mpp4",
341	"mpp5", "mpp8", "mpp9";
342	marvell,function = "spi0";
343	};
344	};
345
346	gpio0: gpio@18100 {
347	compatible = "marvell,orion-gpio";
348	reg = <0x18100 0x40>;
349	ngpios = <32>;
350	gpio-controller;
351	#gpio-cells = <2>;
352	interrupt-controller;
353	#interrupt-cells = <2>;
354	interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
355	<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
356	<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
357	<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
358	};
359
360	gpio1: gpio@18140 {
361	compatible = "marvell,orion-gpio";
362	reg = <0x18140 0x40>;
363	ngpios = <32>;
364	gpio-controller;
365	#gpio-cells = <2>;
366	interrupt-controller;
367	#interrupt-cells = <2>;
368	interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
369	<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
370	<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
371	<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
372	};
373
374	gpio2: gpio@18180 {
375	compatible = "marvell,orion-gpio";
376	reg = <0x18180 0x40>;
377	ngpios = <3>;
378	gpio-controller;
379	#gpio-cells = <2>;
380	interrupt-controller;
381	#interrupt-cells = <2>;
382	interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
383	};
384
35e29e89	385	systemc: system-controller@18200 {
606576d5 SR	386	compatible = "marvell,armada-375-system-controller";
606576d5 SR	387	reg = <0x18200 0x100>;
35e29e89	388	#reset-cells = <2>;
606576d5 SR	389	};
	390
	391	gateclk: clock-gating-control@18220 {
	392	compatible = "marvell,armada-375-gating-clock";
	393	reg = <0x18220 0x4>;
	394	clocks = <&coreclk 0>;
	395	#clock-cells = <1>;
	396	};
	397
	398	usbcluster: usb-cluster@18400 {
	399	compatible = "marvell,armada-375-usb-cluster";
	400	reg = <0x18400 0x4>;
	401	#phy-cells = <1>;
	402	};
	403
	404	mbusc: mbus-controller@20000 {
	405	compatible = "marvell,mbus-controller";
	406	reg = <0x20000 0x100>, <0x20180 0x20>;
	407	};
	408
	409	mpic: interrupt-controller@20a00 {
	410	compatible = "marvell,mpic";
	411	reg = <0x20a00 0x2d0>, <0x21070 0x58>;
	412	#interrupt-cells = <1>;
	413	#size-cells = <1>;
	414	interrupt-controller;
	415	msi-controller;
	416	interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
	417	};
	418
d06ba5cc	419	timer1: timer@20300 {
606576d5 SR	420	compatible = "marvell,armada-375-timer", "marvell,armada-370-timer";
	421	reg = <0x20300 0x30>, <0x21040 0x30>;
	422	interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
	423	<&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
	424	<&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
	425	<&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
	426	<&mpic 5>,
	427	<&mpic 6>;
	428	clocks = <&coreclk 0>, <&refclk>;
	429	clock-names = "nbclk", "fixed";
	430	};
	431
	432	watchdog@20300 {
	433	compatible = "marvell,armada-375-wdt";
	434	reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>;
	435	clocks = <&coreclk 0>, <&refclk>;
	436	clock-names = "nbclk", "fixed";
	437	};
	438
	439	cpurst@20800 {
	440	compatible = "marvell,armada-370-cpu-reset";
	441	reg = <0x20800 0x10>;
	442	};
	443
	444	coherency-fabric@21010 {
	445	compatible = "marvell,armada-375-coherency-fabric";
	446	reg = <0x21010 0x1c>;
	447	};
	448
	449	usb@50000 {
	450	compatible = "marvell,orion-ehci";
	451	reg = <0x50000 0x500>;
	452	interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	453	clocks = <&gateclk 18>;
	454	phys = <&usbcluster PHY_TYPE_USB2>;
	455	phy-names = "usb";
	456	status = "disabled";
	457	};
	458
	459	usb@54000 {
	460	compatible = "marvell,orion-ehci";
	461	reg = <0x54000 0x500>;
	462	interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
	463	clocks = <&gateclk 26>;
	464	status = "disabled";
	465	};
	466
	467	usb3@58000 {
	468	compatible = "marvell,armada-375-xhci";
	469	reg = <0x58000 0x20000>,<0x5b880 0x80>;
	470	interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
	471	clocks = <&gateclk 16>;
	472	phys = <&usbcluster PHY_TYPE_USB3>;
	473	phy-names = "usb";
	474	status = "disabled";
	475	};
	476
	477	xor@60800 {
	478	compatible = "marvell,orion-xor";
	479	reg = <0x60800 0x100
	480	0x60A00 0x100>;
	481	clocks = <&gateclk 22>;
	482	status = "okay";
	483
484	xor00 {
485	interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
486	dmacap,memcpy;
487	dmacap,xor;
488	};
489	xor01 {
490	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
491	dmacap,memcpy;
492	dmacap,xor;
493	dmacap,memset;
494	};
495	};
496
497	xor@60900 {
498	compatible = "marvell,orion-xor";
499	reg = <0x60900 0x100
500	0x60b00 0x100>;
501	clocks = <&gateclk 23>;
502	status = "okay";
503
504	xor10 {
505	interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
506	dmacap,memcpy;
507	dmacap,xor;
508	};
509	xor11 {
510	interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
511	dmacap,memcpy;
512	dmacap,xor;
513	dmacap,memset;
514	};
515	};
516
517	crypto@90000 {
518	compatible = "marvell,armada-375-crypto";
519	reg = <0x90000 0x10000>;
520	reg-names = "regs";
521	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
522	<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
523	clocks = <&gateclk 30>, <&gateclk 31>,
524	<&gateclk 28>, <&gateclk 29>;
525	clock-names = "cesa0", "cesa1",
526	"cesaz0", "cesaz1";
527	marvell,crypto-srams = <&crypto_sram0>,
528	<&crypto_sram1>;
529	marvell,crypto-sram-size = <0x800>;
530	};
531
532	sata@a0000 {
533	compatible = "marvell,orion-sata";
534	reg = <0xa0000 0x5000>;
535	interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
536	clocks = <&gateclk 14>, <&gateclk 20>;
537	clock-names = "0", "1";
538	status = "disabled";
539	};
540
541	nand@d0000 {
204b8707	542	compatible = "marvell,armada370-nand-controller";
606576d5 SR	543	reg = <0xd0000 0x54>;
	544	#address-cells = <1>;
	545	#size-cells = <1>;
	546	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
	547	clocks = <&gateclk 11>;
	548	status = "disabled";
	549	};
	550
	551	mvsdio@d4000 {
	552	compatible = "marvell,orion-sdio";
	553	reg = <0xd4000 0x200>;
	554	interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
	555	clocks = <&gateclk 17>;
	556	bus-width = <4>;
	557	cap-sdio-irq;
	558	cap-sd-highspeed;
	559	cap-mmc-highspeed;
	560	status = "disabled";
	561	};
	562
	563	thermal@e8078 {
	564	compatible = "marvell,armada375-thermal";
	565	reg = <0xe8078 0x4>, <0xe807c 0x8>;
	566	status = "okay";
	567	};
	568
	569	coreclk: mvebu-sar@e8204 {
	570	compatible = "marvell,armada-375-core-clock";
	571	reg = <0xe8204 0x04>;
	572	#clock-cells = <1>;
	573	};
	574
	575	coredivclk: corediv-clock@e8250 {
	576	compatible = "marvell,armada-375-corediv-clock";
	577	reg = <0xe8250 0xc>;
	578	#clock-cells = <1>;
	579	clocks = <&mainpll>;
	580	clock-output-names = "nand";
	581	};
	582	};
	583
6f139bec	584	pciec: pcie@82000000 {
606576d5 SR	585	compatible = "marvell,armada-370-pcie";
	586	status = "disabled";
	587	device_type = "pci";
	588
	589	#address-cells = <3>;
	590	#size-cells = <2>;
	591
	592	msi-parent = <&mpic>;
	593	bus-range = <0x00 0xff>;
	594
	595	ranges =
	596	<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
	597	0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
	598	0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */
	599	0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO */
	600	0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */
	601	0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO */>;
	602
6f139bec	603	pcie0: pcie@1,0 {
606576d5 SR	604	device_type = "pci";
	605	assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
	606	reg = <0x0800 0 0 0 0>;
	607	#address-cells = <3>;
	608	#size-cells = <2>;
	609	#interrupt-cells = <1>;
	610	ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
	611	0x81000000 0 0 0x81000000 0x1 0 1 0>;
6f139bec	612	bus-range = <0x00 0xff>;
606576d5 SR	613	interrupt-map-mask = <0 0 0 0>;
	614	interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
	615	marvell,pcie-port = <0>;
	616	marvell,pcie-lane = <0>;
	617	clocks = <&gateclk 5>;
94c30f9c	618	resets = <&systemc 0 0>;
606576d5 SR	619	status = "disabled";
	620	};
	621
6f139bec	622	pcie1: pcie@2,0 {
606576d5 SR	623	device_type = "pci";
	624	assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
	625	reg = <0x1000 0 0 0 0>;
	626	#address-cells = <3>;
	627	#size-cells = <2>;
	628	#interrupt-cells = <1>;
	629	ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
	630	0x81000000 0 0 0x81000000 0x2 0 1 0>;
6f139bec	631	bus-range = <0x00 0xff>;
606576d5 SR	632	interrupt-map-mask = <0 0 0 0>;
	633	interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
	634	marvell,pcie-port = <0>;
	635	marvell,pcie-lane = <1>;
	636	clocks = <&gateclk 6>;
94c30f9c	637	resets = <&systemc 0 1>;
606576d5 SR	638	status = "disabled";
	639	};
	640
	641	};
	642
	643	crypto_sram0: sa-sram0 {
	644	compatible = "mmio-sram";
	645	reg = <MBUS_ID(0x09, 0x09) 0 0x800>;
	646	clocks = <&gateclk 30>;
	647	#address-cells = <1>;
	648	#size-cells = <1>;
	649	ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>;
	650	};
	651
	652	crypto_sram1: sa-sram1 {
	653	compatible = "mmio-sram";
	654	reg = <MBUS_ID(0x09, 0x05) 0 0x800>;
	655	clocks = <&gateclk 31>;
	656	#address-cells = <1>;
	657	#size-cells = <1>;
	658	ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>;
	659	};
	660	};
	661	};