[u-boot.git] / drivers / mmc / renesas-sdhi.c

/*
 * Copyright (C) 2018 Marek Vasut <[email protected]>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <clk.h>
#include <fdtdec.h>
#include <mmc.h>
#include <dm.h>
#include <linux/compat.h>
#include <linux/dma-direction.h>
#include <linux/io.h>
#include <linux/sizes.h>
#include <power/regulator.h>
#include <asm/unaligned.h>

#include "tmio-common.h"

#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)

/* SCC registers */
#define RENESAS_SDHI_SCC_DTCNTL			0x800
#define   RENESAS_SDHI_SCC_DTCNTL_TAPEN		BIT(0)
#define   RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT	16
#define   RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK		0xff
#define RENESAS_SDHI_SCC_TAPSET			0x804
#define RENESAS_SDHI_SCC_DT2FF			0x808
#define RENESAS_SDHI_SCC_CKSEL			0x80c
#define   RENESAS_SDHI_SCC_CKSEL_DTSEL		BIT(0)
#define RENESAS_SDHI_SCC_RVSCNTL			0x810
#define   RENESAS_SDHI_SCC_RVSCNTL_RVSEN		BIT(0)
#define RENESAS_SDHI_SCC_RVSREQ			0x814
#define   RENESAS_SDHI_SCC_RVSREQ_RVSERR		BIT(2)
#define RENESAS_SDHI_SCC_SMPCMP			0x818
#define RENESAS_SDHI_SCC_TMPPORT2			0x81c

#define RENESAS_SDHI_MAX_TAP 3

static unsigned int renesas_sdhi_init_tuning(struct tmio_sd_priv *priv)
{
	u32 reg;

	/* Initialize SCC */
	tmio_sd_writel(priv, 0, TMIO_SD_INFO1);

	reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
	reg &= ~TMIO_SD_CLKCTL_SCLKEN;
	tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);

	/* Set sampling clock selection range */
	tmio_sd_writel(priv, 0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT,
			   RENESAS_SDHI_SCC_DTCNTL);

	reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL);
	reg |= RENESAS_SDHI_SCC_DTCNTL_TAPEN;
	tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_DTCNTL);

	reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
	reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL;
	tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);

	reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
	reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
	tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);

	tmio_sd_writel(priv, 0x300 /* scc_tappos */,
			   RENESAS_SDHI_SCC_DT2FF);

	reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
	reg |= TMIO_SD_CLKCTL_SCLKEN;
	tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);

	/* Read TAPNUM */
	return (tmio_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL) >>
		RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
		RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK;
}

static void renesas_sdhi_reset_tuning(struct tmio_sd_priv *priv)
{
	u32 reg;

	/* Reset SCC */
	reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
	reg &= ~TMIO_SD_CLKCTL_SCLKEN;
	tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);

	reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
	reg &= ~RENESAS_SDHI_SCC_CKSEL_DTSEL;
	tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);

	reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
	reg |= TMIO_SD_CLKCTL_SCLKEN;
	tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);

	reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
	reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
	tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);

	reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
	reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
	tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
}

static void renesas_sdhi_prepare_tuning(struct tmio_sd_priv *priv,
				       unsigned long tap)
{
	/* Set sampling clock position */
	tmio_sd_writel(priv, tap, RENESAS_SDHI_SCC_TAPSET);
}

static unsigned int renesas_sdhi_compare_scc_data(struct tmio_sd_priv *priv)
{
	/* Get comparison of sampling data */
	return tmio_sd_readl(priv, RENESAS_SDHI_SCC_SMPCMP);
}

static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv,
				     unsigned int tap_num, unsigned int taps,
				     unsigned int smpcmp)
{
	unsigned long tap_cnt;  /* counter of tuning success */
	unsigned long tap_set;  /* tap position */
	unsigned long tap_start;/* start position of tuning success */
	unsigned long tap_end;  /* end position of tuning success */
	unsigned long ntap;     /* temporary counter of tuning success */
	unsigned long match_cnt;/* counter of matching data */
	unsigned long i;
	bool select = false;
	u32 reg;

	/* Clear SCC_RVSREQ */
	tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);

	/* Merge the results */
	for (i = 0; i < tap_num * 2; i++) {
		if (!(taps & BIT(i))) {
			taps &= ~BIT(i % tap_num);
			taps &= ~BIT((i % tap_num) + tap_num);
		}
		if (!(smpcmp & BIT(i))) {
			smpcmp &= ~BIT(i % tap_num);
			smpcmp &= ~BIT((i % tap_num) + tap_num);
		}
	}

	/*
	 * Find the longest consecutive run of successful probes.  If that
	 * is more than RENESAS_SDHI_MAX_TAP probes long then use the
	 * center index as the tap.
	 */
	tap_cnt = 0;
	ntap = 0;
	tap_start = 0;
	tap_end = 0;
	for (i = 0; i < tap_num * 2; i++) {
		if (taps & BIT(i))
			ntap++;
		else {
			if (ntap > tap_cnt) {
				tap_start = i - ntap;
				tap_end = i - 1;
				tap_cnt = ntap;
			}
			ntap = 0;
		}
	}

	if (ntap > tap_cnt) {
		tap_start = i - ntap;
		tap_end = i - 1;
		tap_cnt = ntap;
	}

	/*
	 * If all of the TAP is OK, the sampling clock position is selected by
	 * identifying the change point of data.
	 */
	if (tap_cnt == tap_num * 2) {
		match_cnt = 0;
		ntap = 0;
		tap_start = 0;
		tap_end = 0;
		for (i = 0; i < tap_num * 2; i++) {
			if (smpcmp & BIT(i))
				ntap++;
			else {
				if (ntap > match_cnt) {
					tap_start = i - ntap;
					tap_end = i - 1;
					match_cnt = ntap;
				}
				ntap = 0;
			}
		}
		if (ntap > match_cnt) {
			tap_start = i - ntap;
			tap_end = i - 1;
			match_cnt = ntap;
		}
		if (match_cnt)
			select = true;
	} else if (tap_cnt >= RENESAS_SDHI_MAX_TAP)
		select = true;

	if (select)
		tap_set = ((tap_start + tap_end) / 2) % tap_num;
	else
		return -EIO;

	/* Set SCC */
	tmio_sd_writel(priv, tap_set, RENESAS_SDHI_SCC_TAPSET);

	/* Enable auto re-tuning */
	reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
	reg |= RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
	tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);

	return 0;
}

int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode)
{
	struct tmio_sd_priv *priv = dev_get_priv(dev);
	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
	struct mmc *mmc = upriv->mmc;
	unsigned int tap_num;
	unsigned int taps = 0, smpcmp = 0;
	int i, ret = 0;
	u32 caps;

	/* Only supported on Renesas RCar */
	if (!(priv->caps & TMIO_SD_CAP_RCAR_UHS))
		return -EINVAL;

	/* clock tuning is not needed for upto 52MHz */
	if (!((mmc->selected_mode == MMC_HS_200) ||
	      (mmc->selected_mode == UHS_SDR104) ||
	      (mmc->selected_mode == UHS_SDR50)))
		return 0;

	tap_num = renesas_sdhi_init_tuning(priv);
	if (!tap_num)
		/* Tuning is not supported */
		goto out;

	if (tap_num * 2 >= sizeof(taps) * 8) {
		dev_err(dev,
			"Too many taps, skipping tuning. Please consider updating size of taps field of tmio_mmc_host\n");
		goto out;
	}

	/* Issue CMD19 twice for each tap */
	for (i = 0; i < 2 * tap_num; i++) {
		renesas_sdhi_prepare_tuning(priv, i % tap_num);

		/* Force PIO for the tuning */
		caps = priv->caps;
		priv->caps &= ~TMIO_SD_CAP_DMA_INTERNAL;

		ret = mmc_send_tuning(mmc, opcode, NULL);

		priv->caps = caps;

		if (ret == 0)
			taps |= BIT(i);

		ret = renesas_sdhi_compare_scc_data(priv);
		if (ret == 0)
			smpcmp |= BIT(i);

		mdelay(1);
	}

	ret = renesas_sdhi_select_tuning(priv, tap_num, taps, smpcmp);

out:
	if (ret < 0) {
		dev_warn(dev, "Tuning procedure failed\n");
		renesas_sdhi_reset_tuning(priv);
	}

	return ret;
}
#endif

static int renesas_sdhi_set_ios(struct udevice *dev)
{
	int ret = tmio_sd_set_ios(dev);

	mdelay(10);

#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
	struct tmio_sd_priv *priv = dev_get_priv(dev);

	renesas_sdhi_reset_tuning(priv);
#endif

	return ret;
}

static const struct dm_mmc_ops renesas_sdhi_ops = {
	.send_cmd = tmio_sd_send_cmd,
	.set_ios = renesas_sdhi_set_ios,
	.get_cd = tmio_sd_get_cd,
#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
	.execute_tuning = renesas_sdhi_execute_tuning,
#endif
};

#define RENESAS_GEN2_QUIRKS	TMIO_SD_CAP_RCAR_GEN2
#define RENESAS_GEN3_QUIRKS				\
	TMIO_SD_CAP_64BIT | TMIO_SD_CAP_RCAR_GEN3 | TMIO_SD_CAP_RCAR_UHS

static const struct udevice_id renesas_sdhi_match[] = {
	{ .compatible = "renesas,sdhi-r8a7790", .data = RENESAS_GEN2_QUIRKS },
	{ .compatible = "renesas,sdhi-r8a7791", .data = RENESAS_GEN2_QUIRKS },
	{ .compatible = "renesas,sdhi-r8a7792", .data = RENESAS_GEN2_QUIRKS },
	{ .compatible = "renesas,sdhi-r8a7793", .data = RENESAS_GEN2_QUIRKS },
	{ .compatible = "renesas,sdhi-r8a7794", .data = RENESAS_GEN2_QUIRKS },
	{ .compatible = "renesas,sdhi-r8a7795", .data = RENESAS_GEN3_QUIRKS },
	{ .compatible = "renesas,sdhi-r8a7796", .data = RENESAS_GEN3_QUIRKS },
	{ .compatible = "renesas,sdhi-r8a77965", .data = RENESAS_GEN3_QUIRKS },
	{ .compatible = "renesas,sdhi-r8a77970", .data = RENESAS_GEN3_QUIRKS },
	{ .compatible = "renesas,sdhi-r8a77995", .data = RENESAS_GEN3_QUIRKS },
	{ /* sentinel */ }
};

static int renesas_sdhi_probe(struct udevice *dev)
{
	u32 quirks = dev_get_driver_data(dev);
	struct fdt_resource reg_res;
	DECLARE_GLOBAL_DATA_PTR;
	int ret;

	if (quirks == RENESAS_GEN2_QUIRKS) {
		ret = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev),
				       "reg", 0, &reg_res);
		if (ret < 0) {
			dev_err(dev, "\"reg\" resource not found, ret=%i\n",
				ret);
			return ret;
		}

		if (fdt_resource_size(&reg_res) == 0x100)
			quirks |= TMIO_SD_CAP_16BIT;
	}

	ret = tmio_sd_probe(dev, quirks);
#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
	if (!ret)
		renesas_sdhi_reset_tuning(dev_get_priv(dev));
#endif
	return ret;
}

U_BOOT_DRIVER(renesas_sdhi) = {
	.name = "renesas-sdhi",
	.id = UCLASS_MMC,
	.of_match = renesas_sdhi_match,
	.bind = tmio_sd_bind,
	.probe = renesas_sdhi_probe,
	.priv_auto_alloc_size = sizeof(struct tmio_sd_priv),
	.platdata_auto_alloc_size = sizeof(struct tmio_sd_plat),
	.ops = &renesas_sdhi_ops,
};
Commit	Line	Data
e94cad93 MV	1	/*
	2	* Copyright (C) 2018 Marek Vasut <[email protected]>
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#include <common.h>
	8	#include <clk.h>
	9	#include <fdtdec.h>
	10	#include <mmc.h>
	11	#include <dm.h>
	12	#include <linux/compat.h>
	13	#include <linux/dma-direction.h>
	14	#include <linux/io.h>
	15	#include <linux/sizes.h>
	16	#include <power/regulator.h>
	17	#include <asm/unaligned.h>
	18
cb0b6b03	19	#include "tmio-common.h"
e94cad93	20
f63968ba MV	21	#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
	22
	23	/* SCC registers */
	24	#define RENESAS_SDHI_SCC_DTCNTL 0x800
	25	#define RENESAS_SDHI_SCC_DTCNTL_TAPEN BIT(0)
	26	#define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16
	27	#define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff
	28	#define RENESAS_SDHI_SCC_TAPSET 0x804
	29	#define RENESAS_SDHI_SCC_DT2FF 0x808
	30	#define RENESAS_SDHI_SCC_CKSEL 0x80c
	31	#define RENESAS_SDHI_SCC_CKSEL_DTSEL BIT(0)
	32	#define RENESAS_SDHI_SCC_RVSCNTL 0x810
	33	#define RENESAS_SDHI_SCC_RVSCNTL_RVSEN BIT(0)
	34	#define RENESAS_SDHI_SCC_RVSREQ 0x814
	35	#define RENESAS_SDHI_SCC_RVSREQ_RVSERR BIT(2)
	36	#define RENESAS_SDHI_SCC_SMPCMP 0x818
	37	#define RENESAS_SDHI_SCC_TMPPORT2 0x81c
	38
	39	#define RENESAS_SDHI_MAX_TAP 3
	40
cb0b6b03	41	static unsigned int renesas_sdhi_init_tuning(struct tmio_sd_priv *priv)
f63968ba MV	42	{
	43	u32 reg;
	44
	45	/* Initialize SCC */
cb0b6b03	46	tmio_sd_writel(priv, 0, TMIO_SD_INFO1);
f63968ba	47
cb0b6b03 MV	48	reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
	49	reg &= ~TMIO_SD_CLKCTL_SCLKEN;
	50	tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
f63968ba MV	51
f63968ba MV	52	/* Set sampling clock selection range */
cb0b6b03	53	tmio_sd_writel(priv, 0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT,
f63968ba MV	54	RENESAS_SDHI_SCC_DTCNTL);
f63968ba MV	55
cb0b6b03	56	reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL);
f63968ba	57	reg \|= RENESAS_SDHI_SCC_DTCNTL_TAPEN;
cb0b6b03	58	tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_DTCNTL);
f63968ba	59
cb0b6b03	60	reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
f63968ba	61	reg \|= RENESAS_SDHI_SCC_CKSEL_DTSEL;
cb0b6b03	62	tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
f63968ba	63
cb0b6b03	64	reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
f63968ba	65	reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
cb0b6b03	66	tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
f63968ba	67
cb0b6b03	68	tmio_sd_writel(priv, 0x300 /* scc_tappos */,
f63968ba MV	69	RENESAS_SDHI_SCC_DT2FF);
f63968ba MV	70
cb0b6b03 MV	71	reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
	72	reg \|= TMIO_SD_CLKCTL_SCLKEN;
	73	tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
f63968ba MV	74
f63968ba MV	75	/* Read TAPNUM */
cb0b6b03	76	return (tmio_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL) >>
f63968ba MV	77	RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
	78	RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK;
	79	}
	80
cb0b6b03	81	static void renesas_sdhi_reset_tuning(struct tmio_sd_priv *priv)
f63968ba MV	82	{
	83	u32 reg;
	84
	85	/* Reset SCC */
cb0b6b03 MV	86	reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
	87	reg &= ~TMIO_SD_CLKCTL_SCLKEN;
	88	tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
f63968ba	89
cb0b6b03	90	reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
f63968ba	91	reg &= ~RENESAS_SDHI_SCC_CKSEL_DTSEL;
cb0b6b03	92	tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
f63968ba	93
cb0b6b03 MV	94	reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
	95	reg \|= TMIO_SD_CLKCTL_SCLKEN;
	96	tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
f63968ba	97
cb0b6b03	98	reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
f63968ba	99	reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
cb0b6b03	100	tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
f63968ba	101
cb0b6b03	102	reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
f63968ba	103	reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
cb0b6b03	104	tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
f63968ba MV	105	}
f63968ba MV	106
cb0b6b03	107	static void renesas_sdhi_prepare_tuning(struct tmio_sd_priv *priv,
f63968ba MV	108	unsigned long tap)
	109	{
	110	/* Set sampling clock position */
cb0b6b03	111	tmio_sd_writel(priv, tap, RENESAS_SDHI_SCC_TAPSET);
f63968ba MV	112	}
f63968ba MV	113
cb0b6b03	114	static unsigned int renesas_sdhi_compare_scc_data(struct tmio_sd_priv *priv)
f63968ba MV	115	{
f63968ba MV	116	/* Get comparison of sampling data */
cb0b6b03	117	return tmio_sd_readl(priv, RENESAS_SDHI_SCC_SMPCMP);
f63968ba MV	118	}
f63968ba MV	119
cb0b6b03	120	static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv,
f63968ba MV	121	unsigned int tap_num, unsigned int taps,
	122	unsigned int smpcmp)
	123	{
	124	unsigned long tap_cnt; /* counter of tuning success */
	125	unsigned long tap_set; /* tap position */
	126	unsigned long tap_start;/* start position of tuning success */
	127	unsigned long tap_end; /* end position of tuning success */
	128	unsigned long ntap; /* temporary counter of tuning success */
	129	unsigned long match_cnt;/* counter of matching data */
	130	unsigned long i;
	131	bool select = false;
	132	u32 reg;
	133
	134	/* Clear SCC_RVSREQ */
cb0b6b03	135	tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
f63968ba MV	136
	137	/* Merge the results */
	138	for (i = 0; i < tap_num * 2; i++) {
	139	if (!(taps & BIT(i))) {
	140	taps &= ~BIT(i % tap_num);
	141	taps &= ~BIT((i % tap_num) + tap_num);
	142	}
	143	if (!(smpcmp & BIT(i))) {
	144	smpcmp &= ~BIT(i % tap_num);
	145	smpcmp &= ~BIT((i % tap_num) + tap_num);
	146	}
	147	}
	148
	149	/*
	150	* Find the longest consecutive run of successful probes. If that
	151	* is more than RENESAS_SDHI_MAX_TAP probes long then use the
	152	* center index as the tap.
	153	*/
	154	tap_cnt = 0;
	155	ntap = 0;
	156	tap_start = 0;
	157	tap_end = 0;
	158	for (i = 0; i < tap_num * 2; i++) {
	159	if (taps & BIT(i))
	160	ntap++;
	161	else {
	162	if (ntap > tap_cnt) {
	163	tap_start = i - ntap;
	164	tap_end = i - 1;
	165	tap_cnt = ntap;
	166	}
	167	ntap = 0;
	168	}
	169	}
	170
	171	if (ntap > tap_cnt) {
	172	tap_start = i - ntap;
	173	tap_end = i - 1;
	174	tap_cnt = ntap;
	175	}
	176
	177	/*
	178	* If all of the TAP is OK, the sampling clock position is selected by
	179	* identifying the change point of data.
	180	*/
	181	if (tap_cnt == tap_num * 2) {
	182	match_cnt = 0;
	183	ntap = 0;
	184	tap_start = 0;
	185	tap_end = 0;
	186	for (i = 0; i < tap_num * 2; i++) {
	187	if (smpcmp & BIT(i))
	188	ntap++;
	189	else {
	190	if (ntap > match_cnt) {
	191	tap_start = i - ntap;
	192	tap_end = i - 1;
	193	match_cnt = ntap;
	194	}
	195	ntap = 0;
	196	}
	197	}
	198	if (ntap > match_cnt) {
	199	tap_start = i - ntap;
200	tap_end = i - 1;
201	match_cnt = ntap;
202	}
203	if (match_cnt)
204	select = true;
205	} else if (tap_cnt >= RENESAS_SDHI_MAX_TAP)
206	select = true;
207
208	if (select)
209	tap_set = ((tap_start + tap_end) / 2) % tap_num;
210	else
211	return -EIO;
212
213	/* Set SCC */
cb0b6b03	214	tmio_sd_writel(priv, tap_set, RENESAS_SDHI_SCC_TAPSET);
f63968ba MV	215
f63968ba MV	216	/* Enable auto re-tuning */
cb0b6b03	217	reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
f63968ba	218	reg \|= RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
cb0b6b03	219	tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
f63968ba MV	220
	221	return 0;
	222	}
	223
	224	int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode)
	225	{
cb0b6b03	226	struct tmio_sd_priv *priv = dev_get_priv(dev);
f63968ba MV	227	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
	228	struct mmc *mmc = upriv->mmc;
	229	unsigned int tap_num;
	230	unsigned int taps = 0, smpcmp = 0;
	231	int i, ret = 0;
	232	u32 caps;
	233
	234	/* Only supported on Renesas RCar */
cb0b6b03	235	if (!(priv->caps & TMIO_SD_CAP_RCAR_UHS))
f63968ba MV	236	return -EINVAL;
	237
	238	/* clock tuning is not needed for upto 52MHz */
	239	if (!((mmc->selected_mode == MMC_HS_200) \|\|
	240	(mmc->selected_mode == UHS_SDR104) \|\|
	241	(mmc->selected_mode == UHS_SDR50)))
	242	return 0;
	243
	244	tap_num = renesas_sdhi_init_tuning(priv);
	245	if (!tap_num)
	246	/* Tuning is not supported */
	247	goto out;
	248
	249	if (tap_num * 2 >= sizeof(taps) * 8) {
	250	dev_err(dev,
	251	"Too many taps, skipping tuning. Please consider updating size of taps field of tmio_mmc_host\n");
	252	goto out;
	253	}
	254
	255	/* Issue CMD19 twice for each tap */
	256	for (i = 0; i < 2 * tap_num; i++) {
	257	renesas_sdhi_prepare_tuning(priv, i % tap_num);
	258
	259	/* Force PIO for the tuning */
	260	caps = priv->caps;
cb0b6b03	261	priv->caps &= ~TMIO_SD_CAP_DMA_INTERNAL;
f63968ba MV	262
	263	ret = mmc_send_tuning(mmc, opcode, NULL);
	264
	265	priv->caps = caps;
	266
	267	if (ret == 0)
	268	taps \|= BIT(i);
	269
	270	ret = renesas_sdhi_compare_scc_data(priv);
	271	if (ret == 0)
	272	smpcmp \|= BIT(i);
	273
	274	mdelay(1);
	275	}
	276
	277	ret = renesas_sdhi_select_tuning(priv, tap_num, taps, smpcmp);
	278
	279	out:
	280	if (ret < 0) {
	281	dev_warn(dev, "Tuning procedure failed\n");
	282	renesas_sdhi_reset_tuning(priv);
	283	}
	284
	285	return ret;
	286	}
	287	#endif
	288
	289	static int renesas_sdhi_set_ios(struct udevice *dev)
	290	{
cb0b6b03	291	int ret = tmio_sd_set_ios(dev);
cf39f3f3 MV	292
	293	mdelay(10);
	294
f63968ba	295	#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
cb0b6b03	296	struct tmio_sd_priv *priv = dev_get_priv(dev);
f63968ba MV	297
	298	renesas_sdhi_reset_tuning(priv);
	299	#endif
	300
	301	return ret;
	302	}
	303
e94cad93	304	static const struct dm_mmc_ops renesas_sdhi_ops = {
cb0b6b03	305	.send_cmd = tmio_sd_send_cmd,
f63968ba	306	.set_ios = renesas_sdhi_set_ios,
cb0b6b03	307	.get_cd = tmio_sd_get_cd,
f63968ba MV	308	#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
	309	.execute_tuning = renesas_sdhi_execute_tuning,
	310	#endif
e94cad93 MV	311	};
e94cad93 MV	312
cb0b6b03	313	#define RENESAS_GEN2_QUIRKS TMIO_SD_CAP_RCAR_GEN2
f98833db	314	#define RENESAS_GEN3_QUIRKS \
cb0b6b03	315	TMIO_SD_CAP_64BIT \| TMIO_SD_CAP_RCAR_GEN3 \| TMIO_SD_CAP_RCAR_UHS
f98833db	316
e94cad93	317	static const struct udevice_id renesas_sdhi_match[] = {
f98833db MV	318	{ .compatible = "renesas,sdhi-r8a7790", .data = RENESAS_GEN2_QUIRKS },
	319	{ .compatible = "renesas,sdhi-r8a7791", .data = RENESAS_GEN2_QUIRKS },
	320	{ .compatible = "renesas,sdhi-r8a7792", .data = RENESAS_GEN2_QUIRKS },
	321	{ .compatible = "renesas,sdhi-r8a7793", .data = RENESAS_GEN2_QUIRKS },
	322	{ .compatible = "renesas,sdhi-r8a7794", .data = RENESAS_GEN2_QUIRKS },
	323	{ .compatible = "renesas,sdhi-r8a7795", .data = RENESAS_GEN3_QUIRKS },
	324	{ .compatible = "renesas,sdhi-r8a7796", .data = RENESAS_GEN3_QUIRKS },
	325	{ .compatible = "renesas,sdhi-r8a77965", .data = RENESAS_GEN3_QUIRKS },
	326	{ .compatible = "renesas,sdhi-r8a77970", .data = RENESAS_GEN3_QUIRKS },
	327	{ .compatible = "renesas,sdhi-r8a77995", .data = RENESAS_GEN3_QUIRKS },
e94cad93 MV	328	{ /* sentinel */ }
	329	};
	330
c769e609 MV	331	static int renesas_sdhi_probe(struct udevice *dev)
	332	{
	333	u32 quirks = dev_get_driver_data(dev);
7cf7ef81 MV	334	struct fdt_resource reg_res;
	335	DECLARE_GLOBAL_DATA_PTR;
	336	int ret;
	337
f98833db MV	338	if (quirks == RENESAS_GEN2_QUIRKS) {
	339	ret = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev),
	340	"reg", 0, &reg_res);
	341	if (ret < 0) {
	342	dev_err(dev, "\"reg\" resource not found, ret=%i\n",
	343	ret);
	344	return ret;
	345	}
7cf7ef81	346
f98833db	347	if (fdt_resource_size(&reg_res) == 0x100)
cb0b6b03	348	quirks \|= TMIO_SD_CAP_16BIT;
f98833db	349	}
c769e609	350
cb0b6b03	351	ret = tmio_sd_probe(dev, quirks);
f63968ba MV	352	#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
	353	if (!ret)
	354	renesas_sdhi_reset_tuning(dev_get_priv(dev));
	355	#endif
	356	return ret;
c769e609 MV	357	}
c769e609 MV	358
e94cad93 MV	359	U_BOOT_DRIVER(renesas_sdhi) = {
	360	.name = "renesas-sdhi",
	361	.id = UCLASS_MMC,
	362	.of_match = renesas_sdhi_match,
cb0b6b03	363	.bind = tmio_sd_bind,
c769e609	364	.probe = renesas_sdhi_probe,
cb0b6b03 MV	365	.priv_auto_alloc_size = sizeof(struct tmio_sd_priv),
cb0b6b03 MV	366	.platdata_auto_alloc_size = sizeof(struct tmio_sd_plat),
e94cad93 MV	367	.ops = &renesas_sdhi_ops,
e94cad93 MV	368	};