[u-boot.git] / board / eNET / eNET.c

/*
 * (C) Copyright 2008
 * Graeme Russ, [email protected].
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/io.h>
#include <asm/arch/sc520.h>
#include <net.h>
#include <netdev.h>

#ifdef CONFIG_HW_WATCHDOG
#include <watchdog.h>
#endif

#include "hardware.h"

DECLARE_GLOBAL_DATA_PTR;

unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;

static void enet_timer_isr(void);
static void enet_toggle_run_led(void);
static void enet_setup_pars(void);

/*
 * Miscellaneous platform dependent initializations
 */
int board_early_init_f(void)
{
	u16 pio_out_cfg = 0x0000;

	/* Configure General Purpose Bus timing */
	writeb(CONFIG_SYS_SC520_GPCSRT, &sc520_mmcr->gpcsrt);
	writeb(CONFIG_SYS_SC520_GPCSPW, &sc520_mmcr->gpcspw);
	writeb(CONFIG_SYS_SC520_GPCSOFF, &sc520_mmcr->gpcsoff);
	writeb(CONFIG_SYS_SC520_GPRDW, &sc520_mmcr->gprdw);
	writeb(CONFIG_SYS_SC520_GPRDOFF, &sc520_mmcr->gprdoff);
	writeb(CONFIG_SYS_SC520_GPWRW, &sc520_mmcr->gpwrw);
	writeb(CONFIG_SYS_SC520_GPWROFF, &sc520_mmcr->gpwroff);

	/* Configure Programmable Input/Output Pins */
	writew(CONFIG_SYS_SC520_PIODIR15_0, &sc520_mmcr->piodir15_0);
	writew(CONFIG_SYS_SC520_PIODIR31_16, &sc520_mmcr->piodir31_16);
	writew(CONFIG_SYS_SC520_PIOPFS31_16, &sc520_mmcr->piopfs31_16);
	writew(CONFIG_SYS_SC520_PIOPFS15_0, &sc520_mmcr->piopfs15_0);
	writeb(CONFIG_SYS_SC520_CSPFS, &sc520_mmcr->cspfs);
	writeb(CONFIG_SYS_SC520_CLKSEL, &sc520_mmcr->clksel);

	/*
	 * Turn off top board
	 * Set StrataFlash chips to 16-bit width
	 * Set StrataFlash chips to normal (non reset/power down) mode
	 */
	pio_out_cfg |= CONFIG_SYS_ENET_TOP_BRD_PWR;
	pio_out_cfg |= CONFIG_SYS_ENET_SF_WIDTH;
	pio_out_cfg |= CONFIG_SYS_ENET_SF1_MODE;
	pio_out_cfg |= CONFIG_SYS_ENET_SF2_MODE;
	writew(pio_out_cfg, &sc520_mmcr->pioset15_0);

	/* Turn off auxiliary power output */
	writew(CONFIG_SYS_ENET_AUX_PWR, &sc520_mmcr->pioclr15_0);

	/* Clear FPGA program mode */
	writew(CONFIG_SYS_ENET_FPGA_PROG, &sc520_mmcr->pioset31_16);

	enet_setup_pars();

	/* Disable Watchdog */
	writew(0x3333, &sc520_mmcr->wdtmrctl);
	writew(0xcccc, &sc520_mmcr->wdtmrctl);
	writew(0x0000, &sc520_mmcr->wdtmrctl);

	/* Chip Select Configuration */
	writew(CONFIG_SYS_SC520_BOOTCS_CTRL, &sc520_mmcr->bootcsctl);
	writew(CONFIG_SYS_SC520_ROMCS1_CTRL, &sc520_mmcr->romcs1ctl);
	writew(CONFIG_SYS_SC520_ROMCS2_CTRL, &sc520_mmcr->romcs2ctl);

	writeb(CONFIG_SYS_SC520_ADDDECCTL, &sc520_mmcr->adddecctl);
	writeb(CONFIG_SYS_SC520_UART1CTL, &sc520_mmcr->uart1ctl);
	writeb(CONFIG_SYS_SC520_UART2CTL, &sc520_mmcr->uart2ctl);

	writeb(CONFIG_SYS_SC520_SYSARBCTL, &sc520_mmcr->sysarbctl);
	writew(CONFIG_SYS_SC520_SYSARBMENB, &sc520_mmcr->sysarbmenb);

	/* enable posted-writes */
	writeb(CONFIG_SYS_SC520_HBCTL, &sc520_mmcr->hbctl);

	return 0;
}

static void enet_setup_pars(void)
{
	/*
	 * PARs 11 and 12 are 2MB SRAM @ 0x19000000
	 *
	 * These are setup now because older version of U-Boot have them
	 * mapped to a different PAR which gets clobbered which prevents
	 * using SRAM for warm-booting a new image
	 */
	writel(CONFIG_SYS_SC520_SRAM1_PAR, &sc520_mmcr->par[11]);
	writel(CONFIG_SYS_SC520_SRAM2_PAR, &sc520_mmcr->par[12]);

	/* PARs 0 and 1 are Compact Flash slots (4kB each) */
	writel(CONFIG_SYS_SC520_CF1_PAR, &sc520_mmcr->par[0]);
	writel(CONFIG_SYS_SC520_CF2_PAR, &sc520_mmcr->par[1]);

	/* PAR 2 is used for Cache-As-RAM */

	/*
	 * PARs 5 through 8 are additional NS16550 UARTS
	 * 8 bytes each @ 0x013f8, 0x012f8, 0x011f8 and 0x010f8
	 */
	writel(CONFIG_SYS_SC520_UARTA_PAR, &sc520_mmcr->par[5]);
	writel(CONFIG_SYS_SC520_UARTB_PAR, &sc520_mmcr->par[6]);
	writel(CONFIG_SYS_SC520_UARTC_PAR, &sc520_mmcr->par[7]);
	writel(CONFIG_SYS_SC520_UARTD_PAR, &sc520_mmcr->par[8]);

	/* PARs 9 and 10 are 32MB StrataFlash @ 0x10000000 */
	writel(CONFIG_SYS_SC520_SF1_PAR, &sc520_mmcr->par[9]);
	writel(CONFIG_SYS_SC520_SF2_PAR, &sc520_mmcr->par[10]);

	/* PAR 13 is 4kB DPRAM @ 0x18100000 (implemented in FPGA) */
	writel(CONFIG_SYS_SC520_DPRAM_PAR, &sc520_mmcr->par[13]);

	/*
	 * PAR 14 is Low Level I/O (LEDs, Hex Switches etc)
	 * Already configured in board_init16 (eNET_start16.S)
	 *
	 * PAR 15 is Boot ROM
	 * Already configured in board_init16 (eNET_start16.S)
	 */
}


int board_early_init_r(void)
{
	/* CPU Speed to 100MHz */
	gd->cpu_clk = 100000000;

	/* Crystal is 33.000MHz */
	gd->bus_clk = 33000000;

	return 0;
}

void show_boot_progress(int val)
{
	uchar led_mask;

	led_mask = 0x00;

	if (val < 0)
		led_mask |= LED_ERR_BITMASK;

	led_mask |= (uchar)(val & 0x001f);
	outb(led_mask, LED_LATCH_ADDRESS);
}


int last_stage_init(void)
{
	outb(0x00, LED_LATCH_ADDRESS);

	register_timer_isr(enet_timer_isr);

	printf("Serck Controls eNET\n");

	return 0;
}

ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
{
	if (banknum == 0) {	/* non-CFI boot flash */
		info->portwidth = FLASH_CFI_8BIT;
		info->chipwidth = FLASH_CFI_BY8;
		info->interface = FLASH_CFI_X8;
		return 1;
	} else {
		return 0;
	}
}

int board_eth_init(bd_t *bis)
{
	return pci_eth_init(bis);
}

void setup_pcat_compatibility()
{
	/* disable global interrupt mode */
	writeb(0x40, &sc520_mmcr->picicr);

	/* set all irqs to edge */
	writeb(0x00, &sc520_mmcr->pic_mode[0]);
	writeb(0x00, &sc520_mmcr->pic_mode[1]);
	writeb(0x00, &sc520_mmcr->pic_mode[2]);

	/*
	 *  active low polarity on PIC interrupt pins,
	 *  active high polarity on all other irq pins
	 */
	writew(0x0000, &sc520_mmcr->intpinpol);

	/*
	 * PIT 0 -> IRQ0
	 * RTC -> IRQ8
	 * FP error -> IRQ13
	 * UART1 -> IRQ4
	 * UART2 -> IRQ3
	 */
	writeb(SC520_IRQ0, &sc520_mmcr->pit_int_map[0]);
	writeb(SC520_IRQ8, &sc520_mmcr->rtcmap);
	writeb(SC520_IRQ13, &sc520_mmcr->ferrmap);
	writeb(SC520_IRQ4, &sc520_mmcr->uart_int_map[0]);
	writeb(SC520_IRQ3, &sc520_mmcr->uart_int_map[1]);

	/* Disable all other interrupt sources */
	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[0]);
	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[1]);
	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[2]);
	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[1]);
	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[2]);
	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->ssimap);
	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wdtmap);
	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wpvmap);
	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->icemap);
}

void enet_timer_isr(void)
{
	static long enet_ticks;

	enet_ticks++;

	/* Toggle Watchdog every 100ms */
	if ((enet_ticks % 100) == 0)
		hw_watchdog_reset();

	/* Toggle Run LED every 500ms */
	if ((enet_ticks % 500) == 0)
		enet_toggle_run_led();
}

void hw_watchdog_reset(void)
{
	/* Watchdog Reset must be atomic */
	long flag = disable_interrupts();

	if (sc520_mmcr->piodata15_0 & WATCHDOG_PIO_BIT)
		sc520_mmcr->pioclr15_0 = WATCHDOG_PIO_BIT;
	else
		sc520_mmcr->pioset15_0 = WATCHDOG_PIO_BIT;

	if (flag)
		enable_interrupts();
}

void enet_toggle_run_led(void)
{
	unsigned char leds_state = inb(LED_LATCH_ADDRESS);
	if (leds_state & LED_RUN_BITMASK)
		outb(leds_state & ~LED_RUN_BITMASK, LED_LATCH_ADDRESS);
	else
		outb(leds_state | LED_RUN_BITMASK, LED_LATCH_ADDRESS);
}
Commit	Line	Data
c620c01e GR	1	/*
	2	* (C) Copyright 2008
	3	* Graeme Russ, [email protected].
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
	25	#include <asm/io.h>
3c7db1be	26	#include <asm/arch/sc520.h>
8fd80563 GR	27	#include <net.h>
8fd80563 GR	28	#include <netdev.h>
c620c01e GR	29
	30	#ifdef CONFIG_HW_WATCHDOG
	31	#include <watchdog.h>
	32	#endif
	33
	34	#include "hardware.h"
	35
	36	DECLARE_GLOBAL_DATA_PTR;
	37
e9bf8877 GR	38	unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
e9bf8877 GR	39
880c59e5 GR	40	static void enet_timer_isr(void);
880c59e5 GR	41	static void enet_toggle_run_led(void);
c083e4ba	42	static void enet_setup_pars(void);
880c59e5	43
c620c01e GR	44	/*
	45	* Miscellaneous platform dependent initializations
	46	*/
1c409bc7	47	int board_early_init_f(void)
c620c01e	48	{
420c7c05 GR	49	u16 pio_out_cfg = 0x0000;
	50
	51	/* Configure General Purpose Bus timing */
	52	writeb(CONFIG_SYS_SC520_GPCSRT, &sc520_mmcr->gpcsrt);
	53	writeb(CONFIG_SYS_SC520_GPCSPW, &sc520_mmcr->gpcspw);
	54	writeb(CONFIG_SYS_SC520_GPCSOFF, &sc520_mmcr->gpcsoff);
	55	writeb(CONFIG_SYS_SC520_GPRDW, &sc520_mmcr->gprdw);
	56	writeb(CONFIG_SYS_SC520_GPRDOFF, &sc520_mmcr->gprdoff);
	57	writeb(CONFIG_SYS_SC520_GPWRW, &sc520_mmcr->gpwrw);
	58	writeb(CONFIG_SYS_SC520_GPWROFF, &sc520_mmcr->gpwroff);
	59
	60	/* Configure Programmable Input/Output Pins */
	61	writew(CONFIG_SYS_SC520_PIODIR15_0, &sc520_mmcr->piodir15_0);
	62	writew(CONFIG_SYS_SC520_PIODIR31_16, &sc520_mmcr->piodir31_16);
	63	writew(CONFIG_SYS_SC520_PIOPFS31_16, &sc520_mmcr->piopfs31_16);
	64	writew(CONFIG_SYS_SC520_PIOPFS15_0, &sc520_mmcr->piopfs15_0);
	65	writeb(CONFIG_SYS_SC520_CSPFS, &sc520_mmcr->cspfs);
	66	writeb(CONFIG_SYS_SC520_CLKSEL, &sc520_mmcr->clksel);
	67
	68	/*
	69	* Turn off top board
	70	* Set StrataFlash chips to 16-bit width
	71	* Set StrataFlash chips to normal (non reset/power down) mode
	72	*/
	73	pio_out_cfg \|= CONFIG_SYS_ENET_TOP_BRD_PWR;
	74	pio_out_cfg \|= CONFIG_SYS_ENET_SF_WIDTH;
	75	pio_out_cfg \|= CONFIG_SYS_ENET_SF1_MODE;
	76	pio_out_cfg \|= CONFIG_SYS_ENET_SF2_MODE;
	77	writew(pio_out_cfg, &sc520_mmcr->pioset15_0);
	78
	79	/* Turn off auxiliary power output */
	80	writew(CONFIG_SYS_ENET_AUX_PWR, &sc520_mmcr->pioclr15_0);
	81
	82	/* Clear FPGA program mode */
	83	writew(CONFIG_SYS_ENET_FPGA_PROG, &sc520_mmcr->pioset31_16);
	84
c083e4ba	85	enet_setup_pars();
c620c01e GR	86
c620c01e GR	87	/* Disable Watchdog */
64a0a499 GR	88	writew(0x3333, &sc520_mmcr->wdtmrctl);
	89	writew(0xcccc, &sc520_mmcr->wdtmrctl);
	90	writew(0x0000, &sc520_mmcr->wdtmrctl);
c620c01e GR	91
c620c01e GR	92	/* Chip Select Configuration */
420c7c05 GR	93	writew(CONFIG_SYS_SC520_BOOTCS_CTRL, &sc520_mmcr->bootcsctl);
	94	writew(CONFIG_SYS_SC520_ROMCS1_CTRL, &sc520_mmcr->romcs1ctl);
	95	writew(CONFIG_SYS_SC520_ROMCS2_CTRL, &sc520_mmcr->romcs2ctl);
64a0a499	96
420c7c05 GR	97	writeb(CONFIG_SYS_SC520_ADDDECCTL, &sc520_mmcr->adddecctl);
	98	writeb(CONFIG_SYS_SC520_UART1CTL, &sc520_mmcr->uart1ctl);
	99	writeb(CONFIG_SYS_SC520_UART2CTL, &sc520_mmcr->uart2ctl);
870847f5	100
420c7c05 GR	101	writeb(CONFIG_SYS_SC520_SYSARBCTL, &sc520_mmcr->sysarbctl);
420c7c05 GR	102	writew(CONFIG_SYS_SC520_SYSARBMENB, &sc520_mmcr->sysarbmenb);
c620c01e	103
870847f5	104	/* enable posted-writes */
420c7c05	105	writeb(CONFIG_SYS_SC520_HBCTL, &sc520_mmcr->hbctl);
870847f5	106
1c409bc7 GR	107	return 0;
	108	}
	109
c083e4ba GR	110	static void enet_setup_pars(void)
	111	{
	112	/*
	113	* PARs 11 and 12 are 2MB SRAM @ 0x19000000
	114	*
	115	* These are setup now because older version of U-Boot have them
	116	* mapped to a different PAR which gets clobbered which prevents
	117	* using SRAM for warm-booting a new image
	118	*/
	119	writel(CONFIG_SYS_SC520_SRAM1_PAR, &sc520_mmcr->par[11]);
	120	writel(CONFIG_SYS_SC520_SRAM2_PAR, &sc520_mmcr->par[12]);
	121
	122	/* PARs 0 and 1 are Compact Flash slots (4kB each) */
	123	writel(CONFIG_SYS_SC520_CF1_PAR, &sc520_mmcr->par[0]);
	124	writel(CONFIG_SYS_SC520_CF2_PAR, &sc520_mmcr->par[1]);
	125
	126	/* PAR 2 is used for Cache-As-RAM */
	127
	128	/*
	129	* PARs 5 through 8 are additional NS16550 UARTS
	130	* 8 bytes each @ 0x013f8, 0x012f8, 0x011f8 and 0x010f8
	131	*/
	132	writel(CONFIG_SYS_SC520_UARTA_PAR, &sc520_mmcr->par[5]);
	133	writel(CONFIG_SYS_SC520_UARTB_PAR, &sc520_mmcr->par[6]);
	134	writel(CONFIG_SYS_SC520_UARTC_PAR, &sc520_mmcr->par[7]);
	135	writel(CONFIG_SYS_SC520_UARTD_PAR, &sc520_mmcr->par[8]);
	136
	137	/* PARs 9 and 10 are 32MB StrataFlash @ 0x10000000 */
	138	writel(CONFIG_SYS_SC520_SF1_PAR, &sc520_mmcr->par[9]);
	139	writel(CONFIG_SYS_SC520_SF2_PAR, &sc520_mmcr->par[10]);
	140
	141	/* PAR 13 is 4kB DPRAM @ 0x18100000 (implemented in FPGA) */
	142	writel(CONFIG_SYS_SC520_DPRAM_PAR, &sc520_mmcr->par[13]);
	143
	144	/*
	145	* PAR 14 is Low Level I/O (LEDs, Hex Switches etc)
	146	* Already configured in board_init16 (eNET_start16.S)
	147	*
	148	* PAR 15 is Boot ROM
	149	* Already configured in board_init16 (eNET_start16.S)
	150	*/
	151	}
	152
	153
1c409bc7 GR	154	int board_early_init_r(void)
	155	{
	156	/* CPU Speed to 100MHz */
	157	gd->cpu_clk = 100000000;
	158
c620c01e GR	159	/* Crystal is 33.000MHz */
	160	gd->bus_clk = 33000000;
	161
	162	return 0;
	163	}
	164
c620c01e GR	165	void show_boot_progress(int val)
	166	{
	167	uchar led_mask;
	168
	169	led_mask = 0x00;
	170
	171	if (val < 0)
	172	led_mask \|= LED_ERR_BITMASK;
	173
	174	led_mask \|= (uchar)(val & 0x001f);
	175	outb(led_mask, LED_LATCH_ADDRESS);
	176	}
	177
	178
	179	int last_stage_init(void)
	180	{
880c59e5 GR	181	outb(0x00, LED_LATCH_ADDRESS);
880c59e5 GR	182
cfbe8615	183	register_timer_isr(enet_timer_isr);
880c59e5	184
c620c01e GR	185	printf("Serck Controls eNET\n");
	186
	187	return 0;
	188	}
	189
cfbe8615	190	ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
c620c01e GR	191	{
	192	if (banknum == 0) { /* non-CFI boot flash */
	193	info->portwidth = FLASH_CFI_8BIT;
	194	info->chipwidth = FLASH_CFI_BY8;
	195	info->interface = FLASH_CFI_X8;
	196	return 1;
cfbe8615	197	} else {
c620c01e	198	return 0;
cfbe8615	199	}
c620c01e	200	}
8fd80563 GR	201
	202	int board_eth_init(bd_t *bis)
	203	{
	204	return pci_eth_init(bis);
	205	}
4a4c31ae GR	206
	207	void setup_pcat_compatibility()
	208	{
	209	/* disable global interrupt mode */
	210	writeb(0x40, &sc520_mmcr->picicr);
	211
	212	/* set all irqs to edge */
	213	writeb(0x00, &sc520_mmcr->pic_mode[0]);
	214	writeb(0x00, &sc520_mmcr->pic_mode[1]);
	215	writeb(0x00, &sc520_mmcr->pic_mode[2]);
	216
	217	/*
	218	* active low polarity on PIC interrupt pins,
	219	* active high polarity on all other irq pins
	220	*/
63a90bfb	221	writew(0x0000, &sc520_mmcr->intpinpol);
4a4c31ae	222
d881ea53 GR	223	/*
	224	* PIT 0 -> IRQ0
	225	* RTC -> IRQ8
	226	* FP error -> IRQ13
	227	* UART1 -> IRQ4
	228	* UART2 -> IRQ3
	229	*/
4a4c31ae GR	230	writeb(SC520_IRQ0, &sc520_mmcr->pit_int_map[0]);
	231	writeb(SC520_IRQ8, &sc520_mmcr->rtcmap);
	232	writeb(SC520_IRQ13, &sc520_mmcr->ferrmap);
d881ea53 GR	233	writeb(SC520_IRQ4, &sc520_mmcr->uart_int_map[0]);
d881ea53 GR	234	writeb(SC520_IRQ3, &sc520_mmcr->uart_int_map[1]);
4a4c31ae GR	235
	236	/* Disable all other interrupt sources */
	237	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[0]);
	238	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[1]);
	239	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[2]);
	240	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[1]);
	241	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[2]);
4a4c31ae GR	242	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->ssimap);
	243	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wdtmap);
	244	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wpvmap);
	245	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->icemap);
	246	}
880c59e5 GR	247
	248	void enet_timer_isr(void)
	249	{
63a90bfb	250	static long enet_ticks;
880c59e5 GR	251
	252	enet_ticks++;
	253
	254	/* Toggle Watchdog every 100ms */
	255	if ((enet_ticks % 100) == 0)
	256	hw_watchdog_reset();
	257
	258	/* Toggle Run LED every 500ms */
	259	if ((enet_ticks % 500) == 0)
	260	enet_toggle_run_led();
	261	}
	262
	263	void hw_watchdog_reset(void)
	264	{
	265	/* Watchdog Reset must be atomic */
	266	long flag = disable_interrupts();
	267
	268	if (sc520_mmcr->piodata15_0 & WATCHDOG_PIO_BIT)
	269	sc520_mmcr->pioclr15_0 = WATCHDOG_PIO_BIT;
	270	else
	271	sc520_mmcr->pioset15_0 = WATCHDOG_PIO_BIT;
	272
	273	if (flag)
	274	enable_interrupts();
	275	}
	276
	277	void enet_toggle_run_led(void)
	278	{
63a90bfb	279	unsigned char leds_state = inb(LED_LATCH_ADDRESS);
880c59e5	280	if (leds_state & LED_RUN_BITMASK)
63a90bfb	281	outb(leds_state & ~LED_RUN_BITMASK, LED_LATCH_ADDRESS);
880c59e5 GR	282	else
	283	outb(leds_state \| LED_RUN_BITMASK, LED_LATCH_ADDRESS);
	284	}