[u-boot.git] / include / configs / MPC8541CDS.h

/*
 * Copyright 2004 Freescale Semiconductor.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * mpc8541cds board configuration file
 *
 * Please refer to doc/README.mpc85xxcds for more info.
 *
 */
#ifndef __CONFIG_H
#define __CONFIG_H

/* High Level Configuration Options */
#define CONFIG_BOOKE		1	/* BOOKE */
#define CONFIG_E500		1	/* BOOKE e500 family */
#define CONFIG_MPC85xx		1	/* MPC8540/60/55/41 */
#define CONFIG_CPM2		1	/* has CPM2 */
#define CONFIG_MPC8541		1	/* MPC8541 specific */
#define CONFIG_MPC8541CDS	1	/* MPC8541CDS board specific */

#define CONFIG_PCI
#define CONFIG_TSEC_ENET		/* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_DLL			/* possible DLL fix needed */
#undef CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */

#define CONFIG_DDR_ECC			/* only for ECC DDR module */
#define CONFIG_MEM_INIT_VALUE		0xDeadBeef

#define CONFIG_FSL_LAW		1	/* Use common FSL init code */

#define CONFIG_FSL_VIA
#define CONFIG_FSL_CDS_EEPROM

/*
 * When initializing flash, if we cannot find the manufacturer ID,
 * assume this is the AMD flash associated with the CDS board.
 * This allows booting from a promjet.
 */
#define CONFIG_ASSUME_AMD_FLASH

#define MPC85xx_DDR_SDRAM_CLK_CNTL	/* 85xx has clock control reg */

#ifndef __ASSEMBLY__
extern unsigned long get_clock_freq(void);
#endif
#define CONFIG_SYS_CLK_FREQ	get_clock_freq() /* sysclk for MPC85xx */

/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE			    /* toggle L2 cache	*/
#define CONFIG_BTB			    /* toggle branch predition */
#define CONFIG_ADDR_STREAMING		    /* toggle addr streaming   */

#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */

#undef	CFG_DRAM_TEST			/* memory test, takes time */
#define CFG_MEMTEST_START	0x00200000	/* memtest works on */
#define CFG_MEMTEST_END		0x00400000

/*
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 */
#define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
#define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */

/*
 * DDR Setup
 */
#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE

#define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */

/*
 * Make sure required options are set
 */
#ifndef CONFIG_SPD_EEPROM
#error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
#endif

#undef CONFIG_CLOCKS_IN_MHZ


/*
 * Local Bus Definitions
 */

/*
 * FLASH on the Local Bus
 * Two banks, 8M each, using the CFI driver.
 * Boot from BR0/OR0 bank at 0xff00_0000
 * Alternate BR1/OR1 bank at 0xff80_0000
 *
 * BR0, BR1:
 *    Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
 *    Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
 *    Port Size = 16 bits = BRx[19:20] = 10
 *    Use GPCM = BRx[24:26] = 000
 *    Valid = BRx[31] = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001    BR0
 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001    BR1
 *
 * OR0, OR1:
 *    Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
 *    Reserved ORx[17:18] = 11, confusion here?
 *    CSNT = ORx[20] = 1
 *    ACS = half cycle delay = ORx[21:22] = 11
 *    SCY = 6 = ORx[24:27] = 0110
 *    TRLX = use relaxed timing = ORx[29] = 1
 *    EAD = use external address latch delay = OR[31] = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    ORx
 */

#define CFG_FLASH_BASE		0xff000000	/* start of FLASH 8M */

#define CFG_BR0_PRELIM		0xff801001
#define CFG_BR1_PRELIM		0xff001001

#define	CFG_OR0_PRELIM		0xff806e65
#define	CFG_OR1_PRELIM		0xff806e65

#define CFG_FLASH_BANKS_LIST	{0xff800000, CFG_FLASH_BASE}
#define CFG_MAX_FLASH_BANKS	2		/* number of banks */
#define CFG_MAX_FLASH_SECT	128		/* sectors per device */
#undef	CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */

#define CFG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
#define CFG_FLASH_EMPTY_INFO


/*
 * SDRAM on the Local Bus
 */
#define CFG_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
#define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */

/*
 * Base Register 2 and Option Register 2 configure SDRAM.
 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
 *
 * For BR2, need:
 *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 *    port-size = 32-bits = BR2[19:20] = 11
 *    no parity checking = BR2[21:22] = 00
 *    SDRAM for MSEL = BR2[24:26] = 011
 *    Valid = BR[31] = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 *
 * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
 * FIXME: the top 17 bits of BR2.
 */

#define CFG_BR2_PRELIM          0xf0001861

/*
 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
 *
 * For OR2, need:
 *    64MB mask for AM, OR2[0:7] = 1111 1100
 *		   XAM, OR2[17:18] = 11
 *    9 columns OR2[19-21] = 010
 *    13 rows   OR2[23-25] = 100
 *    EAD set for extra time OR[31] = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 */

#define CFG_OR2_PRELIM		0xfc006901

#define CFG_LBC_LCRR		0x00030004    /* LB clock ratio reg */
#define CFG_LBC_LBCR		0x00000000    /* LB config reg */
#define CFG_LBC_LSRT		0x20000000  /* LB sdram refresh timer */
#define CFG_LBC_MRTPR		0x00000000  /* LB refresh timer prescal*/

/*
 * LSDMR masks
 */
#define CFG_LBC_LSDMR_RFEN	(1 << (31 -  1))
#define CFG_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
#define CFG_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
#define CFG_LBC_LSDMR_RFCR16	(7 << (31 - 16))
#define CFG_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
#define CFG_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
#define CFG_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
#define CFG_LBC_LSDMR_BL8	(1 << (31 - 23))
#define CFG_LBC_LSDMR_WRC4	(0 << (31 - 27))
#define CFG_LBC_LSDMR_CL3	(3 << (31 - 31))

#define CFG_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
#define CFG_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
#define CFG_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
#define CFG_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
#define CFG_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
#define CFG_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
#define CFG_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
#define CFG_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))

/*
 * Common settings for all Local Bus SDRAM commands.
 * At run time, either BSMA1516 (for CPU 1.1)
 *                  or BSMA1617 (for CPU 1.0) (old)
 * is OR'ed in too.
 */
#define CFG_LBC_LSDMR_COMMON	( CFG_LBC_LSDMR_RFCR16		\
				| CFG_LBC_LSDMR_PRETOACT7	\
				| CFG_LBC_LSDMR_ACTTORW7	\
				| CFG_LBC_LSDMR_BL8		\
				| CFG_LBC_LSDMR_WRC4		\
				| CFG_LBC_LSDMR_CL3		\
				| CFG_LBC_LSDMR_RFEN		\
				)

/*
 * The CADMUS registers are connected to CS3 on CDS.
 * The new memory map places CADMUS at 0xf8000000.
 *
 * For BR3, need:
 *    Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
 *    port-size = 8-bits  = BR[19:20] = 01
 *    no parity checking  = BR[21:22] = 00
 *    GPMC for MSEL       = BR[24:26] = 000
 *    Valid               = BR[31]    = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
 *
 * For OR3, need:
 *    1 MB mask for AM,   OR[0:16]  = 1111 1111 1111 0000 0
 *    disable buffer ctrl OR[19]    = 0
 *    CSNT                OR[20]    = 1
 *    ACS                 OR[21:22] = 11
 *    XACS                OR[23]    = 1
 *    SCY 15 wait states  OR[24:27] = 1111	max is suboptimal but safe
 *    SETA                OR[28]    = 0
 *    TRLX                OR[29]    = 1
 *    EHTR                OR[30]    = 1
 *    EAD extra time      OR[31]    = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
 */

#define CONFIG_FSL_CADMUS

#define CADMUS_BASE_ADDR 0xf8000000
#define CFG_BR3_PRELIM   0xf8000801
#define CFG_OR3_PRELIM   0xfff00ff7

#define CONFIG_L1_INIT_RAM
#define CFG_INIT_RAM_LOCK	1
#define CFG_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
#define CFG_INIT_RAM_END	0x4000	    /* End of used area in RAM */

#define CFG_GBL_DATA_SIZE	128	    /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

#define CFG_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */

/* Serial Port */
#define CONFIG_CONS_INDEX     2
#undef	CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_NS16550
#define CFG_NS16550_SERIAL
#define CFG_NS16550_REG_SIZE    1
#define CFG_NS16550_CLK		get_bus_freq(0)

#define CFG_BAUDRATE_TABLE  \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}

#define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
#define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)

/* Use the HUSH parser */
#define CFG_HUSH_PARSER
#ifdef  CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif

/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT		1
#define CONFIG_OF_BOARD_SETUP		1
#define CONFIG_OF_STDOUT_VIA_ALIAS	1

/*
 * I2C
 */
#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
#define CONFIG_HARD_I2C		/* I2C with hardware support*/
#undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
#define CFG_I2C_EEPROM_ADDR	0x57
#define CFG_I2C_SLAVE		0x7F
#define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
#define CFG_I2C_OFFSET		0x3000

/*
 * General PCI
 * Memory space is mapped 1-1, but I/O space must start from 0.
 */
#define CFG_PCI1_MEM_BASE	0x80000000
#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
#define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
#define CFG_PCI1_IO_BASE	0x00000000
#define CFG_PCI1_IO_PHYS	0xe2000000
#define CFG_PCI1_IO_SIZE	0x100000	/* 1M */

#define CFG_PCI2_MEM_BASE	0xa0000000
#define CFG_PCI2_MEM_PHYS	CFG_PCI2_MEM_BASE
#define CFG_PCI2_MEM_SIZE	0x20000000	/* 512M */
#define CFG_PCI2_IO_BASE	0x00000000
#define CFG_PCI2_IO_PHYS	0xe2100000
#define CFG_PCI2_IO_SIZE	0x100000	/* 1M */

#ifdef CONFIG_LEGACY
#define BRIDGE_ID 17
#define VIA_ID 2
#else
#define BRIDGE_ID 28
#define VIA_ID 4
#endif

#if defined(CONFIG_PCI)

#define CONFIG_MPC85XX_PCI2
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP			/* do pci plug-and-play */

#undef CONFIG_EEPRO100
#undef CONFIG_TULIP

#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
#define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */

#endif	/* CONFIG_PCI */


#if defined(CONFIG_TSEC_ENET)

#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI	1
#endif

#define CONFIG_MII		1	/* MII PHY management */
#define CONFIG_TSEC1	1
#define CONFIG_TSEC1_NAME	"TSEC0"
#define CONFIG_TSEC2	1
#define CONFIG_TSEC2_NAME	"TSEC1"
#define TSEC1_PHY_ADDR		0
#define TSEC2_PHY_ADDR		1
#define TSEC1_PHYIDX		0
#define TSEC2_PHYIDX		0
#define TSEC1_FLAGS		TSEC_GIGABIT
#define TSEC2_FLAGS		TSEC_GIGABIT

/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME		"TSEC0"

#endif	/* CONFIG_TSEC_ENET */

/*
 * Environment
 */
#define CFG_ENV_IS_IN_FLASH	1
#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
#define CFG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
#define CFG_ENV_SIZE		0x2000

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_ELF

#if defined(CONFIG_PCI)
    #define CONFIG_CMD_PCI
#endif


#undef CONFIG_WATCHDOG			/* watchdog disabled */

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory	*/
#define CONFIG_CMDLINE_EDITING		/* Command-line editing */
#define CFG_LOAD_ADDR	0x2000000	/* default load address */
#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
#else
#define CFG_CBSIZE	256		/* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args */
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM	0x02		/* Software reboot */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
#endif

/*
 * Environment Configuration
 */

/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR   00:E0:0C:00:00:FD
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
#define CONFIG_HAS_ETH2
#define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
#endif

#define CONFIG_IPADDR    192.168.1.253

#define CONFIG_HOSTNAME  unknown
#define CONFIG_ROOTPATH  /nfsroot
#define CONFIG_BOOTFILE  your.uImage

#define CONFIG_SERVERIP  192.168.1.1
#define CONFIG_GATEWAYIP 192.168.1.1
#define CONFIG_NETMASK   255.255.255.0

#define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/

#define CONFIG_BOOTDELAY 10       /* -1 disables auto-boot */
#undef  CONFIG_BOOTARGS           /* the boot command will set bootargs*/

#define CONFIG_BAUDRATE	115200

#define	CONFIG_EXTRA_ENV_SETTINGS				        \
   "netdev=eth0\0"                                                      \
   "consoledev=ttyS1\0"                                                 \
   "ramdiskaddr=600000\0"                                               \
   "ramdiskfile=your.ramdisk.u-boot\0"					\
   "fdtaddr=400000\0"							\
   "fdtfile=your.fdt.dtb\0"

#define CONFIG_NFSBOOTCOMMAND	                                        \
   "setenv bootargs root=/dev/nfs rw "                                  \
      "nfsroot=$serverip:$rootpath "                                    \
      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
      "console=$consoledev,$baudrate $othbootargs;"                     \
   "tftp $loadaddr $bootfile;"                                          \
   "tftp $fdtaddr $fdtfile;"						\
   "bootm $loadaddr - $fdtaddr"

#define CONFIG_RAMBOOTCOMMAND \
   "setenv bootargs root=/dev/ram rw "                                  \
      "console=$consoledev,$baudrate $othbootargs;"                     \
   "tftp $ramdiskaddr $ramdiskfile;"                                    \
   "tftp $loadaddr $bootfile;"                                          \
   "bootm $loadaddr $ramdiskaddr"

#define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND

#endif	/* __CONFIG_H */
Commit	Line	Data
03f5c550 WD	1	/*
	2	* Copyright 2004 Freescale Semiconductor.
	3	*
	4	* See file CREDITS for list of people who contributed to this
	5	* project.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
	21	*/
	22
	23	/*
	24	* mpc8541cds board configuration file
	25	*
	26	* Please refer to doc/README.mpc85xxcds for more info.
	27	*
	28	*/
03f5c550 WD	29	#ifndef __CONFIG_H
	30	#define __CONFIG_H
	31
	32	/* High Level Configuration Options */
	33	#define CONFIG_BOOKE 1 /* BOOKE */
	34	#define CONFIG_E500 1 /* BOOKE e500 family */
	35	#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */
9c4c5ae3	36	#define CONFIG_CPM2 1 /* has CPM2 */
03f5c550 WD	37	#define CONFIG_MPC8541 1 /* MPC8541 specific */
	38	#define CONFIG_MPC8541CDS 1 /* MPC8541CDS board specific */
	39
	40	#define CONFIG_PCI
53677ef1	41	#define CONFIG_TSEC_ENET /* tsec ethernet support */
03f5c550 WD	42	#define CONFIG_ENV_OVERWRITE
03f5c550 WD	43	#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
03f5c550	44	#define CONFIG_DDR_DLL /* possible DLL fix needed */
d9b94f28 JL	45	#undef CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
	46
	47	#define CONFIG_DDR_ECC /* only for ECC DDR module */
	48	#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
	49
2cfaa1aa	50	#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
03f5c550	51
25eedb2c JL	52	#define CONFIG_FSL_VIA
	53	#define CONFIG_FSL_CDS_EEPROM
	54
03f5c550 WD	55	/*
	56	* When initializing flash, if we cannot find the manufacturer ID,
	57	* assume this is the AMD flash associated with the CDS board.
	58	* This allows booting from a promjet.
	59	*/
	60	#define CONFIG_ASSUME_AMD_FLASH
	61
	62	#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */
	63
	64	#ifndef __ASSEMBLY__
	65	extern unsigned long get_clock_freq(void);
	66	#endif
	67	#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */
	68
	69	/*
	70	* These can be toggled for performance analysis, otherwise use default.
	71	*/
53677ef1	72	#define CONFIG_L2_CACHE /* toggle L2 cache */
03f5c550 WD	73	#define CONFIG_BTB /* toggle branch predition */
	74	#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
	75
	76	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
	77
	78	#undef CFG_DRAM_TEST /* memory test, takes time */
	79	#define CFG_MEMTEST_START 0x00200000 /* memtest works on */
	80	#define CFG_MEMTEST_END 0x00400000
	81
03f5c550 WD	82	/*
	83	* Base addresses -- Note these are effective addresses where the
	84	* actual resources get mapped (not physical addresses)
	85	*/
53677ef1	86	#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
03f5c550	87	#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
f69766e4	88	#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
03f5c550 WD	89	#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
03f5c550 WD	90
03f5c550 WD	91	/*
	92	* DDR Setup
	93	*/
	94	#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
	95	#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
	96
	97	#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
	98
	99	/*
	100	* Make sure required options are set
	101	*/
	102	#ifndef CONFIG_SPD_EEPROM
	103	#error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
	104	#endif
	105
7202d43d JL	106	#undef CONFIG_CLOCKS_IN_MHZ
	107
	108
03f5c550	109	/*
7202d43d	110	* Local Bus Definitions
03f5c550	111	*/
7202d43d JL	112
	113	/*
	114	* FLASH on the Local Bus
	115	* Two banks, 8M each, using the CFI driver.
	116	* Boot from BR0/OR0 bank at 0xff00_0000
	117	* Alternate BR1/OR1 bank at 0xff80_0000
	118	*
	119	* BR0, BR1:
	120	* Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
	121	* Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
	122	* Port Size = 16 bits = BRx[19:20] = 10
	123	* Use GPCM = BRx[24:26] = 000
	124	* Valid = BRx[31] = 1
	125	*
	126	* 0 4 8 12 16 20 24 28
	127	* 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
	128	* 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
	129	*
	130	* OR0, OR1:
	131	* Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
	132	* Reserved ORx[17:18] = 11, confusion here?
	133	* CSNT = ORx[20] = 1
	134	* ACS = half cycle delay = ORx[21:22] = 11
	135	* SCY = 6 = ORx[24:27] = 0110
	136	* TRLX = use relaxed timing = ORx[29] = 1
	137	* EAD = use external address latch delay = OR[31] = 1
	138	*
	139	* 0 4 8 12 16 20 24 28
	140	* 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
	141	*/
	142
03f5c550 WD	143	#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 8M */
03f5c550 WD	144
7202d43d JL	145	#define CFG_BR0_PRELIM 0xff801001
7202d43d JL	146	#define CFG_BR1_PRELIM 0xff001001
03f5c550	147
7202d43d JL	148	#define CFG_OR0_PRELIM 0xff806e65
7202d43d JL	149	#define CFG_OR1_PRELIM 0xff806e65
03f5c550 WD	150
	151	#define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE}
	152	#define CFG_MAX_FLASH_BANKS 2 /* number of banks */
	153	#define CFG_MAX_FLASH_SECT 128 /* sectors per device */
	154	#undef CFG_FLASH_CHECKSUM
	155	#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	156	#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	157
53677ef1	158	#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
03f5c550 WD	159
	160	#define CFG_FLASH_CFI_DRIVER
	161	#define CFG_FLASH_CFI
	162	#define CFG_FLASH_EMPTY_INFO
	163
03f5c550 WD	164
03f5c550 WD	165	/*
7202d43d	166	* SDRAM on the Local Bus
03f5c550	167	*/
7202d43d JL	168	#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
7202d43d JL	169	#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
03f5c550 WD	170
	171	/*
	172	* Base Register 2 and Option Register 2 configure SDRAM.
	173	* The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
	174	*
	175	* For BR2, need:
	176	* Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
	177	* port-size = 32-bits = BR2[19:20] = 11
	178	* no parity checking = BR2[21:22] = 00
	179	* SDRAM for MSEL = BR2[24:26] = 011
	180	* Valid = BR[31] = 1
	181	*
	182	* 0 4 8 12 16 20 24 28
	183	* 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
	184	*
	185	* FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
	186	* FIXME: the top 17 bits of BR2.
	187	*/
	188
	189	#define CFG_BR2_PRELIM 0xf0001861
	190
	191	/*
	192	* The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
	193	*
	194	* For OR2, need:
	195	* 64MB mask for AM, OR2[0:7] = 1111 1100
	196	* XAM, OR2[17:18] = 11
	197	* 9 columns OR2[19-21] = 010
	198	* 13 rows OR2[23-25] = 100
	199	* EAD set for extra time OR[31] = 1
	200	*
	201	* 0 4 8 12 16 20 24 28
	202	* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
	203	*/
	204
	205	#define CFG_OR2_PRELIM 0xfc006901
	206
	207	#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */
	208	#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
	209	#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
	210	#define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
	211
	212	/*
	213	* LSDMR masks
	214	*/
	215	#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1))
	216	#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
	217	#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
	218	#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16))
	219	#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
	220	#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
	221	#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
	222	#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23))
	223	#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27))
	224	#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31))
	225
	226	#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
	227	#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
	228	#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
	229	#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
	230	#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
	231	#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
	232	#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
	233	#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
234
235	/*
236	* Common settings for all Local Bus SDRAM commands.
237	* At run time, either BSMA1516 (for CPU 1.1)
238	* or BSMA1617 (for CPU 1.0) (old)
239	* is OR'ed in too.
240	*/
241	#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \
242	\| CFG_LBC_LSDMR_PRETOACT7 \
243	\| CFG_LBC_LSDMR_ACTTORW7 \
244	\| CFG_LBC_LSDMR_BL8 \
245	\| CFG_LBC_LSDMR_WRC4 \
246	\| CFG_LBC_LSDMR_CL3 \
247	\| CFG_LBC_LSDMR_RFEN \
248	)
249
250	/*
251	* The CADMUS registers are connected to CS3 on CDS.
252	* The new memory map places CADMUS at 0xf8000000.
253	*
254	* For BR3, need:
255	* Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
256	* port-size = 8-bits = BR[19:20] = 01
257	* no parity checking = BR[21:22] = 00
258	* GPMC for MSEL = BR[24:26] = 000
259	* Valid = BR[31] = 1
260	*
261	* 0 4 8 12 16 20 24 28
262	* 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
263	*
264	* For OR3, need:
265	* 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
266	* disable buffer ctrl OR[19] = 0
267	* CSNT OR[20] = 1
268	* ACS OR[21:22] = 11
269	* XACS OR[23] = 1
270	* SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
271	* SETA OR[28] = 0
272	* TRLX OR[29] = 1
273	* EHTR OR[30] = 1
274	* EAD extra time OR[31] = 1
275	*
276	* 0 4 8 12 16 20 24 28
277	* 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
278	*/
279
25eedb2c JL	280	#define CONFIG_FSL_CADMUS
25eedb2c JL	281
03f5c550 WD	282	#define CADMUS_BASE_ADDR 0xf8000000
	283	#define CFG_BR3_PRELIM 0xf8000801
	284	#define CFG_OR3_PRELIM 0xfff00ff7
	285
03f5c550	286	#define CONFIG_L1_INIT_RAM
53677ef1	287	#define CFG_INIT_RAM_LOCK 1
03f5c550	288	#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
53677ef1	289	#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
03f5c550	290
53677ef1	291	#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
03f5c550 WD	292	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	293	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	294
53677ef1 WD	295	#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
53677ef1 WD	296	#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
03f5c550 WD	297
	298	/* Serial Port */
	299	#define CONFIG_CONS_INDEX 2
	300	#undef CONFIG_SERIAL_SOFTWARE_FIFO
	301	#define CFG_NS16550
	302	#define CFG_NS16550_SERIAL
	303	#define CFG_NS16550_REG_SIZE 1
	304	#define CFG_NS16550_CLK get_bus_freq(0)
	305
	306	#define CFG_BAUDRATE_TABLE \
	307	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
	308
	309	#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
	310	#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
	311
	312	/* Use the HUSH parser */
	313	#define CFG_HUSH_PARSER
	314	#ifdef CFG_HUSH_PARSER
	315	#define CFG_PROMPT_HUSH_PS2 "> "
	316	#endif
	317
0e16387d	318	/* pass open firmware flat tree */
b90d2549 KG	319	#define CONFIG_OF_LIBFDT 1
	320	#define CONFIG_OF_BOARD_SETUP 1
	321	#define CONFIG_OF_STDOUT_VIA_ALIAS 1
0e16387d	322
20476726 JL	323	/*
	324	* I2C
	325	*/
	326	#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
	327	#define CONFIG_HARD_I2C /* I2C with hardware support*/
03f5c550 WD	328	#undef CONFIG_SOFT_I2C /* I2C bit-banged */
	329	#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
	330	#define CFG_I2C_EEPROM_ADDR 0x57
	331	#define CFG_I2C_SLAVE 0x7F
	332	#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
20476726	333	#define CFG_I2C_OFFSET 0x3000
03f5c550 WD	334
	335	/*
	336	* General PCI
362dd830	337	* Memory space is mapped 1-1, but I/O space must start from 0.
03f5c550 WD	338	*/
	339	#define CFG_PCI1_MEM_BASE 0x80000000
	340	#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
	341	#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
bf1dfffd MM	342	#define CFG_PCI1_IO_BASE 0x00000000
	343	#define CFG_PCI1_IO_PHYS 0xe2000000
	344	#define CFG_PCI1_IO_SIZE 0x100000 /* 1M */
03f5c550 WD	345
	346	#define CFG_PCI2_MEM_BASE 0xa0000000
	347	#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
	348	#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
bf1dfffd MM	349	#define CFG_PCI2_IO_BASE 0x00000000
	350	#define CFG_PCI2_IO_PHYS 0xe2100000
	351	#define CFG_PCI2_IO_SIZE 0x100000 /* 1M */
03f5c550	352
7f3f2bd2 RV	353	#ifdef CONFIG_LEGACY
	354	#define BRIDGE_ID 17
	355	#define VIA_ID 2
	356	#else
	357	#define BRIDGE_ID 28
	358	#define VIA_ID 4
	359	#endif
03f5c550 WD	360
	361	#if defined(CONFIG_PCI)
	362
bf1dfffd	363	#define CONFIG_MPC85XX_PCI2
03f5c550	364	#define CONFIG_NET_MULTI
53677ef1	365	#define CONFIG_PCI_PNP /* do pci plug-and-play */
03f5c550 WD	366
	367	#undef CONFIG_EEPRO100
	368	#undef CONFIG_TULIP
	369
03f5c550 WD	370	#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
	371	#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
	372
	373	#endif /* CONFIG_PCI */
	374
	375
	376	#if defined(CONFIG_TSEC_ENET)
	377
	378	#ifndef CONFIG_NET_MULTI
53677ef1	379	#define CONFIG_NET_MULTI 1
03f5c550 WD	380	#endif
	381
	382	#define CONFIG_MII 1 /* MII PHY management */
255a3577 KP	383	#define CONFIG_TSEC1 1
	384	#define CONFIG_TSEC1_NAME "TSEC0"
	385	#define CONFIG_TSEC2 1
	386	#define CONFIG_TSEC2_NAME "TSEC1"
03f5c550 WD	387	#define TSEC1_PHY_ADDR 0
03f5c550 WD	388	#define TSEC2_PHY_ADDR 1
03f5c550 WD	389	#define TSEC1_PHYIDX 0
03f5c550 WD	390	#define TSEC2_PHYIDX 0
3a79013e AF	391	#define TSEC1_FLAGS TSEC_GIGABIT
3a79013e AF	392	#define TSEC2_FLAGS TSEC_GIGABIT
d9b94f28 JL	393
	394	/* Options are: TSEC[0-1] */
	395	#define CONFIG_ETHPRIME "TSEC0"
03f5c550 WD	396
	397	#endif /* CONFIG_TSEC_ENET */
	398
03f5c550 WD	399	/*
	400	* Environment
	401	*/
	402	#define CFG_ENV_IS_IN_FLASH 1
	403	#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
	404	#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
	405	#define CFG_ENV_SIZE 0x2000
	406
	407	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	408	#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
	409
659e2f67 JL	410	/*
	411	* BOOTP options
	412	*/
	413	#define CONFIG_BOOTP_BOOTFILESIZE
	414	#define CONFIG_BOOTP_BOOTPATH
	415	#define CONFIG_BOOTP_GATEWAY
	416	#define CONFIG_BOOTP_HOSTNAME
	417
	418
2835e518 JL	419	/*
	420	* Command line configuration.
	421	*/
	422	#include <config_cmd_default.h>
	423
	424	#define CONFIG_CMD_PING
	425	#define CONFIG_CMD_I2C
	426	#define CONFIG_CMD_MII
82ac8c97	427	#define CONFIG_CMD_ELF
2835e518	428
03f5c550	429	#if defined(CONFIG_PCI)
2835e518	430	#define CONFIG_CMD_PCI
03f5c550	431	#endif
2835e518	432
03f5c550 WD	433
	434	#undef CONFIG_WATCHDOG /* watchdog disabled */
	435
	436	/*
	437	* Miscellaneous configurable options
	438	*/
	439	#define CFG_LONGHELP /* undef to save memory */
22abb2d2	440	#define CONFIG_CMDLINE_EDITING /* Command-line editing */
03f5c550 WD	441	#define CFG_LOAD_ADDR 0x2000000 /* default load address */
03f5c550 WD	442	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
2835e518	443	#if defined(CONFIG_CMD_KGDB)
03f5c550 WD	444	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	445	#else
	446	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	447	#endif
	448	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	449	#define CFG_MAXARGS 16 /* max number of command args */
	450	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	451	#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
	452
	453	/*
	454	* For booting Linux, the board info and command line data
	455	* have to be in the first 8 MB of memory, since this is
	456	* the maximum mapped by the Linux kernel during initialization.
	457	*/
53677ef1	458	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
03f5c550	459
03f5c550 WD	460	/*
	461	* Internal Definitions
	462	*
	463	* Boot Flags
	464	*/
	465	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	466	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	467
2835e518	468	#if defined(CONFIG_CMD_KGDB)
03f5c550 WD	469	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
	470	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
	471	#endif
	472
03f5c550 WD	473	/*
	474	* Environment Configuration
	475	*/
	476
	477	/* The mac addresses for all ethernet interface */
	478	#if defined(CONFIG_TSEC_ENET)
10327dc5	479	#define CONFIG_HAS_ETH0
03f5c550	480	#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
e2ffd59b	481	#define CONFIG_HAS_ETH1
03f5c550	482	#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
e2ffd59b	483	#define CONFIG_HAS_ETH2
03f5c550 WD	484	#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
	485	#endif
	486
	487	#define CONFIG_IPADDR 192.168.1.253
	488
	489	#define CONFIG_HOSTNAME unknown
	490	#define CONFIG_ROOTPATH /nfsroot
	491	#define CONFIG_BOOTFILE your.uImage
	492
	493	#define CONFIG_SERVERIP 192.168.1.1
	494	#define CONFIG_GATEWAYIP 192.168.1.1
	495	#define CONFIG_NETMASK 255.255.255.0
	496
	497	#define CONFIG_LOADADDR 200000 /default location for tftp and bootm/
	498
	499	#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
	500	#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
	501
	502	#define CONFIG_BAUDRATE 115200
	503
	504	#define CONFIG_EXTRA_ENV_SETTINGS \
	505	"netdev=eth0\0" \
	506	"consoledev=ttyS1\0" \
8272dc2f AF	507	"ramdiskaddr=600000\0" \
	508	"ramdiskfile=your.ramdisk.u-boot\0" \
	509	"fdtaddr=400000\0" \
	510	"fdtfile=your.fdt.dtb\0"
03f5c550 WD	511
	512	#define CONFIG_NFSBOOTCOMMAND \
	513	"setenv bootargs root=/dev/nfs rw " \
	514	"nfsroot=$serverip:$rootpath " \
	515	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
	516	"console=$consoledev,$baudrate $othbootargs;" \
	517	"tftp $loadaddr $bootfile;" \
8272dc2f AF	518	"tftp $fdtaddr $fdtfile;" \
8272dc2f AF	519	"bootm $loadaddr - $fdtaddr"
03f5c550 WD	520
	521	#define CONFIG_RAMBOOTCOMMAND \
	522	"setenv bootargs root=/dev/ram rw " \
	523	"console=$consoledev,$baudrate $othbootargs;" \
	524	"tftp $ramdiskaddr $ramdiskfile;" \
	525	"tftp $loadaddr $bootfile;" \
	526	"bootm $loadaddr $ramdiskaddr"
	527
	528	#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
	529
03f5c550	530	#endif /* __CONFIG_H */