[u-boot.git] / include / configs / csb272.h

/*
 * (C) Copyright 2004
 * Tolunay Orkun, Nextio Inc., [email protected]
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_405GP		1	/* This is a PPC405GP CPU	*/
#define CONFIG_4xx		1	/* ...member of PPC4xx family   */
#define CONFIG_CSB272		1	/* on a Cogent CSB272 board     */
#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f()    */
#define CONFIG_LAST_STAGE_INIT	1	/* Call last_stage_init()	*/
#define CONFIG_SYS_CLK_FREQ     33000000 /* external frequency to pll   */

/*
 * OS Bootstrap configuration
 *
 */

#if 0
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled */
#else
#define CONFIG_BOOTDELAY	3	/* autoboot after X seconds	*/
#endif

#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check keypress when bootdelay = 0 */

#if 1
#undef  CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
	"setenv bootargs console=ttyS0,38400 debug " \
	"root=/dev/ram rw ramdisk_size=4096 " \
	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
	"bootm fe000000 fe100000"
#endif

#if 0
#undef	CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
	"bootp; " \
	"setenv bootargs console=ttyS0,38400 debug " \
	"root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
	"bootm"
#endif

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_DNS2


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_BEDBUG
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_I2C
#define CONFIG_CMD_PCI
#define CONFIG_CMD_DATE
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP


/*
 * Serial download configuration
 *
 */
#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

/*
 * KGDB Configuration
 *
 */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
#endif

/*
 * Miscellaneous configurable options
 *
 */
#undef	CFG_HUSH_PARSER			/* use "hush" command parser */
#ifdef	CFG_HUSH_PARSER
#define	CFG_PROMPT_HUSH_PS2	"> "	/* hush shell secondary prompt */
#endif

#define CFG_LONGHELP			/* undef to save memory	*/
#define CFG_PROMPT		"=> "	/* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
#define	CFG_CBSIZE		1024	/* Console I/O Buffer Size */
#else
#define	CFG_CBSIZE		256	/* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS		16	/* max number of command args */
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */

#define CFG_MEMTEST_START	0x0400000 /* memtest works on */
#define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM */

#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
#define CFG_CLKS_IN_HZ		1	/* everything, incl board info, in Hz */
#define CFG_EXTBDINFO		1	/* To use extended board_info (bd_t) */
#define CFG_LOAD_ADDR		0x100000 /* default load address */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */

/*
 * watchdog configuration
 *
 */
#undef  CONFIG_WATCHDOG			/* watchdog disabled */

/*
 * UART configuration
 *
 */
#define CFG_EXT_SERIAL_CLOCK	3868400	/* use external serial clock */
#undef  CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59 */
#undef  CFG_BASE_BAUD
#define CONFIG_BAUDRATE		38400	/* Default baud rate */
#define CFG_BAUDRATE_TABLE      \
    { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400 }

/*
 * I2C configuration
 *
 */
#define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
#define CFG_I2C_SPEED		100000	/* I2C speed			*/
#define CFG_I2C_SLAVE		0x7F	/* I2C slave address		*/

/*
 * MII PHY configuration
 *
 */
#define CONFIG_MII		1	/* MII PHY management		*/
#define CONFIG_PHY_ADDR		0	/* PHY address			*/
#define CONFIG_PHY_CMD_DELAY	40	/* PHY COMMAND delay		*/
					/* 32usec min. for LXT971A	*/
#define CONFIG_PHY_RESET_DELAY	300	/* PHY RESET recovery delay	*/

/*
 * RTC configuration
 *
 * Note that DS1307 RTC is limited to 100Khz I2C bus.
 *
 */
#define CONFIG_RTC_DS1307		/* Use Dallas 1307 RTC		*/

/*
 * PCI stuff
 *
 */
#define CONFIG_PCI			/* include pci support	        */
#define PCI_HOST_ADAPTER	0	/* configure ar pci adapter     */
#define PCI_HOST_FORCE		1	/* configure as pci host        */
#define PCI_HOST_AUTO		2	/* detected via arbiter enable  */

#define CONFIG_PCI_HOST	PCI_HOST_FORCE  /* select pci host function     */
#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
					/* resource configuration       */
#undef  CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/

#define CFG_PCI_SUBSYS_VENDORID 0x0000  /* PCI Vendor ID: to-do!!!      */
#define CFG_PCI_SUBSYS_DEVICEID 0x0000  /* PCI Device ID: to-do!!!      */
#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
#define CFG_PCI_PTM1MS  0x80000001      /* 2GB, enable hard-wired to 1  */
#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
#define CFG_PCI_PTM2LA  0x00000000      /* disabled                     */
#define CFG_PCI_PTM2MS  0x00000000      /* disabled                     */
#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */

/*
 * IDE stuff
 *
 */
#undef  CONFIG_IDE_PCMCIA               /* no pcmcia interface required */
#undef  CONFIG_IDE_LED                  /* no led for ide supported     */
#undef  CONFIG_IDE_RESET                /* no reset for ide supported   */

/*
 * Environment configuration
 *
 */
#define CFG_ENV_IS_IN_FLASH	1	/* environment is in FLASH	*/
#undef CFG_ENV_IS_IN_NVRAM
#undef CFG_ENV_IS_IN_EEPROM

/*
 * General Memory organization
 *
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define CFG_SDRAM_BASE		0x00000000
#define CFG_FLASH_BASE		0xFE000000
#define CFG_FLASH_SIZE		0x02000000
#define CFG_MONITOR_BASE	TEXT_BASE
#define CFG_MONITOR_LEN		(256 * 1024) /* Reserve 256 KB for Monitor */
#define CFG_MALLOC_LEN		(128 * 1024) /* Reserve 128 KB for malloc() */

#if CFG_MONITOR_BASE < CFG_FLASH_BASE
#define CFG_RAMSTART
#endif

#if defined(CFG_ENV_IS_IN_FLASH)
#define CFG_ENV_IN_OWN_SECTOR	1	   /* Give Environment own sector */
#define CFG_ENV_ADDR		0xFFF00000 /* Address of Environment Sector */
#define	CFG_ENV_SIZE		0x00001000 /* Size of Environment */
#define CFG_ENV_SECT_SIZE	0x00040000 /* Size of Environment Sector */
#endif

/*
 * FLASH Device configuration
 *
 */
#define CFG_FLASH_CFI		1	/* flash is CFI conformant	*/
#define CFG_FLASH_CFI_DRIVER	1	/* use common cfi driver	*/
#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster) */
#define CFG_MAX_FLASH_BANKS	1	/* max # of memory banks	*/
#define CFG_FLASH_INCREMENT	0	/* there is only one bank	*/
#define CFG_MAX_FLASH_SECT	128	/* max # of sectors on one chip	*/
#define CFG_FLASH_PROTECTION	1	/* hardware flash protection	*/
#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }

/*
 * On Chip Memory location/size
 *
 */
#define CFG_OCM_DATA_ADDR	0xF8000000
#define CFG_OCM_DATA_SIZE	0x1000

/*
 * Global info and initial stack
 *
 */
#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of on-chip SRAM */
#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM */
#define CFG_GBL_DATA_SIZE	128 /* byte size reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

/*
 * Miscellaneous board specific definitions
 *
 */
#define CFG_I2C_PLL_ADDR	0x58	/* I2C address of AMIS FS6377-01 PLL */
#define CONFIG_I2CFAST		1	/* enable "i2cfast" env. setting     */

/*
 * Internal Definitions
 *
 * Boot Flags
 *
 */
#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM		0x02	/* Software reboot */

#endif	/* __CONFIG_H */
Commit	Line	Data
cd0a9de6 WD	1	/*
	2	* (C) Copyright 2004
	3	* Tolunay Orkun, Nextio Inc., [email protected]
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* board/config.h - configuration options, board specific
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/*
	32	* High Level Configuration Options
	33	* (easy to change)
	34	*/
	35
53677ef1	36	#define CONFIG_405GP 1 /* This is a PPC405GP CPU */
cd0a9de6 WD	37	#define CONFIG_4xx 1 /* ...member of PPC4xx family */
cd0a9de6 WD	38	#define CONFIG_CSB272 1 /* on a Cogent CSB272 board */
4d13cbad	39	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f() */
cd0a9de6 WD	40	#define CONFIG_LAST_STAGE_INIT 1 /* Call last_stage_init() */
	41	#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
	42
	43	/*
	44	* OS Bootstrap configuration
	45	*
	46	*/
	47
	48	#if 0
	49	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
	50	#else
	51	#define CONFIG_BOOTDELAY 3 /* autoboot after X seconds */
	52	#endif
	53
	54	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check keypress when bootdelay = 0 */
	55
	56	#if 1
	57	#undef CONFIG_BOOTARGS
	58	#define CONFIG_BOOTCOMMAND \
	59	"setenv bootargs console=ttyS0,38400 debug " \
	60	"root=/dev/ram rw ramdisk_size=4096 " \
fe126d8b	61	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
cd0a9de6 WD	62	"bootm fe000000 fe100000"
	63	#endif
	64
	65	#if 0
	66	#undef CONFIG_BOOTARGS
	67	#define CONFIG_BOOTCOMMAND \
	68	"bootp; " \
	69	"setenv bootargs console=ttyS0,38400 debug " \
fe126d8b WD	70	"root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
fe126d8b WD	71	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
cd0a9de6 WD	72	"bootm"
	73	#endif
	74
	75	/*
2fd90ce5	76	* BOOTP options
cd0a9de6	77	*/
2fd90ce5 JL	78	#define CONFIG_BOOTP_SUBNETMASK
	79	#define CONFIG_BOOTP_GATEWAY
	80	#define CONFIG_BOOTP_HOSTNAME
	81	#define CONFIG_BOOTP_BOOTPATH
	82	#define CONFIG_BOOTP_BOOTFILESIZE
	83	#define CONFIG_BOOTP_DNS2
37e4f24b JL	84
37e4f24b JL	85
cd0a9de6	86	/*
37e4f24b	87	* Command line configuration.
cd0a9de6	88	*/
37e4f24b JL	89	#include <config_cmd_default.h>
	90
	91	#define CONFIG_CMD_ASKENV
	92	#define CONFIG_CMD_BEDBUG
	93	#define CONFIG_CMD_ELF
	94	#define CONFIG_CMD_IRQ
	95	#define CONFIG_CMD_I2C
	96	#define CONFIG_CMD_PCI
	97	#define CONFIG_CMD_DATE
	98	#define CONFIG_CMD_MII
	99	#define CONFIG_CMD_PING
	100	#define CONFIG_CMD_DHCP
	101
cd0a9de6 WD	102
	103	/*
	104	* Serial download configuration
	105	*
	106	*/
	107	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	108	#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
	109
	110	/*
	111	* KGDB Configuration
	112	*
	113	*/
37e4f24b	114	#if defined(CONFIG_CMD_KGDB)
cd0a9de6 WD	115	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
	116	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
	117	#endif
	118
	119	/*
	120	* Miscellaneous configurable options
	121	*
	122	*/
	123	#undef CFG_HUSH_PARSER /* use "hush" command parser */
	124	#ifdef CFG_HUSH_PARSER
	125	#define CFG_PROMPT_HUSH_PS2 "> " /* hush shell secondary prompt */
	126	#endif
	127
	128	#define CFG_LONGHELP /* undef to save memory */
	129	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
37e4f24b	130	#if defined(CONFIG_CMD_KGDB)
cd0a9de6 WD	131	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	132	#else
	133	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	134	#endif
	135	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	136	#define CFG_MAXARGS 16 /* max number of command args */
	137	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	138
	139	#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
	140	#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
	141
	142	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	143	#define CFG_CLKS_IN_HZ 1 /* everything, incl board info, in Hz */
	144	#define CFG_EXTBDINFO 1 /* To use extended board_info (bd_t) */
	145	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	146
	147	/*
	148	* For booting Linux, the board info and command line data
	149	* have to be in the first 8 MB of memory, since this is
	150	* the maximum mapped by the Linux kernel during initialization.
	151	*/
	152	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	153
	154	/*
	155	* watchdog configuration
	156	*
	157	*/
	158	#undef CONFIG_WATCHDOG /* watchdog disabled */
	159
	160	/*
	161	* UART configuration
	162	*
	163	*/
	164	#define CFG_EXT_SERIAL_CLOCK 3868400 /* use external serial clock */
	165	#undef CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
	166	#undef CFG_BASE_BAUD
	167	#define CONFIG_BAUDRATE 38400 /* Default baud rate */
	168	#define CFG_BAUDRATE_TABLE \
	169	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400 }
	170
	171	/*
	172	* I2C configuration
	173	*
	174	*/
	175	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
	176	#define CFG_I2C_SPEED 100000 /* I2C speed */
	177	#define CFG_I2C_SLAVE 0x7F /* I2C slave address */
	178
	179	/*
	180	* MII PHY configuration
	181	*
	182	*/
	183	#define CONFIG_MII 1 /* MII PHY management */
	184	#define CONFIG_PHY_ADDR 0 /* PHY address */
53677ef1	185	#define CONFIG_PHY_CMD_DELAY 40 /* PHY COMMAND delay */
cd0a9de6 WD	186	/* 32usec min. for LXT971A */
	187	#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */
	188
	189	/*
	190	* RTC configuration
	191	*
	192	* Note that DS1307 RTC is limited to 100Khz I2C bus.
	193	*
	194	*/
	195	#define CONFIG_RTC_DS1307 /* Use Dallas 1307 RTC */
	196
	197	/*
	198	* PCI stuff
	199	*
	200	*/
	201	#define CONFIG_PCI /* include pci support */
	202	#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
	203	#define PCI_HOST_FORCE 1 /* configure as pci host */
	204	#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
	205
	206	#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
	207	#define CONFIG_PCI_PNP /* do pci plug-and-play */
	208	/* resource configuration */
	209	#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
	210	#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
	211
	212	#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
	213	#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
	214	#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
	215	#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
	216	#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
	217	#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
	218	#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
	219	#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
	220
	221	/*
	222	* IDE stuff
	223	*
	224	*/
	225	#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */
	226	#undef CONFIG_IDE_LED /* no led for ide supported */
	227	#undef CONFIG_IDE_RESET /* no reset for ide supported */
	228
	229	/*
	230	* Environment configuration
	231	*
	232	*/
	233	#define CFG_ENV_IS_IN_FLASH 1 /* environment is in FLASH */
	234	#undef CFG_ENV_IS_IN_NVRAM
	235	#undef CFG_ENV_IS_IN_EEPROM
	236
	237	/*
	238	* General Memory organization
	239	*
	240	* Start addresses for the final memory configuration
	241	* (Set up by the startup code)
	242	* Please note that CFG_SDRAM_BASE _must_ start at 0
	243	*/
	244	#define CFG_SDRAM_BASE 0x00000000
	245	#define CFG_FLASH_BASE 0xFE000000
	246	#define CFG_FLASH_SIZE 0x02000000
	247	#define CFG_MONITOR_BASE TEXT_BASE
	248	#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 KB for Monitor */
	249	#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 KB for malloc() */
250
251	#if CFG_MONITOR_BASE < CFG_FLASH_BASE
252	#define CFG_RAMSTART
253	#endif
254
255	#if defined(CFG_ENV_IS_IN_FLASH)
256	#define CFG_ENV_IN_OWN_SECTOR 1 /* Give Environment own sector */
257	#define CFG_ENV_ADDR 0xFFF00000 /* Address of Environment Sector */
258	#define CFG_ENV_SIZE 0x00001000 /* Size of Environment */
259	#define CFG_ENV_SECT_SIZE 0x00040000 /* Size of Environment Sector */
260	#endif
261
262	/*
263	* FLASH Device configuration
264	*
265	*/
266	#define CFG_FLASH_CFI 1 /* flash is CFI conformant */
267	#define CFG_FLASH_CFI_DRIVER 1 /* use common cfi driver */
268	#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
269	#define CFG_MAX_FLASH_BANKS 1 /* max # of memory banks */
270	#define CFG_FLASH_INCREMENT 0 /* there is only one bank */
271	#define CFG_MAX_FLASH_SECT 128 /* max # of sectors on one chip */
272	#define CFG_FLASH_PROTECTION 1 /* hardware flash protection */
273	#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
274
275	/*
276	* On Chip Memory location/size
277	*
278	*/
279	#define CFG_OCM_DATA_ADDR 0xF8000000
280	#define CFG_OCM_DATA_SIZE 0x1000
281
282	/*
283	* Global info and initial stack
284	*
285	*/
286	#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of on-chip SRAM */
287	#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
288	#define CFG_GBL_DATA_SIZE 128 /* byte size reserved for initial data */
289	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
290	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
291
cd0a9de6 WD	292	/*
	293	* Miscellaneous board specific definitions
	294	*
	295	*/
	296	#define CFG_I2C_PLL_ADDR 0x58 /* I2C address of AMIS FS6377-01 PLL */
eeb1b77b	297	#define CONFIG_I2CFAST 1 /* enable "i2cfast" env. setting */
cd0a9de6 WD	298
	299	/*
	300	* Internal Definitions
	301	*
	302	* Boot Flags
	303	*
	304	*/
	305	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	306	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	307
	308	#endif /* __CONFIG_H */