[u-boot.git] / board / uc100 / uc100.c

/*
 * (C) Copyright 2000-2004
 * Wolfgang Denk, DENX Software Engineering, [email protected].
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#if 0
#define DEBUG
#endif

#include <common.h>
#include <mpc8xx.h>
#include <i2c.h>
#include <miiphy.h>

int fec8xx_miiphy_write(char *devname, unsigned char  addr,
		unsigned char  reg, unsigned short value);

/*********************************************************************/
/* UPMA Pre Initilization Table by WV (Miron MT48LC16M16A2-7E B)     */
/*********************************************************************/
const uint sdram_init_upm_table[] = {
	/* SDRAM Initialisation Sequence (offset 0 in UPMA RAM) WV */
	/* NOP    - Precharge - AutoRefr  - NOP       - NOP        */
	/* NOP    - AutoRefr  - NOP                                */
	/* NOP    - NOP       - LoadModeR - NOP       - Active     */
	/* Position of Single Read                                 */
	0x0ffffc04, 0x0ff77c04, 0x0ff5fc04, 0x0ffffc04, 0x0ffffc04,
	0x0ffffc04, 0x0ff5fc04, 0x0ffffc04,

	/* Burst Read. (offset 8 in UPMA RAM)     */
	/* Cycle lent for Initialisation WV */
	0x0ffffc04, 0x0ffffc34, 0x0f057c34, 0x0ffffc30, 0x1ff7fc05,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,

	/* Single Write. (offset 18 in UPMA RAM) */
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,

	/* Burst Write. (offset 20 in UPMA RAM) */
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,

	/* Refresh  (offset 30 in UPMA RAM) */
	0x0FF77C04, 0x0FFFFC04, 0x0FF5FC84, 0x0FFFFC04, 0x0FFFFC04,
	0x0FFFFC84, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF,

	/* Exception. (offset 3c in UPMA RAM) */
	0x7FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
};

/*********************************************************************/
/* UPMA initilization table.                                         */
/*********************************************************************/
const uint sdram_upm_table[] = {
	/* single read. (offset 0 in UPMA RAM) */
	0x0F07FC04, 0x0FFFFC04, 0x00BDFC04, 0x0FF77C00, 0x1FFFFC05,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,     /* 0x05-0x07 new WV */

	/* Burst Read. (offset 8 in UPMA RAM) */
	0x0F07FC04, 0x0FFFFC04, 0x00BDFC04, 0x00FFFC00, 0x00FFFC00,
	0x00FFFC00, 0x0FF77C00, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,

	/* Single Write. (offset 18 in UPMA RAM) */
	0x0F07FC04, 0x0FFFFC00, 0x00BD7C04, 0x0FFFFC04, 0x0FF77C04,
	0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF,

	/* Burst Write. (offset 20 in UPMA RAM) */
	0x0F07FC04, 0x0FFFFC00, 0x00BD7C00, 0x00FFFC00, 0x00FFFC00,
	0x00FFFC04, 0x0FFFFC04, 0x0FF77C04, 0x1FFFFC05, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,

	/* Refresh  (offset 30 in UPMA RAM) */
	0x0FF77C04, 0x0FFFFC04, 0x0FF5FC84, 0x0FFFFC04, 0x0FFFFC04,
	0x0FFFFC84, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF,

	/* Exception. (offset 3c in UPMA RAM) */
	0x7FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, /* 0x3C new WV */
};

/*********************************************************************/
/* UPMB initilization table.                                         */
/*********************************************************************/
const uint mpm_upm_table[] = {
	/*  single read. (offset 0 in upm RAM) */
	0x8FF00004, 0x0FF00004, 0x0FF81004, 0x1FF00001,
	0x1FF00001, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,

	/* burst read. (Offset 8 in upm RAM)   */
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,

	/* single write. (Offset 0x18 in upm RAM) */
	0x8FF00004, 0x0FF00004, 0x0FF81004, 0x0FF00004,
	0x0FF00004, 0x1FF00001, 0xFFFFFFFF, 0xFFFFFFFF,

	/*  burst write. (Offset 0x20 in upm RAM) */
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,

	/* Refresh cycle, offset 0x30 */
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,

	/* Exception, 0ffset 0x3C */
	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
};


int board_switch(void)
{
	volatile pcmconf8xx_t	*pcmp;

	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));

	return ((pcmp->pcmc_pipr >> 24) & 0xf);
}


/*
 * Check Board Identity:
 */
int checkboard (void)
{
	char str[64];
	int i = getenv_r ("serial#", str, sizeof(str));

	puts ("Board: ");

	if (i == -1) {
		puts ("### No HW ID - assuming UC100");
	} else {
		puts(str);
	}

	printf (" (SWITCH=%1X)\n", board_switch());

	return 0;
}


/*
 * Initialize SDRAM
 */
long int initdram (int board_type)
{
	volatile immap_t *immap = (immap_t *) CFG_IMMR;
	volatile memctl8xx_t *memctl = &immap->im_memctl;

	/*---------------------------------------------------------------------*/
	/* Initialize the UPMA/UPMB registers with the appropriate table.      */
	/*---------------------------------------------------------------------*/
	upmconfig (UPMA, (uint *) sdram_init_upm_table,
		   sizeof (sdram_init_upm_table) / sizeof (uint));
	upmconfig (UPMB, (uint *) mpm_upm_table,
		   sizeof (mpm_upm_table) / sizeof (uint));

	/*---------------------------------------------------------------------*/
	/* Memory Periodic Timer Prescaler: divide by 16                       */
	/*---------------------------------------------------------------------*/
	memctl->memc_mptpr = 0x0200; /* Divide by 32 WV */

	memctl->memc_mamr = CFG_MAMR_VAL & 0xFF7FFFFF; /* Bit 8 := "0" Kein Refresh WV */
	memctl->memc_mbmr = CFG_MBMR_VAL;

	/*---------------------------------------------------------------------*/
	/* Initialize the Memory Controller registers, MPTPR, Chip Select 1    */
	/* for SDRAM                                                           */
	/*                                                                     */
	/* NOTE: The refresh rate in MAMR reg is set according to the lowest   */
	/*       clock rate (16.67MHz) to allow proper operation for all ADS   */
	/*       clock frequencies.                                            */
	/*---------------------------------------------------------------------*/
	memctl->memc_or1 = CFG_OR1_PRELIM;
	memctl->memc_br1 = CFG_BR1_PRELIM;

	/*-------------------------------------------------------------------*/
	/* Wait at least 200 usec for DRAM to stabilize, this magic number   */
	/* obtained from the init code.                                      */
	/*-------------------------------------------------------------------*/
	udelay(200);

	memctl->memc_mamr = (memctl->memc_mamr | 0x04) & ~0x08;

	memctl->memc_br1 = CFG_BR1_PRELIM;
	memctl->memc_or1 = CFG_OR1_PRELIM;

	/*---------------------------------------------------------------------*/
	/* run MRS command in location 5-8 of UPMB.                            */
	/*---------------------------------------------------------------------*/
	memctl->memc_mar = 0x88;
	/* RUN UPMA on CS1 1-time from UPMA addr 0x05 */

	memctl->memc_mcr = 0x80002100;
	/* RUN UPMA on CS1 1-time from UPMA addr 0x00 WV */

	udelay(200);

	/*---------------------------------------------------------------------*/
	/* Initialisation for normal access WV                                 */
	/*---------------------------------------------------------------------*/

	/*---------------------------------------------------------------------*/
	/* Initialize the UPMA register with the appropriate table.            */
	/*---------------------------------------------------------------------*/
	upmconfig (UPMA, (uint *) sdram_upm_table,
		   sizeof (sdram_upm_table) / sizeof (uint));

	/*---------------------------------------------------------------------*/
	/* rerstore MBMR value (4-beat refresh burst.)                         */
	/*---------------------------------------------------------------------*/
	memctl->memc_mamr = CFG_MAMR_VAL | 0x00800000; /* Bit 8 := "1" Refresh Enable WV */

	udelay(200);

	return (64 * 1024 * 1024); /* fixed setup for 64MBytes! */
}


int misc_init_r (void)
{
	uchar val;

	/*
	 * Make sure that RTC has clock output enabled (triggers watchdog!)
	 */
	val = i2c_reg_read (CFG_I2C_RTC_ADDR, 0x0D);
	val |= 0x80;
	i2c_reg_write (CFG_I2C_RTC_ADDR, 0x0D, val);

	/*
	 * Configure PHY to setup LED's correctly and use 100MBit, FD
	 */
	mii_init();

	/* disable auto-negotiation, 100mbit, full-duplex */
	fec8xx_miiphy_write(NULL, 0, PHY_BMCR, 0x2100);

	/* set LED's to Link, Transmit, Receive           */
	fec8xx_miiphy_write(NULL,  0, PHY_FCSCR, 0x4122);

	return 0;
}


#ifdef CONFIG_POST
/*
 * Returns 1 if keys pressed to start the power-on long-running tests
 * Called from board_init_f().
 */
int post_hotkeys_pressed (void)
{
	return 0;		/* No hotkeys supported */
}
#endif
Commit	Line	Data
f7d1572b WD	1	/*
	2	* (C) Copyright 2000-2004
	3	* Wolfgang Denk, DENX Software Engineering, [email protected].
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#if 0
	25	#define DEBUG
	26	#endif
	27
	28	#include <common.h>
	29	#include <mpc8xx.h>
	30	#include <i2c.h>
cd5b2b99	31	#include <miiphy.h>
f7d1572b	32
63ff004c MB	33	int fec8xx_miiphy_write(char *devname, unsigned char addr,
63ff004c MB	34	unsigned char reg, unsigned short value);
f7d1572b WD	35
	36	/*********************************************************************/
	37	/* UPMA Pre Initilization Table by WV (Miron MT48LC16M16A2-7E B) */
	38	/*********************************************************************/
	39	const uint sdram_init_upm_table[] = {
	40	/* SDRAM Initialisation Sequence (offset 0 in UPMA RAM) WV */
	41	/* NOP - Precharge - AutoRefr - NOP - NOP */
	42	/* NOP - AutoRefr - NOP */
	43	/* NOP - NOP - LoadModeR - NOP - Active */
	44	/* Position of Single Read */
	45	0x0ffffc04, 0x0ff77c04, 0x0ff5fc04, 0x0ffffc04, 0x0ffffc04,
	46	0x0ffffc04, 0x0ff5fc04, 0x0ffffc04,
	47
	48	/* Burst Read. (offset 8 in UPMA RAM) */
	49	/* Cycle lent for Initialisation WV */
	50	0x0ffffc04, 0x0ffffc34, 0x0f057c34, 0x0ffffc30, 0x1ff7fc05,
	51	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	52	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	53
	54	/* Single Write. (offset 18 in UPMA RAM) */
	55	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	56	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	57
	58	/* Burst Write. (offset 20 in UPMA RAM) */
	59	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	60	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	61	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	62
	63	/* Refresh (offset 30 in UPMA RAM) */
	64	0x0FF77C04, 0x0FFFFC04, 0x0FF5FC84, 0x0FFFFC04, 0x0FFFFC04,
	65	0x0FFFFC84, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	66	0xFFFFFFFF, 0xFFFFFFFF,
	67
	68	/* Exception. (offset 3c in UPMA RAM) */
	69	0x7FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	70	};
	71
	72	/*********************************************************************/
	73	/* UPMA initilization table. */
	74	/*********************************************************************/
	75	const uint sdram_upm_table[] = {
	76	/* single read. (offset 0 in UPMA RAM) */
	77	0x0F07FC04, 0x0FFFFC04, 0x00BDFC04, 0x0FF77C00, 0x1FFFFC05,
	78	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, /* 0x05-0x07 new WV */
	79
	80	/* Burst Read. (offset 8 in UPMA RAM) */
	81	0x0F07FC04, 0x0FFFFC04, 0x00BDFC04, 0x00FFFC00, 0x00FFFC00,
	82	0x00FFFC00, 0x0FF77C00, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF,
	83	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	84
	85	/* Single Write. (offset 18 in UPMA RAM) */
	86	0x0F07FC04, 0x0FFFFC00, 0x00BD7C04, 0x0FFFFC04, 0x0FF77C04,
	87	0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF,
	88
	89	/* Burst Write. (offset 20 in UPMA RAM) */
	90	0x0F07FC04, 0x0FFFFC00, 0x00BD7C00, 0x00FFFC00, 0x00FFFC00,
	91	0x00FFFC04, 0x0FFFFC04, 0x0FF77C04, 0x1FFFFC05, 0xFFFFFFFF,
	92	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	93
	94	/* Refresh (offset 30 in UPMA RAM) */
	95	0x0FF77C04, 0x0FFFFC04, 0x0FF5FC84, 0x0FFFFC04, 0x0FFFFC04,
	96	0x0FFFFC84, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
	97	0xFFFFFFFF, 0xFFFFFFFF,
	98
99	/* Exception. (offset 3c in UPMA RAM) */
100	0x7FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, /* 0x3C new WV */
101	};
102
103	/*********************************************************************/
104	/* UPMB initilization table. */
105	/*********************************************************************/
106	const uint mpm_upm_table[] = {
107	/* single read. (offset 0 in upm RAM) */
108	0x8FF00004, 0x0FF00004, 0x0FF81004, 0x1FF00001,
109	0x1FF00001, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
110
111	/* burst read. (Offset 8 in upm RAM) */
112	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
113	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
114	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
115	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
116
117	/* single write. (Offset 0x18 in upm RAM) */
118	0x8FF00004, 0x0FF00004, 0x0FF81004, 0x0FF00004,
119	0x0FF00004, 0x1FF00001, 0xFFFFFFFF, 0xFFFFFFFF,
120
121	/* burst write. (Offset 0x20 in upm RAM) */
122	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
123	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
124	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
125	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
126
127	/* Refresh cycle, offset 0x30 */
128	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
129	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
130	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
131
132	/* Exception, 0ffset 0x3C */
133	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
134	};
135
136
137	int board_switch(void)
138	{
139	volatile pcmconf8xx_t *pcmp;
140
141	pcmp = (pcmconf8xx_t )(&(((immap_t )CFG_IMMR)->im_pcmcia));
142
143	return ((pcmp->pcmc_pipr >> 24) & 0xf);
144	}
145
146
147	/*
148	* Check Board Identity:
149	*/
150	int checkboard (void)
151	{
77ddac94	152	char str[64];
f7d1572b WD	153	int i = getenv_r ("serial#", str, sizeof(str));
	154
	155	puts ("Board: ");
	156
	157	if (i == -1) {
	158	puts ("### No HW ID - assuming UC100");
	159	} else {
	160	puts(str);
	161	}
	162
	163	printf (" (SWITCH=%1X)\n", board_switch());
	164
	165	return 0;
	166	}
	167
	168
	169	/*
	170	* Initialize SDRAM
	171	*/
	172	long int initdram (int board_type)
	173	{
	174	volatile immap_t immap = (immap_t ) CFG_IMMR;
	175	volatile memctl8xx_t *memctl = &immap->im_memctl;
	176
	177	/---------------------------------------------------------------------/
	178	/* Initialize the UPMA/UPMB registers with the appropriate table. */
	179	/---------------------------------------------------------------------/
	180	upmconfig (UPMA, (uint *) sdram_init_upm_table,
	181	sizeof (sdram_init_upm_table) / sizeof (uint));
	182	upmconfig (UPMB, (uint *) mpm_upm_table,
	183	sizeof (mpm_upm_table) / sizeof (uint));
	184
	185	/---------------------------------------------------------------------/
	186	/* Memory Periodic Timer Prescaler: divide by 16 */
	187	/---------------------------------------------------------------------/
	188	memctl->memc_mptpr = 0x0200; /* Divide by 32 WV */
	189
	190	memctl->memc_mamr = CFG_MAMR_VAL & 0xFF7FFFFF; /* Bit 8 := "0" Kein Refresh WV */
53677ef1	191	memctl->memc_mbmr = CFG_MBMR_VAL;
f7d1572b WD	192
	193	/---------------------------------------------------------------------/
	194	/* Initialize the Memory Controller registers, MPTPR, Chip Select 1 */
	195	/* for SDRAM */
	196	/* */
	197	/* NOTE: The refresh rate in MAMR reg is set according to the lowest */
	198	/* clock rate (16.67MHz) to allow proper operation for all ADS */
	199	/* clock frequencies. */
	200	/---------------------------------------------------------------------/
	201	memctl->memc_or1 = CFG_OR1_PRELIM;
	202	memctl->memc_br1 = CFG_BR1_PRELIM;
	203
	204	/-------------------------------------------------------------------/
	205	/* Wait at least 200 usec for DRAM to stabilize, this magic number */
	206	/* obtained from the init code. */
	207	/-------------------------------------------------------------------/
	208	udelay(200);
	209
	210	memctl->memc_mamr = (memctl->memc_mamr \| 0x04) & ~0x08;
	211
	212	memctl->memc_br1 = CFG_BR1_PRELIM;
	213	memctl->memc_or1 = CFG_OR1_PRELIM;
	214
	215	/---------------------------------------------------------------------/
	216	/* run MRS command in location 5-8 of UPMB. */
	217	/---------------------------------------------------------------------/
	218	memctl->memc_mar = 0x88;
	219	/* RUN UPMA on CS1 1-time from UPMA addr 0x05 */
	220
	221	memctl->memc_mcr = 0x80002100;
	222	/* RUN UPMA on CS1 1-time from UPMA addr 0x00 WV */
	223
	224	udelay(200);
	225
	226	/---------------------------------------------------------------------/
	227	/* Initialisation for normal access WV */
	228	/---------------------------------------------------------------------/
	229
	230	/---------------------------------------------------------------------/
	231	/* Initialize the UPMA register with the appropriate table. */
	232	/---------------------------------------------------------------------/
	233	upmconfig (UPMA, (uint *) sdram_upm_table,
	234	sizeof (sdram_upm_table) / sizeof (uint));
	235
	236	/---------------------------------------------------------------------/
	237	/* rerstore MBMR value (4-beat refresh burst.) */
	238	/---------------------------------------------------------------------/
	239	memctl->memc_mamr = CFG_MAMR_VAL \| 0x00800000; /* Bit 8 := "1" Refresh Enable WV */
	240
	241	udelay(200);
	242
	243	return (64 * 1024 * 1024); /* fixed setup for 64MBytes! */
	244	}
	245
	246
	247	int misc_init_r (void)
	248	{
	249	uchar val;
	250
	251	/*
	252	* Make sure that RTC has clock output enabled (triggers watchdog!)
	253	*/
	254	val = i2c_reg_read (CFG_I2C_RTC_ADDR, 0x0D);
	255	val \|= 0x80;
256	i2c_reg_write (CFG_I2C_RTC_ADDR, 0x0D, val);
257
cd5b2b99 SR	258	/*
	259	* Configure PHY to setup LED's correctly and use 100MBit, FD
	260	*/
	261	mii_init();
	262
63ff004c MB	263	/* disable auto-negotiation, 100mbit, full-duplex */
	264	fec8xx_miiphy_write(NULL, 0, PHY_BMCR, 0x2100);
	265
	266	/* set LED's to Link, Transmit, Receive */
	267	fec8xx_miiphy_write(NULL, 0, PHY_FCSCR, 0x4122);
cd5b2b99	268
f7d1572b WD	269	return 0;
	270	}
	271
	272
	273	#ifdef CONFIG_POST
	274	/*
	275	* Returns 1 if keys pressed to start the power-on long-running tests
	276	* Called from board_init_f().
	277	*/
	278	int post_hotkeys_pressed (void)
	279	{
	280	return 0; /* No hotkeys supported */
	281	}
	282	#endif