[u-boot.git] / board / netstar / setup.S

/*
 * Board specific setup info
 *
 * (C) Copyright 2004 Ales Jindra <[email protected]>
 * (C) Copyright 2005 Ladislav Michl <[email protected]>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <config.h>
#include <version.h>

_TEXT_BASE:
	.word	TEXT_BASE	/* SDRAM load addr from config.mk */

OMAP5910_LPG1_BASE:		.word 0xfffbd000
OMAP5910_TIPB_SWITCHES_BASE:	.word 0xfffbc800
OMAP5910_MPU_TC_BASE:		.word 0xfffecc00
OMAP5910_MPU_CLKM_BASE:		.word 0xfffece00
OMAP5910_ULPD_PWR_MNG_BASE:	.word 0xfffe0800
OMAP5910_DPLL1_BASE:		.word 0xfffecf00
OMAP5910_GPIO_BASE:		.word 0xfffce000
OMAP5910_MPU_WD_TIMER_BASE:	.word 0xfffec800
OMAP5910_MPUI_BASE:		.word 0xfffec900

_OMAP5910_ARM_CKCTL:		.word OMAP5910_ARM_CKCTL
_OMAP5910_ARM_EN_CLK:		.word OMAP5910_ARM_EN_CLK

OMAP5910_MPUI_CTRL:		.word 0x0000ff1b

VAL_EMIFS_CS0_CONFIG:		.word 0x00009090
VAL_EMIFS_CS1_CONFIG:		.word 0x00003031
VAL_EMIFS_CS2_CONFIG:		.word 0x0000a0a1
VAL_EMIFS_CS3_CONFIG:		.word 0x0000c0c0
VAL_EMIFS_DYN_WAIT:		.word 0x00000000
/* autorefresh counter 0x246 ((64000000/13.4)-400)/8192) */
				/*     SLRF       SD_RET     ARE        SDRAM_TYPE   ARCV           SDRAM_FREQUENCY PWD     CLK */

#if (PHYS_SDRAM_1_SIZE == SZ_32M)
VAL_EMIFF_SDRAM_CONFIG:		.word ((0 << 0) | (0 << 1) | (3 << 2) | (0xf << 4) | (0x246 << 8) | (0 << 24) | (0 << 26) | (0 << 27))
#else
VAL_EMIFF_SDRAM_CONFIG:		.word ((0 << 0) | (0 << 1) | (3 << 2) | (0xd << 4) | (0x246 << 8) | (0 << 24) | (0 << 26) | (0 << 27))
#endif

VAL_EMIFF_SDRAM_CONFIG2:	.word 0x00000003
VAL_EMIFF_MRS:			.word 0x00000037

/*
 * GPIO04 - Green LED (Red LED is connected to LED Pulse Generator)
 * GPIO07 - LAN91C111 reset
 */
GPIO_DIRECTION:
	.word 0x0000ff6f
/*
 * Disable everything (green LED is connected via invertor)
 */
GPIO_OUTPUT:
	.word 0x00000010

MUX_CONFIG_BASE:
	.word 0xfffe1000

MUX_CONFIG_VALUES:
	.align 4
	.word 0x00000000	@ FUNC_MUX_CTRL_0
	.word 0x00000000	@ FUNC_MUX_CTRL_1
	.word 0x00000000	@ FUNC_MUX_CTRL_2
	.word 0x00000000	@ FUNC_MUX_CTRL_3
	.word 0x00000000	@ FUNC_MUX_CTRL_4
	.word 0x02080480	@ FUNC_MUX_CTRL_5
	.word 0x0100001c	@ FUNC_MUX_CTRL_6
	.word 0x0004800b	@ FUNC_MUX_CTRL_7
	.word 0x10001200	@ FUNC_MUX_CTRL_8
	.word 0x01201012	@ FUNC_MUX_CTRL_9
	.word 0x02082248	@ FUNC_MUX_CTRL_A
	.word 0x00000248	@ FUNC_MUX_CTRL_B
	.word 0x12240000	@ FUNC_MUX_CTRL_C
	.word 0x00002000	@ FUNC_MUX_CTRL_D
	.word 0x00000000	@ PULL_DWN_CTRL_0
	.word 0x00000800	@ PULL_DWN_CTRL_1
	.word 0x01801000	@ PULL_DWN_CTRL_2
	.word 0x00000000	@ PULL_DWN_CTRL_3
	.word 0x00000000	@ GATE_INH_CTRL_0
	.word 0x00000000	@ VOLTAGE_CTRL_0
	.word 0x00000000	@ TEST_DBG_CTRL_0
	.word 0x00000006	@ MOD_CONF_CTRL_0
	.word 0x0000eaef	@ COMP_MODE_CTRL_0

MUX_CONFIG_OFFSETS:
	.align 1
	.byte 0x00		@ FUNC_MUX_CTRL_0
	.byte 0x04		@ FUNC_MUX_CTRL_1
	.byte 0x08		@ FUNC_MUX_CTRL_2
	.byte 0x10		@ FUNC_MUX_CTRL_3
	.byte 0x14		@ FUNC_MUX_CTRL_4
	.byte 0x18		@ FUNC_MUX_CTRL_5
	.byte 0x1c		@ FUNC_MUX_CTRL_6
	.byte 0x20		@ FUNC_MUX_CTRL_7
	.byte 0x24		@ FUNC_MUX_CTRL_8
	.byte 0x28		@ FUNC_MUX_CTRL_9
	.byte 0x2c		@ FUNC_MUX_CTRL_A
	.byte 0x30		@ FUNC_MUX_CTRL_B
	.byte 0x34		@ FUNC_MUX_CTRL_C
	.byte 0x38		@ FUNC_MUX_CTRL_D
	.byte 0x40		@ PULL_DWN_CTRL_0
	.byte 0x44		@ PULL_DWN_CTRL_1
	.byte 0x48		@ PULL_DWN_CTRL_2
	.byte 0x4c		@ PULL_DWN_CTRL_3
	.byte 0x50		@ GATE_INH_CTRL_0
	.byte 0x60		@ VOLTAGE_CTRL_0
	.byte 0x70		@ TEST_DBG_CTRL_0
	.byte 0x80		@ MOD_CONF_CTRL_0
	.byte 0x0c		@ COMP_MODE_CTRL_0
	.byte 0xff

.globl lowlevel_init
lowlevel_init:
	/* Improve performance a bit... */
	mrc	p15, 0, r1, c0, c0, 0		@ read C15 ID register
	mrc	p15, 0, r1, c0, c0, 1		@ read C15 Cache information register
	mrc	p15, 0, r1, c1, c0, 0		@ read C15 Control register
	orr	r1, r1, #0x1000			@ enable I-cache, map interrupt vector 0xffff0000
	mcr	p15, 0, r1, c1, c0, 0		@ write C15 Control register
	mov	r1, #0x00
	mcr	p15, 0, r1, c7, c5, 0		@ Flush I-cache
	nop
	nop
	nop
	nop

	/* Setup clocking mode */
	ldr	r0, OMAP5910_MPU_CLKM_BASE	@ base of CLOCK unit
	ldrh	r1, [r0, #0x18]			@ ARM_SYST - get reset status
	bic	r1, r1, #(7 << 11)		@ clear clock select
	orr	r1, r1, #(2 << 11)		@ set synchronous scalable
	mov	r2, #0
loop:
	cmp	r2, #1				@ this loop will wait for at least 100 cycles
	streqh	r1, [r0, #0x18]			@ before issuing next request from MPU
	add	r2, r2, #1			@ on the 1st run code is loaded into I-cache
	cmp	r2, #16				@ and second run will set clocking mode
	bne	loop
	nop

	/* Setup clock dividers */
	ldr	r1, _OMAP5910_ARM_CKCTL
	orr	r1, r1, #0x2000			@ enable DSP clock
	strh	r1, [r0]			@ setup clock divisors

	/* Setup DPLL to generate requested freq */
	ldr	r0, OMAP5910_DPLL1_BASE		@ base of DPLL1 register
	mov	r1, #0x0010			@ set PLL_ENABLE
	orr	r1, r1, #0x2000			@ set IOB to new locking
	orr	r1, r1, #(OMAP5910_DPLL_MUL << 7) @ setup multiplier CLKREF
	orr	r1, r1, #(OMAP5910_DPLL_DIV << 5) @ setup divider CLKREF
	strh	r1, [r0]			@ write

locking:
	ldrh	r1, [r0]			@ get DPLL value
	tst	r1, #0x01
	beq	locking				@ while LOCK not set

	/* Enable clock */
	ldr	r0, OMAP5910_MPU_CLKM_BASE	@ base of CLOCK unit
	mov	r1, #(1 << 10)			@ disable idle mode do not check
						@ nWAKEUP pin, other remain active
	strh	r1, [r0, #0x04]
	ldr	r1, _OMAP5910_ARM_EN_CLK
	strh	r1, [r0, #0x08]
	mov	r1, #0x003f			@ FLASH.RP not enabled in idle and
	strh	r1, [r0, #0x0c]			@ max delayed ( 32 x CLKIN )

	/* Configure 5910 pins functions to match our board. */
	ldr     r0, MUX_CONFIG_BASE
	adr	r1, MUX_CONFIG_VALUES
	adr	r2, MUX_CONFIG_OFFSETS
next_mux_cfg:
	ldrb	r3, [r2], #1
	ldr	r4, [r1], #4
	cmp	r3, #0xff
	strne	r4, [r0, r3]
	bne	next_mux_cfg

	/* Configure GPIO pins (also disables Green LED) */
	ldr	r0, OMAP5910_GPIO_BASE
	ldr	r1, GPIO_OUTPUT
	strh    r1, [r0, #0x04]
	ldr	r1, GPIO_DIRECTION
	strh	r1, [r0, #0x08]

	/* EnablePeripherals */
	ldr	r0, OMAP5910_MPU_CLKM_BASE	@ CLOCK unit
	mov	r1, #0x0001			@ Peripheral enable
	strh	r1, [r0, #0x14]

	/* Program LED Pulse Generator */
	ldr	r0, OMAP5910_LPG1_BASE		@ 1st LED Pulse Generator
	mov	r1, #0x7F			@ Set obscure frequency in
	strb	r1, [r0, #0x00]			@ LCR
	mov	r1, #0x01			@ Enable clock (CLK_EN) in
	strb    r1, [r0, #0x04]			@ PMR

	/* TIPB Lock UART1 */
	ldr	r0, OMAP5910_TIPB_SWITCHES_BASE	@ prepare base of TIPB switches
	mov	r1, #1				@ ARM allocated
	strh	r1, [r0,#0x04]			@ clear IRQ line and status bits
	strh	r1, [r0,#0x00]
	ldrh	r1, [r0,#0x04]

	/* Disable watchdog */
	ldr	r0, OMAP5910_MPU_WD_TIMER_BASE
	mov	r1, #0xf5
	strh	r1, [r0, #0x8]
	mov	r1, #0xa0
	strh	r1, [r0, #0x8]

	/* Enable MCLK */
	ldr	r0, OMAP5910_ULPD_PWR_MNG_BASE
	mov	r1, #0x6
	strh	r1, [r0, #0x34]
	strh	r1, [r0, #0x34]

	/* Setup clock divisors */
	ldr	r0, OMAP5910_ULPD_PWR_MNG_BASE	@ base of ULDPL DPLL1 register

	mov	r1, #0x0010			@ set PLL_ENABLE
	orr	r1, r1, #0x2000			@ set IOB to new locking
	strh	r1, [r0]			@ write

ulocking:
	ldrh	r1, [r0]			@ get DPLL value
	tst	r1, #1
	beq	ulocking			@ while LOCK not set

	/* EMIF init */
	ldr	r0, OMAP5910_MPU_TC_BASE
	ldrh	r1, [r0, #0x0c]			@ EMIFS_CONFIG_REG
	bic	r1, r1, #0x0c			@ pwr down disabled, flash WP
	orr	r1, r1, #0x01
	str	r1, [r0, #0x0c]

	ldr	r1, VAL_EMIFS_CS0_CONFIG
	str	r1, [r0, #0x10]			@ EMIFS_CS0_CONFIG
	ldr	r1, VAL_EMIFS_CS1_CONFIG
	str	r1, [r0, #0x14]			@ EMIFS_CS1_CONFIG
	ldr	r1, VAL_EMIFS_CS2_CONFIG
	str	r1, [r0, #0x18]			@ EMIFS_CS2_CONFIG
	ldr	r1, VAL_EMIFS_CS3_CONFIG
	str	r1, [r0, #0x1c]			@ EMIFS_CS3_CONFIG
	ldr	r1, VAL_EMIFS_DYN_WAIT
	str	r1, [r0, #0x40]			@ EMIFS_CFG_DYN_WAIT

	/* Setup SDRAM */
	ldr	r1, VAL_EMIFF_SDRAM_CONFIG
	str	r1, [r0, #0x20]			@ EMIFF_SDRAM_CONFIG
	ldr	r1, VAL_EMIFF_SDRAM_CONFIG2
	str	r1, [r0, #0x3c]			@ EMIFF_SDRAM_CONFIG2
	ldr	r1, VAL_EMIFF_MRS
	str	r1, [r0, #0x24]			@ EMIFF_MRS
	/* SDRAM needs 100us to stabilize */
	mov	r0, #0x4000
sdelay:
	subs	r0, r0, #0x1
	bne	sdelay

	/* back to arch calling code */
	mov	pc, lr
.end
Commit	Line	Data
ac7eb8a3 WD	1	/*
	2	* Board specific setup info
	3	*
	4	* (C) Copyright 2004 Ales Jindra <[email protected]>
	5	* (C) Copyright 2005 Ladislav Michl <[email protected]>
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26	#include <config.h>
	27	#include <version.h>
	28
	29	_TEXT_BASE:
	30	.word TEXT_BASE /* SDRAM load addr from config.mk */
	31
	32	OMAP5910_LPG1_BASE: .word 0xfffbd000
	33	OMAP5910_TIPB_SWITCHES_BASE: .word 0xfffbc800
	34	OMAP5910_MPU_TC_BASE: .word 0xfffecc00
	35	OMAP5910_MPU_CLKM_BASE: .word 0xfffece00
	36	OMAP5910_ULPD_PWR_MNG_BASE: .word 0xfffe0800
	37	OMAP5910_DPLL1_BASE: .word 0xfffecf00
	38	OMAP5910_GPIO_BASE: .word 0xfffce000
	39	OMAP5910_MPU_WD_TIMER_BASE: .word 0xfffec800
	40	OMAP5910_MPUI_BASE: .word 0xfffec900
	41
	42	_OMAP5910_ARM_CKCTL: .word OMAP5910_ARM_CKCTL
	43	_OMAP5910_ARM_EN_CLK: .word OMAP5910_ARM_EN_CLK
	44
	45	OMAP5910_MPUI_CTRL: .word 0x0000ff1b
	46
	47	VAL_EMIFS_CS0_CONFIG: .word 0x00009090
	48	VAL_EMIFS_CS1_CONFIG: .word 0x00003031
	49	VAL_EMIFS_CS2_CONFIG: .word 0x0000a0a1
	50	VAL_EMIFS_CS3_CONFIG: .word 0x0000c0c0
	51	VAL_EMIFS_DYN_WAIT: .word 0x00000000
	52	/* autorefresh counter 0x246 ((64000000/13.4)-400)/8192) */
	53	/* SLRF SD_RET ARE SDRAM_TYPE ARCV SDRAM_FREQUENCY PWD CLK */
	54
	55	#if (PHYS_SDRAM_1_SIZE == SZ_32M)
	56	VAL_EMIFF_SDRAM_CONFIG: .word ((0 << 0) \| (0 << 1) \| (3 << 2) \| (0xf << 4) \| (0x246 << 8) \| (0 << 24) \| (0 << 26) \| (0 << 27))
	57	#else
	58	VAL_EMIFF_SDRAM_CONFIG: .word ((0 << 0) \| (0 << 1) \| (3 << 2) \| (0xd << 4) \| (0x246 << 8) \| (0 << 24) \| (0 << 26) \| (0 << 27))
	59	#endif
	60
b9365a26	61	VAL_EMIFF_SDRAM_CONFIG2: .word 0x00000003
ac7eb8a3 WD	62	VAL_EMIFF_MRS: .word 0x00000037
ac7eb8a3 WD	63
b9365a26	64	/*
ac7eb8a3 WD	65	* GPIO04 - Green LED (Red LED is connected to LED Pulse Generator)
	66	* GPIO07 - LAN91C111 reset
	67	*/
	68	GPIO_DIRECTION:
	69	.word 0x0000ff6f
	70	/*
	71	* Disable everything (green LED is connected via invertor)
	72	*/
	73	GPIO_OUTPUT:
	74	.word 0x00000010
	75
	76	MUX_CONFIG_BASE:
	77	.word 0xfffe1000
	78
	79	MUX_CONFIG_VALUES:
	80	.align 4
	81	.word 0x00000000 @ FUNC_MUX_CTRL_0
	82	.word 0x00000000 @ FUNC_MUX_CTRL_1
	83	.word 0x00000000 @ FUNC_MUX_CTRL_2
	84	.word 0x00000000 @ FUNC_MUX_CTRL_3
	85	.word 0x00000000 @ FUNC_MUX_CTRL_4
	86	.word 0x02080480 @ FUNC_MUX_CTRL_5
	87	.word 0x0100001c @ FUNC_MUX_CTRL_6
	88	.word 0x0004800b @ FUNC_MUX_CTRL_7
	89	.word 0x10001200 @ FUNC_MUX_CTRL_8
	90	.word 0x01201012 @ FUNC_MUX_CTRL_9
	91	.word 0x02082248 @ FUNC_MUX_CTRL_A
	92	.word 0x00000248 @ FUNC_MUX_CTRL_B
	93	.word 0x12240000 @ FUNC_MUX_CTRL_C
	94	.word 0x00002000 @ FUNC_MUX_CTRL_D
	95	.word 0x00000000 @ PULL_DWN_CTRL_0
	96	.word 0x00000800 @ PULL_DWN_CTRL_1
	97	.word 0x01801000 @ PULL_DWN_CTRL_2
	98	.word 0x00000000 @ PULL_DWN_CTRL_3
	99	.word 0x00000000 @ GATE_INH_CTRL_0
	100	.word 0x00000000 @ VOLTAGE_CTRL_0
	101	.word 0x00000000 @ TEST_DBG_CTRL_0
	102	.word 0x00000006 @ MOD_CONF_CTRL_0
	103	.word 0x0000eaef @ COMP_MODE_CTRL_0
	104
	105	MUX_CONFIG_OFFSETS:
	106	.align 1
	107	.byte 0x00 @ FUNC_MUX_CTRL_0
	108	.byte 0x04 @ FUNC_MUX_CTRL_1
b9365a26	109	.byte 0x08 @ FUNC_MUX_CTRL_2
ac7eb8a3 WD	110	.byte 0x10 @ FUNC_MUX_CTRL_3
	111	.byte 0x14 @ FUNC_MUX_CTRL_4
	112	.byte 0x18 @ FUNC_MUX_CTRL_5
	113	.byte 0x1c @ FUNC_MUX_CTRL_6
	114	.byte 0x20 @ FUNC_MUX_CTRL_7
	115	.byte 0x24 @ FUNC_MUX_CTRL_8
	116	.byte 0x28 @ FUNC_MUX_CTRL_9
	117	.byte 0x2c @ FUNC_MUX_CTRL_A
	118	.byte 0x30 @ FUNC_MUX_CTRL_B
	119	.byte 0x34 @ FUNC_MUX_CTRL_C
	120	.byte 0x38 @ FUNC_MUX_CTRL_D
	121	.byte 0x40 @ PULL_DWN_CTRL_0
	122	.byte 0x44 @ PULL_DWN_CTRL_1
	123	.byte 0x48 @ PULL_DWN_CTRL_2
	124	.byte 0x4c @ PULL_DWN_CTRL_3
	125	.byte 0x50 @ GATE_INH_CTRL_0
	126	.byte 0x60 @ VOLTAGE_CTRL_0
	127	.byte 0x70 @ TEST_DBG_CTRL_0
	128	.byte 0x80 @ MOD_CONF_CTRL_0
	129	.byte 0x0c @ COMP_MODE_CTRL_0
	130	.byte 0xff
	131
addb2e16 BS	132	.globl lowlevel_init
addb2e16 BS	133	lowlevel_init:
ac7eb8a3 WD	134	/* Improve performance a bit... */
	135	mrc p15, 0, r1, c0, c0, 0 @ read C15 ID register
	136	mrc p15, 0, r1, c0, c0, 1 @ read C15 Cache information register
	137	mrc p15, 0, r1, c1, c0, 0 @ read C15 Control register
	138	orr r1, r1, #0x1000 @ enable I-cache, map interrupt vector 0xffff0000
	139	mcr p15, 0, r1, c1, c0, 0 @ write C15 Control register
	140	mov r1, #0x00
	141	mcr p15, 0, r1, c7, c5, 0 @ Flush I-cache
	142	nop
	143	nop
	144	nop
	145	nop
	146
	147	/* Setup clocking mode */
87a5c73d WD	148	ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit
87a5c73d WD	149	ldrh r1, [r0, #0x18] @ ARM_SYST - get reset status
ac7eb8a3 WD	150	bic r1, r1, #(7 << 11) @ clear clock select
ac7eb8a3 WD	151	orr r1, r1, #(2 << 11) @ set synchronous scalable
87a5c73d WD	152	mov r2, #0
	153	loop:
	154	cmp r2, #1 @ this loop will wait for at least 100 cycles
	155	streqh r1, [r0, #0x18] @ before issuing next request from MPU
	156	add r2, r2, #1 @ on the 1st run code is loaded into I-cache
	157	cmp r2, #16 @ and second run will set clocking mode
	158	bne loop
ac7eb8a3 WD	159	nop
ac7eb8a3 WD	160
87a5c73d	161	/* Setup clock dividers */
ac7eb8a3 WD	162	ldr r1, _OMAP5910_ARM_CKCTL
ac7eb8a3 WD	163	orr r1, r1, #0x2000 @ enable DSP clock
87a5c73d	164	strh r1, [r0] @ setup clock divisors
ac7eb8a3 WD	165
	166	/* Setup DPLL to generate requested freq */
	167	ldr r0, OMAP5910_DPLL1_BASE @ base of DPLL1 register
	168	mov r1, #0x0010 @ set PLL_ENABLE
	169	orr r1, r1, #0x2000 @ set IOB to new locking
	170	orr r1, r1, #(OMAP5910_DPLL_MUL << 7) @ setup multiplier CLKREF
	171	orr r1, r1, #(OMAP5910_DPLL_DIV << 5) @ setup divider CLKREF
	172	strh r1, [r0] @ write
	173
	174	locking:
	175	ldrh r1, [r0] @ get DPLL value
	176	tst r1, #0x01
	177	beq locking @ while LOCK not set
	178
	179	/* Enable clock */
	180	ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit
	181	mov r1, #(1 << 10) @ disable idle mode do not check
	182	@ nWAKEUP pin, other remain active
b9365a26	183	strh r1, [r0, #0x04]
ac7eb8a3 WD	184	ldr r1, _OMAP5910_ARM_EN_CLK
	185	strh r1, [r0, #0x08]
	186	mov r1, #0x003f @ FLASH.RP not enabled in idle and
87a5c73d	187	strh r1, [r0, #0x0c] @ max delayed ( 32 x CLKIN )
ac7eb8a3 WD	188
	189	/* Configure 5910 pins functions to match our board. */
	190	ldr r0, MUX_CONFIG_BASE
	191	adr r1, MUX_CONFIG_VALUES
	192	adr r2, MUX_CONFIG_OFFSETS
b9365a26	193	next_mux_cfg:
ac7eb8a3 WD	194	ldrb r3, [r2], #1
	195	ldr r4, [r1], #4
	196	cmp r3, #0xff
	197	strne r4, [r0, r3]
	198	bne next_mux_cfg
	199
	200	/* Configure GPIO pins (also disables Green LED) */
	201	ldr r0, OMAP5910_GPIO_BASE
	202	ldr r1, GPIO_OUTPUT
	203	strh r1, [r0, #0x04]
	204	ldr r1, GPIO_DIRECTION
	205	strh r1, [r0, #0x08]
	206
	207	/* EnablePeripherals */
	208	ldr r0, OMAP5910_MPU_CLKM_BASE @ CLOCK unit
	209	mov r1, #0x0001 @ Peripheral enable
	210	strh r1, [r0, #0x14]
	211
	212	/* Program LED Pulse Generator */
	213	ldr r0, OMAP5910_LPG1_BASE @ 1st LED Pulse Generator
	214	mov r1, #0x7F @ Set obscure frequency in
	215	strb r1, [r0, #0x00] @ LCR
	216	mov r1, #0x01 @ Enable clock (CLK_EN) in
	217	strb r1, [r0, #0x04] @ PMR
	218
	219	/* TIPB Lock UART1 */
	220	ldr r0, OMAP5910_TIPB_SWITCHES_BASE @ prepare base of TIPB switches
	221	mov r1, #1 @ ARM allocated
	222	strh r1, [r0,#0x04] @ clear IRQ line and status bits
	223	strh r1, [r0,#0x00]
	224	ldrh r1, [r0,#0x04]
	225
	226	/* Disable watchdog */
	227	ldr r0, OMAP5910_MPU_WD_TIMER_BASE
	228	mov r1, #0xf5
	229	strh r1, [r0, #0x8]
	230	mov r1, #0xa0
	231	strh r1, [r0, #0x8]
	232
	233	/* Enable MCLK */
	234	ldr r0, OMAP5910_ULPD_PWR_MNG_BASE
	235	mov r1, #0x6
	236	strh r1, [r0, #0x34]
	237	strh r1, [r0, #0x34]
	238
	239	/* Setup clock divisors */
b9365a26	240	ldr r0, OMAP5910_ULPD_PWR_MNG_BASE @ base of ULDPL DPLL1 register
ac7eb8a3 WD	241
ac7eb8a3 WD	242	mov r1, #0x0010 @ set PLL_ENABLE
b9365a26 WD	243	orr r1, r1, #0x2000 @ set IOB to new locking
b9365a26 WD	244	strh r1, [r0] @ write
ac7eb8a3 WD	245
	246	ulocking:
	247	ldrh r1, [r0] @ get DPLL value
b9365a26	248	tst r1, #1
ac7eb8a3 WD	249	beq ulocking @ while LOCK not set
	250
	251	/* EMIF init */
	252	ldr r0, OMAP5910_MPU_TC_BASE
	253	ldrh r1, [r0, #0x0c] @ EMIFS_CONFIG_REG
	254	bic r1, r1, #0x0c @ pwr down disabled, flash WP
	255	orr r1, r1, #0x01
	256	str r1, [r0, #0x0c]
b9365a26	257
ac7eb8a3 WD	258	ldr r1, VAL_EMIFS_CS0_CONFIG
	259	str r1, [r0, #0x10] @ EMIFS_CS0_CONFIG
	260	ldr r1, VAL_EMIFS_CS1_CONFIG
	261	str r1, [r0, #0x14] @ EMIFS_CS1_CONFIG
	262	ldr r1, VAL_EMIFS_CS2_CONFIG
	263	str r1, [r0, #0x18] @ EMIFS_CS2_CONFIG
	264	ldr r1, VAL_EMIFS_CS3_CONFIG
	265	str r1, [r0, #0x1c] @ EMIFS_CS3_CONFIG
	266	ldr r1, VAL_EMIFS_DYN_WAIT
	267	str r1, [r0, #0x40] @ EMIFS_CFG_DYN_WAIT
	268
	269	/* Setup SDRAM */
	270	ldr r1, VAL_EMIFF_SDRAM_CONFIG
	271	str r1, [r0, #0x20] @ EMIFF_SDRAM_CONFIG
	272	ldr r1, VAL_EMIFF_SDRAM_CONFIG2
	273	str r1, [r0, #0x3c] @ EMIFF_SDRAM_CONFIG2
	274	ldr r1, VAL_EMIFF_MRS
	275	str r1, [r0, #0x24] @ EMIFF_MRS
	276	/* SDRAM needs 100us to stabilize */
	277	mov r0, #0x4000
	278	sdelay:
	279	subs r0, r0, #0x1
53677ef1	280	bne sdelay
ac7eb8a3 WD	281
	282	/* back to arch calling code */
	283	mov pc, lr
	284	.end