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[u-boot.git] / board / netphone / netphone.c
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04a85b3b
WD		 1/*
2 * (C) Copyright 2000-2004
c26e454d 3 * Pantelis Antoniou, Intracom S.A., [email protected]
04a85b3b
WD		 4 * Wolfgang Denk, DENX Software Engineering, [email protected].
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25/*
26 * Pantelis Antoniou, Intracom S.A., [email protected]
27 * U-Boot port on NetTA4 board
28 */
29
30#include <common.h>
31#include <miiphy.h>
32#include <sed156x.h>
5cf91d6b 33#include <status_led.h>
04a85b3b
WD		 34
35#include "mpc8xx.h"
36
37#ifdef CONFIG_HW_WATCHDOG
38#include <watchdog.h>
39#endif
40
63ff004c
MB		 41int fec8xx_miiphy_read(char *devname, unsigned char addr,
42 unsigned char reg, unsigned short *value);
43int fec8xx_miiphy_write(char *devname, unsigned char addr,
44 unsigned char reg, unsigned short value);
45
04a85b3b
WD		 46/****************************************************************/
47
48/* some sane bit macros */
49#define _BD(_b) (1U << (31-(_b)))
50#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
51
52#define _BW(_b) (1U << (15-(_b)))
53#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
54
55#define _BB(_b) (1U << (7-(_b)))
56#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
57
58#define _B(_b) _BD(_b)
59#define _BR(_l, _h) _BDR(_l, _h)
60
61/****************************************************************/
62
63/*
64 * Check Board Identity:
65 *
66 * Return 1 always.
67 */
68
69int checkboard(void)
70{
c26e454d 71 printf ("Intracom NetPhone V%d\n", CONFIG_NETPHONE_VERSION);
04a85b3b
WD		 72 return (0);
73}
74
75/****************************************************************/
76
77#define _NOT_USED_ 0xFFFFFFFF
78
79/****************************************************************/
80
81#define CS_0000 0x00000000
82#define CS_0001 0x10000000
83#define CS_0010 0x20000000
84#define CS_0011 0x30000000
85#define CS_0100 0x40000000
86#define CS_0101 0x50000000
87#define CS_0110 0x60000000
88#define CS_0111 0x70000000
89#define CS_1000 0x80000000
90#define CS_1001 0x90000000
91#define CS_1010 0xA0000000
92#define CS_1011 0xB0000000
93#define CS_1100 0xC0000000
94#define CS_1101 0xD0000000
95#define CS_1110 0xE0000000
96#define CS_1111 0xF0000000
97
98#define BS_0000 0x00000000
99#define BS_0001 0x01000000
100#define BS_0010 0x02000000
101#define BS_0011 0x03000000
102#define BS_0100 0x04000000
103#define BS_0101 0x05000000
104#define BS_0110 0x06000000
105#define BS_0111 0x07000000
106#define BS_1000 0x08000000
107#define BS_1001 0x09000000
108#define BS_1010 0x0A000000
109#define BS_1011 0x0B000000
110#define BS_1100 0x0C000000
111#define BS_1101 0x0D000000
112#define BS_1110 0x0E000000
113#define BS_1111 0x0F000000
114
c26e454d
WD		 115#define GPL0_AAAA 0x00000000
116#define GPL0_AAA0 0x00200000
117#define GPL0_AAA1 0x00300000
118#define GPL0_000A 0x00800000
119#define GPL0_0000 0x00A00000
120#define GPL0_0001 0x00B00000
121#define GPL0_111A 0x00C00000
122#define GPL0_1110 0x00E00000
123#define GPL0_1111 0x00F00000
124
125#define GPL1_0000 0x00000000
126#define GPL1_0001 0x00040000
127#define GPL1_1110 0x00080000
128#define GPL1_1111 0x000C0000
129
130#define GPL2_0000 0x00000000
131#define GPL2_0001 0x00010000
132#define GPL2_1110 0x00020000
133#define GPL2_1111 0x00030000
134
135#define GPL3_0000 0x00000000
136#define GPL3_0001 0x00004000
137#define GPL3_1110 0x00008000
138#define GPL3_1111 0x0000C000
04a85b3b
WD		 139
140#define GPL4_0000 0x00000000
141#define GPL4_0001 0x00001000
142#define GPL4_1110 0x00002000
143#define GPL4_1111 0x00003000
144
145#define GPL5_0000 0x00000000
146#define GPL5_0001 0x00000400
147#define GPL5_1110 0x00000800
148#define GPL5_1111 0x00000C00
149#define LOOP 0x00000080
150
151#define EXEN 0x00000040
152
153#define AMX_COL 0x00000000
154#define AMX_ROW 0x00000020
155#define AMX_MAR 0x00000030
156
157#define NA 0x00000008
158
159#define UTA 0x00000004
160
161#define TODT 0x00000002
162
163#define LAST 0x00000001
164
c26e454d
WD		 165#define A10_AAAA GPL0_AAAA
166#define A10_AAA0 GPL0_AAA0
167#define A10_AAA1 GPL0_AAA1
168#define A10_000A GPL0_000A
169#define A10_0000 GPL0_0000
170#define A10_0001 GPL0_0001
171#define A10_111A GPL0_111A
172#define A10_1110 GPL0_1110
173#define A10_1111 GPL0_1111
174
175#define RAS_0000 GPL1_0000
176#define RAS_0001 GPL1_0001
177#define RAS_1110 GPL1_1110
178#define RAS_1111 GPL1_1111
179
180#define CAS_0000 GPL2_0000
181#define CAS_0001 GPL2_0001
182#define CAS_1110 GPL2_1110
183#define CAS_1111 GPL2_1111
184
185#define WE_0000 GPL3_0000
186#define WE_0001 GPL3_0001
187#define WE_1110 GPL3_1110
188#define WE_1111 GPL3_1111
189
04a85b3b
WD		 190/* #define CAS_LATENCY 3 */
191#define CAS_LATENCY 2
192
193const uint sdram_table[0x40] = {
194
195#if CAS_LATENCY == 3
196 /* RSS */
197 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
198 CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
199 CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
200 CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
201 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
202 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
203 _NOT_USED_, _NOT_USED_,
204
205 /* RBS */
206 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
207 CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
208 CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
209 CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
210 CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
211 CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
212 CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, /* PALL */
213 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, /* NOP */
214 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
215 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
216
217 /* WSS */
218 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
219 CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
220 CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */
221 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
222 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
223 _NOT_USED_, _NOT_USED_, _NOT_USED_,
224
225 /* WBS */
226 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
227 CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
228 CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL, /* WRITE */
229 CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
230 CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
231 CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
232 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
233 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
234 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
235 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
236 _NOT_USED_, _NOT_USED_, _NOT_USED_,
237#endif
238
239#if CAS_LATENCY == 2
240 /* RSS */
241 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
242 CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */
243 CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
244 CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */
245 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
246 _NOT_USED_,
247 _NOT_USED_, _NOT_USED_,
248
249 /* RBS */
250 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
251 CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */
252 CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
253 CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
254 CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
255 CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
256 CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */
257 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
258 _NOT_USED_,
259 _NOT_USED_, _NOT_USED_, _NOT_USED_,
260 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
261
262 /* WSS */
263 CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
264 CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */
265 CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */
266 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
267 _NOT_USED_,
268 _NOT_USED_, _NOT_USED_,
269 _NOT_USED_,
270
271 /* WBS */
272 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
273 CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */
274 CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL, /* WRITE */
275 CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
276 CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
277 CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA, /* NOP */
278 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
279 _NOT_USED_,
280 _NOT_USED_, _NOT_USED_, _NOT_USED_,
281 _NOT_USED_, _NOT_USED_, _NOT_USED_,
282 _NOT_USED_, _NOT_USED_,
283
284#endif
285
286 /* UPT */
287 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP, /* ATRFR */
288 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
289 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
290 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
291 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP, /* NOP */
292 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
293 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
294 _NOT_USED_, _NOT_USED_,
295
296 /* EXC */
297 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST,
298 _NOT_USED_,
299
300 /* REG */
301 CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA,
302 CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST,
303};
304
c26e454d
WD		 305#if CONFIG_NETPHONE_VERSION == 2
306static const uint nandcs_table[0x40] = {
307 /* RSS */
308 CS_1000 | GPL4_1111 | GPL5_1111 | UTA,
309 CS_0000 | GPL4_1110 | GPL5_1111 | UTA,
310 CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
311 CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
312 CS_0000 | GPL4_0000 | GPL5_1111,
313 CS_0000 | GPL4_0001 | GPL5_1111 | UTA,
314 CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
315 CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST, /* NOP */
316
317 /* RBS */
318 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
319 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
320 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
321 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
322
323 /* WSS */
324 CS_1000 | GPL4_1111 | GPL5_1110 | UTA,
325 CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
326 CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
327 CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
328 CS_0000 | GPL4_1111 | GPL5_0001 | UTA,
329 CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
330 CS_0000 | GPL4_1111 | GPL5_1111,
331 CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST,
332
333 /* WBS */
334 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
335 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
336 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
337 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
338
339 /* UPT */
340 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
341 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
342 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
343
344 /* EXC */
345 CS_0001 | LAST,
346 _NOT_USED_,
347
348 /* REG */
349 CS_1110 ,
350 CS_0001 | LAST,
351};
352#endif
353
04a85b3b
WD		 354/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */
355/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */
356#define MAR_SDRAM_INIT ((CAS_LATENCY << 6) | 0x00000008LU)
357
358/* 8 */
359#define CFG_MAMR ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
360 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
361 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
362
363void check_ram(unsigned int addr, unsigned int size)
364{
365 unsigned int i, j, v, vv;
366 volatile unsigned int *p;
367 unsigned int pv;
368
369 p = (unsigned int *)addr;
370 pv = (unsigned int)p;
371 for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int))
372 *p++ = pv;
373
374 p = (unsigned int *)addr;
375 for (i = 0; i < size / sizeof(unsigned int); i++) {
376 v = (unsigned int)p;
377 vv = *p;
378 if (vv != v) {
379 printf("%p: read %08x instead of %08x\n", p, vv, v);
380 hang();
381 }
382 p++;
383 }
384
385 for (j = 0; j < 5; j++) {
386 switch (j) {
387 case 0: v = 0x00000000; break;
388 case 1: v = 0xffffffff; break;
389 case 2: v = 0x55555555; break;
390 case 3: v = 0xaaaaaaaa; break;
391 default:v = 0xdeadbeef; break;
392 }
393 p = (unsigned int *)addr;
394 for (i = 0; i < size / sizeof(unsigned int); i++) {
395 *p = v;
396 vv = *p;
397 if (vv != v) {
398 printf("%p: read %08x instead of %08x\n", p, vv, v);
399 hang();
400 }
401 *p = ~v;
402 p++;
403 }
404 }
405}
406
407long int initdram(int board_type)
408{
409 volatile immap_t *immap = (immap_t *) CFG_IMMR;
410 volatile memctl8xx_t *memctl = &immap->im_memctl;
411 long int size;
412
c26e454d 413 upmconfig(UPMB, (uint *) sdram_table, sizeof(sdram_table) / sizeof(sdram_table[0]));
04a85b3b
WD		 414
415 /*
416 * Preliminary prescaler for refresh
417 */
418 memctl->memc_mptpr = MPTPR_PTP_DIV8;
419
420 memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */
421
422 /*
423 * Map controller bank 3 to the SDRAM bank at preliminary address.
424 */
425 memctl->memc_or3 = CFG_OR3_PRELIM;
426 memctl->memc_br3 = CFG_BR3_PRELIM;
427
428 memctl->memc_mbmr = CFG_MAMR & ~MAMR_PTAE; /* no refresh yet */
429
430 udelay(200);
431
432 /* perform SDRAM initialisation sequence */
433 memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3C); /* precharge all */
434 udelay(1);
435
436 memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(2) | MCR_MAD(0x30); /* refresh 2 times(0) */
437 udelay(1);
438
439 memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3E); /* exception program (write mar)*/
440 udelay(1);
441
442 memctl->memc_mbmr |= MAMR_PTAE; /* enable refresh */
443
444 udelay(10000);
445
446 {
447 u32 d1, d2;
448
449 d1 = 0xAA55AA55;
450 *(volatile u32 *)0 = d1;
451 d2 = *(volatile u32 *)0;
452 if (d1 != d2) {
453 printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
454 hang();
455 }
456
457 d1 = 0x55AA55AA;
458 *(volatile u32 *)0 = d1;
459 d2 = *(volatile u32 *)0;
460 if (d1 != d2) {
461 printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
462 hang();
463 }
464 }
465
466 size = get_ram_size((long *)0, SDRAM_MAX_SIZE);
467
04a85b3b
WD		 468 if (size == 0) {
469 printf("SIZE is zero: LOOP on 0\n");
470 for (;;) {
471 *(volatile u32 *)0 = 0;
472 (void)*(volatile u32 *)0;
473 }
474 }
475
476 return size;
477}
478
479/* ------------------------------------------------------------------------- */
480
481void reset_phys(void)
482{
483 int phyno;
484 unsigned short v;
485
486 udelay(10000);
487 /* reset the damn phys */
488 mii_init();
489
490 for (phyno = 0; phyno < 32; ++phyno) {
63ff004c 491 fec8xx_miiphy_read(NULL, phyno, PHY_PHYIDR1, &v);
04a85b3b
WD		 492 if (v == 0xFFFF)
493 continue;
63ff004c 494 fec8xx_miiphy_write(NULL, phyno, PHY_BMCR, PHY_BMCR_POWD);
04a85b3b 495 udelay(10000);
63ff004c
MB		 496 fec8xx_miiphy_write(NULL, phyno, PHY_BMCR,
497 PHY_BMCR_RESET | PHY_BMCR_AUTON);
04a85b3b
WD		 498 udelay(10000);
499 }
500}
501
502/* ------------------------------------------------------------------------- */
503
504/* GP = general purpose, SP = special purpose (on chip peripheral) */
505
506/* bits that can have a special purpose or can be configured as inputs/outputs */
507#define PA_GP_INMASK 0
508#define PA_GP_OUTMASK (_BW(3) | _BW(7) | _BW(10) | _BW(14) | _BW(15))
509#define PA_SP_MASK 0
510#define PA_ODR_VAL 0
511#define PA_GP_OUTVAL (_BW(3) | _BW(14) | _BW(15))
512#define PA_SP_DIRVAL 0
513
514#define PB_GP_INMASK _B(28)
515#define PB_GP_OUTMASK (_B(19) | _B(23) | _B(26) | _B(27) | _B(29) | _B(30))
516#define PB_SP_MASK (_BR(22, 25))
517#define PB_ODR_VAL 0
518#define PB_GP_OUTVAL (_B(26) | _B(27) | _B(29) | _B(30))
519#define PB_SP_DIRVAL 0
520
c26e454d 521#if CONFIG_NETPHONE_VERSION == 1
04a85b3b
WD		 522#define PC_GP_INMASK _BW(12)
523#define PC_GP_OUTMASK (_BW(10) | _BW(11) | _BW(13) | _BW(15))
c26e454d
WD		 524#elif CONFIG_NETPHONE_VERSION == 2
525#define PC_GP_INMASK (_BW(13) | _BW(15))
526#define PC_GP_OUTMASK (_BW(10) | _BW(11) | _BW(12))
527#endif
04a85b3b
WD		 528#define PC_SP_MASK 0
529#define PC_SOVAL 0
530#define PC_INTVAL 0
531#define PC_GP_OUTVAL (_BW(10) | _BW(11))
532#define PC_SP_DIRVAL 0
533
c26e454d 534#if CONFIG_NETPHONE_VERSION == 1
04a85b3b
WD		 535#define PE_GP_INMASK _B(31)
536#define PE_GP_OUTMASK (_B(17) | _B(18) |_B(20) | _B(24) | _B(27) | _B(28) | _B(29) | _B(30))
c26e454d
WD		 537#define PE_GP_OUTVAL (_B(20) | _B(24) | _B(27) | _B(28))
538#elif CONFIG_NETPHONE_VERSION == 2
539#define PE_GP_INMASK _BR(28, 31)
540#define PE_GP_OUTMASK (_B(17) | _B(18) |_B(20) | _B(24) | _B(27))
541#define PE_GP_OUTVAL (_B(20) | _B(24) | _B(27))
542#endif
04a85b3b
WD		 543#define PE_SP_MASK 0
544#define PE_ODR_VAL 0
04a85b3b
WD		 545#define PE_SP_DIRVAL 0
546
547int board_early_init_f(void)
548{
549 volatile immap_t *immap = (immap_t *) CFG_IMMR;
550 volatile iop8xx_t *ioport = &immap->im_ioport;
551 volatile cpm8xx_t *cpm = &immap->im_cpm;
552 volatile memctl8xx_t *memctl = &immap->im_memctl;
553
554 /* NAND chip select */
c26e454d 555#if CONFIG_NETPHONE_VERSION == 1
04a85b3b
WD		 556 memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK | OR_EHTR | OR_TRLX);
557 memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
c26e454d
WD		 558#elif CONFIG_NETPHONE_VERSION == 2
559 upmconfig(UPMA, (uint *) nandcs_table, sizeof(nandcs_table) / sizeof(nandcs_table[0]));
560 memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_G5LS);
561 memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V | BR_MS_UPMA);
562 memctl->memc_mamr = 0; /* all clear */
563#endif
04a85b3b
WD		 564
565 /* DSP chip select */
566 memctl->memc_or2 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_ACS_DIV2 | OR_SETA | OR_TRLX);
567 memctl->memc_br2 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
568
c26e454d
WD		 569#if CONFIG_NETPHONE_VERSION == 1
570 memctl->memc_br4 &= ~BR_V;
571#endif
04a85b3b
WD		 572 memctl->memc_br5 &= ~BR_V;
573 memctl->memc_br6 &= ~BR_V;
574 memctl->memc_br7 &= ~BR_V;
575
576 ioport->iop_padat = PA_GP_OUTVAL;
577 ioport->iop_paodr = PA_ODR_VAL;
578 ioport->iop_padir = PA_GP_OUTMASK | PA_SP_DIRVAL;
579 ioport->iop_papar = PA_SP_MASK;
580
581 cpm->cp_pbdat = PB_GP_OUTVAL;
582 cpm->cp_pbodr = PB_ODR_VAL;
583 cpm->cp_pbdir = PB_GP_OUTMASK | PB_SP_DIRVAL;
584 cpm->cp_pbpar = PB_SP_MASK;
585
586 ioport->iop_pcdat = PC_GP_OUTVAL;
587 ioport->iop_pcdir = PC_GP_OUTMASK | PC_SP_DIRVAL;
588 ioport->iop_pcso = PC_SOVAL;
589 ioport->iop_pcint = PC_INTVAL;
590 ioport->iop_pcpar = PC_SP_MASK;
591
592 cpm->cp_pedat = PE_GP_OUTVAL;
593 cpm->cp_peodr = PE_ODR_VAL;
594 cpm->cp_pedir = PE_GP_OUTMASK | PE_SP_DIRVAL;
595 cpm->cp_pepar = PE_SP_MASK;
596
597 return 0;
598}
599
3fe00109 600#if defined(CONFIG_CMD_NAND)
04a85b3b 601
addb2e16 602#include <linux/mtd/nand_legacy.h>
04a85b3b
WD		 603
604extern ulong nand_probe(ulong physadr);
605extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
606
607void nand_init(void)
608{
609 unsigned long totlen;
610
611 totlen = nand_probe(CFG_NAND_BASE);
612 printf ("%4lu MB\n", totlen >> 20);
613}
614#endif
615
616#ifdef CONFIG_HW_WATCHDOG
617
618void hw_watchdog_reset(void)
619{
620 /* XXX add here the really funky stuff */
621}
622
623#endif
624
625#ifdef CONFIG_SHOW_ACTIVITY
626
627static volatile int left_to_poll = PHONE_CONSOLE_POLL_HZ; /* poll */
628
629/* called from timer interrupt every 1/CFG_HZ sec */
630void board_show_activity(ulong timestamp)
631{
632 if (left_to_poll > -PHONE_CONSOLE_POLL_HZ)
633 --left_to_poll;
634}
635
636extern void phone_console_do_poll(void);
637
638static void do_poll(void)
639{
640 unsigned int base;
641
642 while (left_to_poll <= 0) {
643 phone_console_do_poll();
644 base = left_to_poll + PHONE_CONSOLE_POLL_HZ;
645 do {
646 left_to_poll = base;
647 } while (base != left_to_poll);
648 }
649}
650
651/* called when looping */
652void show_activity(int arg)
653{
654 do_poll();
655}
656
657#endif
658
659#if defined(CFG_CONSOLE_IS_IN_ENV) && defined(CFG_CONSOLE_OVERWRITE_ROUTINE)
660int overwrite_console(void)
661{
662 /* printf("overwrite_console called\n"); */
663 return 0;
664}
665#endif
666
667extern int drv_phone_init(void);
668extern int drv_phone_use_me(void);
5cf91d6b 669extern int drv_phone_is_idle(void);
04a85b3b
WD		 670
671int misc_init_r(void)
672{
673 return drv_phone_init();
674}
675
676int last_stage_init(void)
677{
678 int i;
679
c26e454d
WD		 680#if CONFIG_NETPHONE_VERSION == 2
681 /* assert peripheral reset */
682 ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat &= ~_BW(12);
683 for (i = 0; i < 10; i++)
684 udelay(1000);
685 ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat |= _BW(12);
686#endif
04a85b3b
WD		 687 reset_phys();
688
689 /* check in order to enable the local console */
690 left_to_poll = PHONE_CONSOLE_POLL_HZ;
691 i = CFG_HZ * 2;
692 while (i > 0) {
693
53677ef1 694 if (tstc()) {
04a85b3b
WD		 695 getc();
696 break;
697 }
698
699 do_poll();
700
701 if (drv_phone_use_me()) {
5cf91d6b
WD		 702 status_led_set(0, STATUS_LED_ON);
703 while (!drv_phone_is_idle()) {
704 do_poll();
705 udelay(1000000 / CFG_HZ);
706 }
707
04a85b3b
WD		 708 console_assign(stdin, "phone");
709 console_assign(stdout, "phone");
710 console_assign(stderr, "phone");
711 setenv("bootdelay", "-1");
712 break;
713 }
714
715 udelay(1000000 / CFG_HZ);
716 i--;
717 left_to_poll--;
718 }
719 left_to_poll = PHONE_CONSOLE_POLL_HZ;
720
721 return 0;
722}
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