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4745acaa 1/*
845c6c95 2 * (C) Copyright 2007-2008
4745acaa
SR		 3 * Stefan Roese, DENX Software Engineering, [email protected].
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 *
23 */
24
25#include <common.h>
26#include <ppc4xx.h>
4745acaa 27#include <i2c.h>
bf8324e4
SR		 28#include <libfdt.h>
29#include <fdt_support.h>
c7c6da23
SR		 30#include <asm/processor.h>
31#include <asm/io.h>
32#include <asm/gpio.h>
33#include <asm/4xx_pcie.h>
4745acaa 34
1218abf1
WD		 35DECLARE_GLOBAL_DATA_PTR;
36
4745acaa
SR		 37int board_early_init_f (void)
38{
39 unsigned long mfr;
4745acaa
SR		 40
41 /*----------------------------------------------------------------------+
42 * Interrupt controller setup for the Katmai 440SPe Evaluation board.
43 *-----------------------------------------------------------------------+
44 *-----------------------------------------------------------------------+
45 * Interrupt | Source | Pol. | Sensi.| Crit. |
46 *-----------+-----------------------------------+-------+-------+-------+
47 * IRQ 00 | UART0 | High | Level | Non |
48 * IRQ 01 | UART1 | High | Level | Non |
49 * IRQ 02 | IIC0 | High | Level | Non |
50 * IRQ 03 | IIC1 | High | Level | Non |
51 * IRQ 04 | PCI0X0 MSG IN | High | Level | Non |
52 * IRQ 05 | PCI0X0 CMD Write | High | Level | Non |
53 * IRQ 06 | PCI0X0 Power Mgt | High | Level | Non |
54 * IRQ 07 | PCI0X0 VPD Access | Rising| Edge | Non |
55 * IRQ 08 | PCI0X0 MSI level 0 | High | Lvl/ed| Non |
56 * IRQ 09 | External IRQ 15 - (PCI-Express) | pgm H | Pgm | Non |
57 * IRQ 10 | UIC2 Non-critical Int. | NA | NA | Non |
58 * IRQ 11 | UIC2 Critical Interrupt | NA | NA | Crit |
59 * IRQ 12 | PCI Express MSI Level 0 | Rising| Edge | Non |
60 * IRQ 13 | PCI Express MSI Level 1 | Rising| Edge | Non |
61 * IRQ 14 | PCI Express MSI Level 2 | Rising| Edge | Non |
62 * IRQ 15 | PCI Express MSI Level 3 | Rising| Edge | Non |
63 * IRQ 16 | UIC3 Non-critical Int. | NA | NA | Non |
64 * IRQ 17 | UIC3 Critical Interrupt | NA | NA | Crit |
65 * IRQ 18 | External IRQ 14 - (PCI-Express) | Pgm | Pgm | Non |
66 * IRQ 19 | DMA Channel 0 FIFO Full | High | Level | Non |
67 * IRQ 20 | DMA Channel 0 Stat FIFO | High | Level | Non |
68 * IRQ 21 | DMA Channel 1 FIFO Full | High | Level | Non |
69 * IRQ 22 | DMA Channel 1 Stat FIFO | High | Level | Non |
70 * IRQ 23 | I2O Inbound Doorbell | High | Level | Non |
71 * IRQ 24 | Inbound Post List FIFO Not Empt | High | Level | Non |
72 * IRQ 25 | I2O Region 0 LL PLB Write | High | Level | Non |
73 * IRQ 26 | I2O Region 1 LL PLB Write | High | Level | Non |
74 * IRQ 27 | I2O Region 0 HB PLB Write | High | Level | Non |
75 * IRQ 28 | I2O Region 1 HB PLB Write | High | Level | Non |
76 * IRQ 29 | GPT Down Count Timer | Rising| Edge | Non |
77 * IRQ 30 | UIC1 Non-critical Int. | NA | NA | Non |
78 * IRQ 31 | UIC1 Critical Interrupt | NA | NA | Crit. |
79 *------------------------------------------------------------------------
80 * IRQ 32 | Ext. IRQ 13 - (PCI-Express) |pgm (H)|pgm/Lvl| Non |
81 * IRQ 33 | MAL Serr | High | Level | Non |
82 * IRQ 34 | MAL Txde | High | Level | Non |
83 * IRQ 35 | MAL Rxde | High | Level | Non |
84 * IRQ 36 | DMC CE or DMC UE | High | Level | Non |
85 * IRQ 37 | EBC or UART2 | High |Lvl Edg| Non |
86 * IRQ 38 | MAL TX EOB | High | Level | Non |
87 * IRQ 39 | MAL RX EOB | High | Level | Non |
88 * IRQ 40 | PCIX0 MSI Level 1 | High |Lvl Edg| Non |
89 * IRQ 41 | PCIX0 MSI level 2 | High |Lvl Edg| Non |
90 * IRQ 42 | PCIX0 MSI level 3 | High |Lvl Edg| Non |
91 * IRQ 43 | L2 Cache | Risin | Edge | Non |
92 * IRQ 44 | GPT Compare Timer 0 | Risin | Edge | Non |
93 * IRQ 45 | GPT Compare Timer 1 | Risin | Edge | Non |
94 * IRQ 46 | GPT Compare Timer 2 | Risin | Edge | Non |
95 * IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non |
96 * IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non |
97 * IRQ 49 | Ext. IRQ 12 - PCI-X |pgm/Fal|pgm/Lvl| Non |
98 * IRQ 50 | Ext. IRQ 11 - |pgm (H)|pgm/Lvl| Non |
99 * IRQ 51 | Ext. IRQ 10 - |pgm (H)|pgm/Lvl| Non |
100 * IRQ 52 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non |
101 * IRQ 53 | Ext. IRQ 8 |pgm (H)|pgm/Lvl| Non |
102 * IRQ 54 | DMA Error | High | Level | Non |
103 * IRQ 55 | DMA I2O Error | High | Level | Non |
104 * IRQ 56 | Serial ROM | High | Level | Non |
105 * IRQ 57 | PCIX0 Error | High | Edge | Non |
106 * IRQ 58 | Ext. IRQ 7- |pgm (H)|pgm/Lvl| Non |
107 * IRQ 59 | Ext. IRQ 6- |pgm (H)|pgm/Lvl| Non |
108 * IRQ 60 | EMAC0 Interrupt | High | Level | Non |
109 * IRQ 61 | EMAC0 Wake-up | High | Level | Non |
110 * IRQ 62 | Reserved | High | Level | Non |
111 * IRQ 63 | XOR | High | Level | Non |
112 *-----------------------------------------------------------------------
113 * IRQ 64 | PE0 AL | High | Level | Non |
114 * IRQ 65 | PE0 VPD Access | Risin | Edge | Non |
115 * IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non |
116 * IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non |
117 * IRQ 68 | PE0 TCR | High | Level | Non |
118 * IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non |
119 * IRQ 70 | PE0 DCR Error | High | Level | Non |
120 * IRQ 71 | Reserved | N/A | N/A | Non |
121 * IRQ 72 | PE1 AL | High | Level | Non |
122 * IRQ 73 | PE1 VPD Access | Risin | Edge | Non |
123 * IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non |
124 * IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non |
125 * IRQ 76 | PE1 TCR | High | Level | Non |
126 * IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non |
127 * IRQ 78 | PE1 DCR Error | High | Level | Non |
128 * IRQ 79 | Reserved | N/A | N/A | Non |
129 * IRQ 80 | PE2 AL | High | Level | Non |
130 * IRQ 81 | PE2 VPD Access | Risin | Edge | Non |
131 * IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non |
132 * IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non |
133 * IRQ 84 | PE2 TCR | High | Level | Non |
134 * IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non |
135 * IRQ 86 | PE2 DCR Error | High | Level | Non |
136 * IRQ 87 | Reserved | N/A | N/A | Non |
137 * IRQ 88 | External IRQ(5) | Progr | Progr | Non |
138 * IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non |
139 * IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non |
140 * IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non |
141 * IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non |
142 * IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non |
143 * IRQ 94 | Reserved | N/A | N/A | Non |
144 * IRQ 95 | Reserved | N/A | N/A | Non |
145 *-----------------------------------------------------------------------
146 * IRQ 96 | PE0 INTA | High | Level | Non |
147 * IRQ 97 | PE0 INTB | High | Level | Non |
148 * IRQ 98 | PE0 INTC | High | Level | Non |
149 * IRQ 99 | PE0 INTD | High | Level | Non |
150 * IRQ 100 | PE1 INTA | High | Level | Non |
151 * IRQ 101 | PE1 INTB | High | Level | Non |
152 * IRQ 102 | PE1 INTC | High | Level | Non |
153 * IRQ 103 | PE1 INTD | High | Level | Non |
154 * IRQ 104 | PE2 INTA | High | Level | Non |
155 * IRQ 105 | PE2 INTB | High | Level | Non |
156 * IRQ 106 | PE2 INTC | High | Level | Non |
157 * IRQ 107 | PE2 INTD | Risin | Edge | Non |
158 * IRQ 108 | PCI Express MSI Level 4 | Risin | Edge | Non |
159 * IRQ 109 | PCI Express MSI Level 5 | Risin | Edge | Non |
160 * IRQ 110 | PCI Express MSI Level 6 | Risin | Edge | Non |
161 * IRQ 111 | PCI Express MSI Level 7 | Risin | Edge | Non |
162 * IRQ 116 | PCI Express MSI Level 12 | Risin | Edge | Non |
163 * IRQ 112 | PCI Express MSI Level 8 | Risin | Edge | Non |
164 * IRQ 113 | PCI Express MSI Level 9 | Risin | Edge | Non |
165 * IRQ 114 | PCI Express MSI Level 10 | Risin | Edge | Non |
166 * IRQ 115 | PCI Express MSI Level 11 | Risin | Edge | Non |
167 * IRQ 117 | PCI Express MSI Level 13 | Risin | Edge | Non |
168 * IRQ 118 | PCI Express MSI Level 14 | Risin | Edge | Non |
169 * IRQ 119 | PCI Express MSI Level 15 | Risin | Edge | Non |
170 * IRQ 120 | PCI Express MSI Level 16 | Risin | Edge | Non |
171 * IRQ 121 | PCI Express MSI Level 17 | Risin | Edge | Non |
172 * IRQ 122 | PCI Express MSI Level 18 | Risin | Edge | Non |
173 * IRQ 123 | PCI Express MSI Level 19 | Risin | Edge | Non |
174 * IRQ 124 | PCI Express MSI Level 20 | Risin | Edge | Non |
175 * IRQ 125 | PCI Express MSI Level 21 | Risin | Edge | Non |
176 * IRQ 126 | PCI Express MSI Level 22 | Risin | Edge | Non |
177 * IRQ 127 | PCI Express MSI Level 23 | Risin | Edge | Non |
178 *-----------+-----------------------------------+-------+-------+-------+ */
179 /*-------------------------------------------------------------------------+
180 * Put UICs in PowerPC440SPemode.
181 * Initialise UIC registers. Clear all interrupts. Disable all interrupts.
182 * Set critical interrupt values. Set interrupt polarities. Set interrupt
183 * trigger levels. Make bit 0 High priority. Clear all interrupts again.
184 *------------------------------------------------------------------------*/
185 mtdcr (uic3sr, 0xffffffff); /* Clear all interrupts */
186 mtdcr (uic3er, 0x00000000); /* disable all interrupts */
187 mtdcr (uic3cr, 0x00000000); /* Set Critical / Non Critical interrupts: */
188 mtdcr (uic3pr, 0xffffffff); /* Set Interrupt Polarities*/
189 mtdcr (uic3tr, 0x001fffff); /* Set Interrupt Trigger Levels */
190 mtdcr (uic3vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
191 mtdcr (uic3sr, 0x00000000); /* clear all interrupts*/
192 mtdcr (uic3sr, 0xffffffff); /* clear all interrupts*/
193
194
195 mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */
196 mtdcr (uic2er, 0x00000000); /* disable all interrupts*/
197 mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical interrupts*/
198 mtdcr (uic2pr, 0xebebebff); /* Set Interrupt Polarities*/
199 mtdcr (uic2tr, 0x74747400); /* Set Interrupt Trigger Levels */
200 mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
201 mtdcr (uic2sr, 0x00000000); /* clear all interrupts */
202 mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */
203
204 mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts*/
205 mtdcr (uic1er, 0x00000000); /* disable all interrupts*/
206 mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical interrupts*/
207 mtdcr (uic1pr, 0xffffffff); /* Set Interrupt Polarities */
208 mtdcr (uic1tr, 0x001f8040); /* Set Interrupt Trigger Levels*/
209 mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
210 mtdcr (uic1sr, 0x00000000); /* clear all interrupts*/
211 mtdcr (uic1sr, 0xffffffff); /* clear all interrupts*/
212
213 mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */
214 mtdcr (uic0er, 0x00000000); /* disable all interrupts excepted cascade to be checked */
215 mtdcr (uic0cr, 0x00104001); /* Set Critical / Non Critical interrupts*/
216 mtdcr (uic0pr, 0xffffffff); /* Set Interrupt Polarities*/
217 mtdcr (uic0tr, 0x010f0004); /* Set Interrupt Trigger Levels */
218 mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
219 mtdcr (uic0sr, 0x00000000); /* clear all interrupts*/
220 mtdcr (uic0sr, 0xffffffff); /* clear all interrupts*/
221
a27044b1
SR		 222 mfsdr(sdr_mfr, mfr);
223 mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */
224 mtsdr(sdr_mfr, mfr);
4745acaa 225
ba58e4c9 226 mtsdr(SDR0_PFC0, CFG_PFC0);
4745acaa 227
ba58e4c9
SR		 228 out32(GPIO0_OR, CFG_GPIO_OR);
229 out32(GPIO0_ODR, CFG_GPIO_ODR);
230 out32(GPIO0_TCR, CFG_GPIO_TCR);
4745acaa
SR		 231
232 return 0;
233}
234
235int checkboard (void)
236{
237 char *s = getenv("serial#");
238
239 printf("Board: Katmai - AMCC 440SPe Evaluation Board");
240 if (s != NULL) {
241 puts(", serial# ");
242 puts(s);
243 }
244 putc('\n');
245
246 return 0;
247}
248
845c6c95
SR		 249/*
250 * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
251 * board specific values.
252 */
253u32 ddr_wrdtr(u32 default_val) {
254 return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823);
255}
256
257u32 ddr_clktr(u32 default_val) {
258 return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
259}
260
4745acaa
SR		 261#if defined(CFG_DRAM_TEST)
262int testdram (void)
263{
264 uint *pstart = (uint *) 0x00000000;
265 uint *pend = (uint *) 0x08000000;
266 uint *p;
267
268 for (p = pstart; p < pend; p++)
269 *p = 0xaaaaaaaa;
270
271 for (p = pstart; p < pend; p++) {
272 if (*p != 0xaaaaaaaa) {
273 printf ("SDRAM test fails at: %08x\n", (uint) p);
274 return 1;
275 }
276 }
277
278 for (p = pstart; p < pend; p++)
279 *p = 0x55555555;
280
281 for (p = pstart; p < pend; p++) {
282 if (*p != 0x55555555) {
283 printf ("SDRAM test fails at: %08x\n", (uint) p);
284 return 1;
285 }
286 }
287 return 0;
288}
289#endif
290
291/*************************************************************************
292 * pci_pre_init
293 *
294 * This routine is called just prior to registering the hose and gives
295 * the board the opportunity to check things. Returning a value of zero
296 * indicates that things are bad & PCI initialization should be aborted.
297 *
298 * Different boards may wish to customize the pci controller structure
299 * (add regions, override default access routines, etc) or perform
300 * certain pre-initialization actions.
301 *
302 ************************************************************************/
466fff1a 303#if defined(CONFIG_PCI)
4745acaa
SR		 304int pci_pre_init(struct pci_controller * hose )
305{
306 unsigned long strap;
307
308 /*-------------------------------------------------------------------+
309 * The katmai board is always configured as the host & requires the
310 * PCI arbiter to be enabled.
311 *-------------------------------------------------------------------*/
312 mfsdr(sdr_sdstp1, strap);
313 if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) {
314 printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
315 return 0;
316 }
317
318 return 1;
319}
466fff1a 320#endif /* defined(CONFIG_PCI) */
4745acaa
SR		 321
322/*************************************************************************
323 * pci_target_init
324 *
325 * The bootstrap configuration provides default settings for the pci
326 * inbound map (PIM). But the bootstrap config choices are limited and
327 * may not be sufficient for a given board.
328 *
329 ************************************************************************/
330#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
331void pci_target_init(struct pci_controller * hose )
332{
4745acaa
SR		 333 /*-------------------------------------------------------------------+
334 * Disable everything
335 *-------------------------------------------------------------------*/
336 out32r( PCIX0_PIM0SA, 0 ); /* disable */
337 out32r( PCIX0_PIM1SA, 0 ); /* disable */
338 out32r( PCIX0_PIM2SA, 0 ); /* disable */
339 out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
340
341 /*-------------------------------------------------------------------+
342 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
343 * strapping options to not support sizes such as 128/256 MB.
344 *-------------------------------------------------------------------*/
345 out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
346 out32r( PCIX0_PIM0LAH, 0 );
347 out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
348 out32r( PCIX0_BAR0, 0 );
349
350 /*-------------------------------------------------------------------+
351 * Program the board's subsystem id/vendor id
352 *-------------------------------------------------------------------*/
353 out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
354 out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
355
356 out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
357}
358#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
359
360#if defined(CONFIG_PCI)
361/*************************************************************************
362 * is_pci_host
363 *
364 * This routine is called to determine if a pci scan should be
365 * performed. With various hardware environments (especially cPCI and
366 * PPMC) it's insufficient to depend on the state of the arbiter enable
367 * bit in the strap register, or generic host/adapter assumptions.
368 *
369 * Rather than hard-code a bad assumption in the general 440 code, the
370 * 440 pci code requires the board to decide at runtime.
371 *
372 * Return 0 for adapter mode, non-zero for host (monarch) mode.
373 *
374 *
375 ************************************************************************/
376int is_pci_host(struct pci_controller *hose)
377{
378 /* The katmai board is always configured as host. */
379 return 1;
380}
381
ba58e4c9
SR		 382int katmai_pcie_card_present(int port)
383{
384 u32 val;
385
386 val = in32(GPIO0_IR);
387 switch (port) {
388 case 0:
389 return !(val & GPIO_VAL(CFG_GPIO_PCIE_PRESENT0));
390 case 1:
391 return !(val & GPIO_VAL(CFG_GPIO_PCIE_PRESENT1));
392 case 2:
393 return !(val & GPIO_VAL(CFG_GPIO_PCIE_PRESENT2));
394 default:
395 return 0;
396 }
397}
398
4745acaa
SR		 399static struct pci_controller pcie_hose[3] = {{0},{0},{0}};
400
7f191393 401void pcie_setup_hoses(int busno)
4745acaa
SR		 402{
403 struct pci_controller *hose;
404 int i, bus;
d4cb2d17 405 int ret = 0;
6efc1fc0
GB		 406 char *env;
407 unsigned int delay;
4745acaa
SR		 408
409 /*
410 * assume we're called after the PCIX hose is initialized, which takes
411 * bus ID 0 and therefore start numbering PCIe's from 1.
412 */
7f191393 413 bus = busno;
4745acaa 414 for (i = 0; i <= 2; i++) {
ba58e4c9
SR		 415 /* Check for katmai card presence */
416 if (!katmai_pcie_card_present(i))
417 continue;
418
654f38b3 419 if (is_end_point(i))
d4cb2d17 420 ret = ppc4xx_init_pcie_endport(i);
654f38b3 421 else
d4cb2d17 422 ret = ppc4xx_init_pcie_rootport(i);
d4cb2d17 423 if (ret) {
654f38b3
SR		 424 printf("PCIE%d: initialization as %s failed\n", i,
425 is_end_point(i) ? "endpoint" : "root-complex");
4745acaa
SR		 426 continue;
427 }
428
429 hose = &pcie_hose[i];
430 hose->first_busno = bus;
7f191393
GB		 431 hose->last_busno = bus;
432 hose->current_busno = bus;
4745acaa
SR		 433
434 /* setup mem resource */
435 pci_set_region(hose->regions + 0,
436 CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
437 CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
438 CFG_PCIE_MEMSIZE,
d4cb2d17 439 PCI_REGION_MEM);
4745acaa
SR		 440 hose->region_count = 1;
441 pci_register_hose(hose);
442
d4cb2d17 443 if (is_end_point(i)) {
53677ef1 444 ppc4xx_setup_pcie_endpoint(hose, i);
d4cb2d17
SR		 445 /*
446 * Reson for no scanning is endpoint can not generate
447 * upstream configuration accesses.
53677ef1 448 */
d4cb2d17 449 } else {
53677ef1 450 ppc4xx_setup_pcie_rootpoint(hose, i);
d4cb2d17 451 env = getenv ("pciscandelay");
53677ef1
WD		 452 if (env != NULL) {
453 delay = simple_strtoul(env, NULL, 10);
d4cb2d17 454 if (delay > 5)
53677ef1 455 printf("Warning, expect noticable delay before "
d4cb2d17
SR		 456 "PCIe scan due to 'pciscandelay' value!\n");
457 mdelay(delay * 1000);
458 }
459
53677ef1
WD		 460 /*
461 * Config access can only go down stream
462 */
463 hose->last_busno = pci_hose_scan(hose);
464 bus = hose->last_busno + 1;
6efc1fc0 465 }
4745acaa
SR		 466 }
467}
468#endif /* defined(CONFIG_PCI) */
469
470int misc_init_f (void)
471{
472 uint reg;
473#if defined(CONFIG_STRESS)
474 uint i ;
475 uint disp;
476#endif
477
478 /* minimal init for PCIe */
479#if 0 /* test-only: test endpoint at some time, for now rootpoint only */
480 /* pci express 0 Endpoint Mode */
481 mfsdr(SDR0_PE0DLPSET, reg);
482 reg &= (~0x00400000);
483 mtsdr(SDR0_PE0DLPSET, reg);
484#else
485 /* pci express 0 Rootpoint Mode */
486 mfsdr(SDR0_PE0DLPSET, reg);
487 reg |= 0x00400000;
488 mtsdr(SDR0_PE0DLPSET, reg);
489#endif
490 /* pci express 1 Rootpoint Mode */
491 mfsdr(SDR0_PE1DLPSET, reg);
492 reg |= 0x00400000;
493 mtsdr(SDR0_PE1DLPSET, reg);
494 /* pci express 2 Rootpoint Mode */
495 mfsdr(SDR0_PE2DLPSET, reg);
496 reg |= 0x00400000;
497 mtsdr(SDR0_PE2DLPSET, reg);
498
499#if defined(CONFIG_STRESS)
500 /*
501 * All this setting done by linux only needed by stress an charac. test
502 * procedure
503 * PCIe 1 Rootpoint PCIe2 Endpoint
504 * PCIe 0 FIR Pre-emphasis Filter Coefficients & Transmit Driver Power Level
505 */
506 for (i=0,disp=0; i<8; i++,disp+=3) {
507 mfsdr(SDR0_PE0HSSSET1L0+disp, reg);
508 reg |= 0x33000000;
509 mtsdr(SDR0_PE0HSSSET1L0+disp, reg);
510 }
511
512 /*PCIe 1 FIR Pre-emphasis Filter Coefficients & Transmit Driver Power Level */
513 for (i=0,disp=0; i<4; i++,disp+=3) {
514 mfsdr(SDR0_PE1HSSSET1L0+disp, reg);
515 reg |= 0x33000000;
516 mtsdr(SDR0_PE1HSSSET1L0+disp, reg);
517 }
518
519 /*PCIE 2 FIR Pre-emphasis Filter Coefficients & Transmit Driver Power Level */
520 for (i=0,disp=0; i<4; i++,disp+=3) {
521 mfsdr(SDR0_PE2HSSSET1L0+disp, reg);
522 reg |= 0x33000000;
523 mtsdr(SDR0_PE2HSSSET1L0+disp, reg);
524 }
525
526 reg = 0x21242222;
527 mtsdr(SDR0_PE2UTLSET1, reg);
528 reg = 0x11000000;
529 mtsdr(SDR0_PE2UTLSET2, reg);
530 /* pci express 1 Endpoint Mode */
531 reg = 0x00004000;
532 mtsdr(SDR0_PE2DLPSET, reg);
533
534 mtsdr(SDR0_UART1, 0x2080005a); /* patch for TG */
535#endif
536
537 return 0;
538}
539
540#ifdef CONFIG_POST
541/*
542 * Returns 1 if keys pressed to start the power-on long-running tests
543 * Called from board_init_f().
544 */
545int post_hotkeys_pressed(void)
546{
547 return (ctrlc());
548}
549#endif
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SR		 550
551#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
552void ft_board_setup(void *blob, bd_t *bd)
553{
554 u32 val[4];
555 int rc;
556
557 ft_cpu_setup(blob, bd);
558
559 /* Fixup NOR mapping */
560 val[0] = 0; /* chip select number */
561 val[1] = 0; /* always 0 */
562 val[2] = gd->bd->bi_flashstart;
563 val[3] = gd->bd->bi_flashsize;
564 rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
565 val, sizeof(val), 1);
566 if (rc)
567 printf("Unable to update property NOR mapping, err=%s\n",
568 fdt_strerror(rc));
569}
570#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
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