[u-boot.git] / include / configs / cmc_pu2.h

/*
 * 2004-2005 Gary Jennejohn <[email protected]>
 *
 * Configuration settings for the CMC PU2 board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * If we are developing, we might want to start armboot from ram
 * so we MUST NOT initialize critical regs like mem-timing ...
 */
#define CONFIG_INIT_CRITICAL

/* ARM asynchronous clock */
#define AT91C_MAIN_CLOCK	207360000	/* from 18.432 MHz crystal (18432000 / 4 * 45) */
#define AT91C_MASTER_CLOCK	69120000	/* peripheral clock (AT91C_MASTER_CLOCK / 3) */

#define AT91_SLOW_CLOCK		32768	/* slow clock */

#define CONFIG_AT91RM9200DK	1	/* on an AT91RM9200DK Board	 */
#define CONFIG_CMC_PU2		1	/* on an CMC_PU2 Board	 */
#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG	1

#ifdef CONFIG_INIT_CRITICAL
#define CFG_USE_MAIN_OSCILLATOR		1
/* flash */
#define MC_PUIA_VAL	0x00000000
#define MC_PUP_VAL	0x00000000
#define MC_PUER_VAL	0x00000000
#define MC_ASR_VAL	0x00000000
#define MC_AASR_VAL	0x00000000
#define EBI_CFGR_VAL	0x00000000
#define SMC2_CSR_VAL	0x100032ad /* 16bit, 2 TDF, 4 WS */

/* clocks */
#define PLLAR_VAL	0x202CBE04 /* 207.360 MHz for PCK */
#define PLLBR_VAL	0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
#define MCKR_VAL	0x00000202 /* PCK/3 = MCK Master Clock = 69.120MHz from PLLA */

/* sdram */
#define PIOC_ASR_VAL	0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
#define PIOC_BSR_VAL	0x00000000
#define PIOC_PDR_VAL	0xFFFF0000
#define EBI_CSA_VAL	0x00000002 /* CS1=SDRAM */
#define SDRC_CR_VAL	0x3399c1d4 /* set up the SDRAM */
#define SDRAM		0x20000000 /* address of the SDRAM */
#define SDRAM1		0x20000080 /* address of the SDRAM */
#define SDRAM_VAL	0x00000000 /* value written to SDRAM */
#define SDRC_MR_VAL	0x00000002 /* Precharge All */
#define SDRC_MR_VAL1	0x00000004 /* refresh */
#define SDRC_MR_VAL2	0x00000003 /* Load Mode Register */
#define SDRC_MR_VAL3	0x00000000 /* Normal Mode */
#define SDRC_TR_VAL	0x000002E0 /* Write refresh rate */
#endif	/* CONFIG_INIT_CRITICAL */

/*
 * Size of malloc() pool
 */
#define CFG_MALLOC_LEN	(CFG_ENV_SIZE + 128*1024)
#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */

#define CONFIG_BAUDRATE		9600

#define CFG_AT91C_BRGR_DIVISOR	450	/* hardcode so no __divsi3 : AT91C_MASTER_CLOCK /(baudrate * 16) */

/*
 * Hardware drivers
 */

/* define one of these to choose the DBGU, USART0  or USART1 as console */
#undef CONFIG_DBGU
#define CONFIG_USART0
#undef CONFIG_USART1

#undef	CONFIG_HWFLOW			/* don't include RTS/CTS flow control support	*/

#undef	CONFIG_MODEM_SUPPORT		/* disable modem initialization stuff */

#define CONFIG_HARD_I2C

#ifdef CONFIG_HARD_I2C
#define CFG_I2C_SPEED		0	/* not used */
#define CFG_I2C_SLAVE		0	/* not used */
#define CONFIG_RTC_RS5C372A		/* RICOH I2C RTC */
#define CFG_I2C_RTC_ADDR	0x32
#define CFG_I2C_EEPROM_ADDR	0x50
#define CFG_I2C_EEPROM_ADDR_LEN 1
#define CFG_I2C_EEPROM_ADDR_OVERFLOW
#endif
/* still about 20 kB free with this defined */
#define CFG_LONGHELP

#define CONFIG_BOOTDELAY      3

#ifdef CONFIG_HARD_I2C
#define CONFIG_COMMANDS		\
		       ((CONFIG_CMD_DFL	| \
			CFG_CMD_DATE	| \
			CFG_CMD_DHCP 	| \
			CFG_CMD_EEPROM	| \
			CFG_CMD_I2C	| \
			CFG_CMD_NFS	| \
			CFG_CMD_SNTP  ) & \
		      ~(CFG_CMD_FPGA | CFG_CMD_MISC) )
#else
#define CONFIG_COMMANDS		\
		       ((CONFIG_CMD_DFL	| \
			CFG_CMD_DHCP 	| \
			CFG_CMD_NFS	| \
			CFG_CMD_SNTP  ) & \
		      ~(CFG_CMD_FPGA | CFG_CMD_MISC) )
#define CONFIG_TIMESTAMP
#endif
#define CFG_LONGHELP

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

#define AT91_SMART_MEDIA_ALE	(1 << 22)	/* our ALE is AD22 */
#define AT91_SMART_MEDIA_CLE	(1 << 21)	/* our CLE is AD21 */

#define CONFIG_NR_DRAM_BANKS	1
#define PHYS_SDRAM		0x20000000
#define PHYS_SDRAM_SIZE		0x1000000 	/* 16 megs */

#define CFG_MEMTEST_START		PHYS_SDRAM
#define CFG_MEMTEST_END			CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144

#define CONFIG_DRIVER_ETHER
#define CONFIG_NET_RETRY_COUNT		20
#define CONFIG_AT91C_USE_RMII

#define CONFIG_HAS_DATAFLASH		1
#define CFG_SPI_WRITE_TOUT		(5*CFG_HZ)
#define CFG_MAX_DATAFLASH_BANKS		2
#define CFG_MAX_DATAFLASH_PAGES		16384
#define CFG_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* Logical adress for CS0 */
#define CFG_DATAFLASH_LOGIC_ADDR_CS3	0xD0000000	/* Logical adress for CS3 */

#define PHYS_FLASH_1			0x10000000
#define PHYS_FLASH_SIZE			0x800000  /* 8 megs main flash */
#define CFG_FLASH_BASE			PHYS_FLASH_1
#define CFG_MONITOR_BASE		CFG_FLASH_BASE
#define CFG_MAX_FLASH_BANKS		1
#define CFG_MAX_FLASH_SECT		256
#define CFG_FLASH_ERASE_TOUT		(11 * CFG_HZ)	/* Timeout for Flash Erase */
#define CFG_FLASH_WRITE_TOUT		( 2 * CFG_HZ)	/* Timeout for Flash Write */

#define CFG_ENV_IS_IN_FLASH		1
#define CFG_ENV_OFFSET			0x20000		/* after u-boot.bin */
#define CFG_ENV_SECT_SIZE		(64 << 10)	/* sectors are 64 kB */
#define CFG_ENV_SIZE			(16 << 10)	/* Use only 16 kB */

#define CFG_LOAD_ADDR		0x21000000  /* default load address */

#define CFG_BAUDRATE_TABLE	{ 115200, 57600, 38400, 19200, 9600 }

#define CFG_PROMPT		"=> "		/* Monitor Command Prompt */
#define CFG_CBSIZE		256		/* Console I/O Buffer Size */
#define CFG_MAXARGS		32		/* max number of command args */
#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */

#ifndef __ASSEMBLY__
/*-----------------------------------------------------------------------
 * Board specific extension for bd_info
 *
 * This structure is embedded in the global bd_info (bd_t) structure
 * and can be used by the board specific code (eg board/...)
 */

struct bd_info_ext {
	/* helper variable for board environment handling
	 *
	 * env_crc_valid == 0	 =>   uninitialised
	 * env_crc_valid  > 0	 =>   environment crc in flash is valid
	 * env_crc_valid  < 0	 =>   environment crc in flash is invalid
	 */
	int env_crc_valid;
};
#endif	/* __ASSEMBLY__ */

#define CFG_HZ 1000
#define CFG_HZ_CLOCK AT91C_MASTER_CLOCK/2	/* AT91C_TC0_CMR is implicitly set to */
						/* AT91C_TC_TIMER_DIV1_CLOCK */

#define CONFIG_STACKSIZE	(32*1024)	/* regular stack */

#ifdef CONFIG_USE_IRQ
#error CONFIG_USE_IRQ not supported
#endif

#endif	/* __CONFIG_H */
Commit	Line	Data
2cbe571a	1	/*
414eec35	2	* 2004-2005 Gary Jennejohn <[email protected]>
2cbe571a	3	*
9d5028c2	4	* Configuration settings for the CMC PU2 board.
2cbe571a WD	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
45ea3fca	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2cbe571a WD	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	#ifndef __CONFIG_H
	26	#define __CONFIG_H
	27
	28	/*
	29	* If we are developing, we might want to start armboot from ram
	30	* so we MUST NOT initialize critical regs like mem-timing ...
	31	*/
400558b5	32	#define CONFIG_INIT_CRITICAL
2cbe571a WD	33
2cbe571a WD	34	/* ARM asynchronous clock */
ed54e621 WD	35	#define AT91C_MAIN_CLOCK 207360000 /* from 18.432 MHz crystal (18432000 / 4 * 45) */
ed54e621 WD	36	#define AT91C_MASTER_CLOCK 69120000 /* peripheral clock (AT91C_MASTER_CLOCK / 3) */
2cbe571a WD	37
	38	#define AT91_SLOW_CLOCK 32768 /* slow clock */
	39
	40	#define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */
45ea3fca	41	#define CONFIG_CMC_PU2 1 /* on an CMC_PU2 Board */
2cbe571a WD	42	#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
	43	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	44	#define CONFIG_SETUP_MEMORY_TAGS 1
	45	#define CONFIG_INITRD_TAG 1
	46
400558b5	47	#ifdef CONFIG_INIT_CRITICAL
ef2807c6 WD	48	#define CFG_USE_MAIN_OSCILLATOR 1
	49	/* flash */
	50	#define MC_PUIA_VAL 0x00000000
	51	#define MC_PUP_VAL 0x00000000
	52	#define MC_PUER_VAL 0x00000000
	53	#define MC_ASR_VAL 0x00000000
	54	#define MC_AASR_VAL 0x00000000
	55	#define EBI_CFGR_VAL 0x00000000
	56	#define SMC2_CSR_VAL 0x100032ad /* 16bit, 2 TDF, 4 WS */
	57
	58	/* clocks */
	59	#define PLLAR_VAL 0x202CBE04 /* 207.360 MHz for PCK */
	60	#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
	61	#define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 69.120MHz from PLLA */
	62
	63	/* sdram */
	64	#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
	65	#define PIOC_BSR_VAL 0x00000000
	66	#define PIOC_PDR_VAL 0xFFFF0000
	67	#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
	68	#define SDRC_CR_VAL 0x3399c1d4 /* set up the SDRAM */
	69	#define SDRAM 0x20000000 /* address of the SDRAM */
	70	#define SDRAM1 0x20000080 /* address of the SDRAM */
	71	#define SDRAM_VAL 0x00000000 /* value written to SDRAM */
	72	#define SDRC_MR_VAL 0x00000002 /* Precharge All */
	73	#define SDRC_MR_VAL1 0x00000004 /* refresh */
	74	#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
	75	#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */
	76	#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
400558b5	77	#endif /* CONFIG_INIT_CRITICAL */
ef2807c6	78
2cbe571a WD	79	/*
	80	* Size of malloc() pool
	81	*/
	82	#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
	83	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	84
45ea3fca	85	#define CONFIG_BAUDRATE 9600
2cbe571a	86
ed54e621	87	#define CFG_AT91C_BRGR_DIVISOR 450 /* hardcode so no __divsi3 : AT91C_MASTER_CLOCK /(baudrate * 16) */
2cbe571a WD	88
	89	/*
	90	* Hardware drivers
	91	*/
	92
	93	/* define one of these to choose the DBGU, USART0 or USART1 as console */
	94	#undef CONFIG_DBGU
9d5028c2 WD	95	#define CONFIG_USART0
9d5028c2 WD	96	#undef CONFIG_USART1
2cbe571a WD	97
	98	#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */
	99
	100	#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */
	101
9d5028c2	102	#define CONFIG_HARD_I2C
2cbe571a WD	103
2cbe571a WD	104	#ifdef CONFIG_HARD_I2C
45ea3fca WD	105	#define CFG_I2C_SPEED 0 /* not used */
	106	#define CFG_I2C_SLAVE 0 /* not used */
	107	#define CONFIG_RTC_RS5C372A /* RICOH I2C RTC */
	108	#define CFG_I2C_RTC_ADDR 0x32
	109	#define CFG_I2C_EEPROM_ADDR 0x50
2cbe571a WD	110	#define CFG_I2C_EEPROM_ADDR_LEN 1
	111	#define CFG_I2C_EEPROM_ADDR_OVERFLOW
	112	#endif
ed54e621 WD	113	/* still about 20 kB free with this defined */
ed54e621 WD	114	#define CFG_LONGHELP
2cbe571a WD	115
2cbe571a WD	116	#define CONFIG_BOOTDELAY 3
2cbe571a WD	117
	118	#ifdef CONFIG_HARD_I2C
	119	#define CONFIG_COMMANDS \
45ea3fca	120	((CONFIG_CMD_DFL \| \
45ea3fca	121	CFG_CMD_DATE \| \
414eec35	122	CFG_CMD_DHCP \| \
45ea3fca	123	CFG_CMD_EEPROM \| \
414eec35 WD	124	CFG_CMD_I2C \| \
	125	CFG_CMD_NFS \| \
	126	CFG_CMD_SNTP ) & \
45ea3fca	127	~(CFG_CMD_FPGA \| CFG_CMD_MISC) )
2cbe571a WD	128	#else
2cbe571a WD	129	#define CONFIG_COMMANDS \
45ea3fca	130	((CONFIG_CMD_DFL \| \
414eec35 WD	131	CFG_CMD_DHCP \| \
	132	CFG_CMD_NFS \| \
	133	CFG_CMD_SNTP ) & \
45ea3fca WD	134	~(CFG_CMD_FPGA \| CFG_CMD_MISC) )
45ea3fca WD	135	#define CONFIG_TIMESTAMP
2cbe571a	136	#endif
ed54e621	137	#define CFG_LONGHELP
2cbe571a WD	138
	139	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
	140	#include <cmd_confdefs.h>
	141
45ea3fca WD	142	#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */
45ea3fca WD	143	#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */
2cbe571a	144
45ea3fca WD	145	#define CONFIG_NR_DRAM_BANKS 1
	146	#define PHYS_SDRAM 0x20000000
	147	#define PHYS_SDRAM_SIZE 0x1000000 /* 16 megs */
2cbe571a WD	148
	149	#define CFG_MEMTEST_START PHYS_SDRAM
	150	#define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
	151
	152	#define CONFIG_DRIVER_ETHER
	153	#define CONFIG_NET_RETRY_COUNT 20
	154	#define CONFIG_AT91C_USE_RMII
	155
	156	#define CONFIG_HAS_DATAFLASH 1
	157	#define CFG_SPI_WRITE_TOUT (5*CFG_HZ)
45ea3fca WD	158	#define CFG_MAX_DATAFLASH_BANKS 2
45ea3fca WD	159	#define CFG_MAX_DATAFLASH_PAGES 16384
2cbe571a WD	160	#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */
	161	#define CFG_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */
	162
	163	#define PHYS_FLASH_1 0x10000000
9d5028c2	164	#define PHYS_FLASH_SIZE 0x800000 /* 8 megs main flash */
2cbe571a	165	#define CFG_FLASH_BASE PHYS_FLASH_1
45ea3fca	166	#define CFG_MONITOR_BASE CFG_FLASH_BASE
2cbe571a WD	167	#define CFG_MAX_FLASH_BANKS 1
2cbe571a WD	168	#define CFG_MAX_FLASH_SECT 256
e6ba3c92 WD	169	#define CFG_FLASH_ERASE_TOUT (11 * CFG_HZ) /* Timeout for Flash Erase */
e6ba3c92 WD	170	#define CFG_FLASH_WRITE_TOUT ( 2 * CFG_HZ) /* Timeout for Flash Write */
2cbe571a	171
2cbe571a	172	#define CFG_ENV_IS_IN_FLASH 1
45ea3fca WD	173	#define CFG_ENV_OFFSET 0x20000 /* after u-boot.bin */
	174	#define CFG_ENV_SECT_SIZE (64 << 10) /* sectors are 64 kB */
	175	#define CFG_ENV_SIZE (16 << 10) /* Use only 16 kB */
2cbe571a WD	176
	177	#define CFG_LOAD_ADDR 0x21000000 /* default load address */
	178
45ea3fca	179	#define CFG_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 }
2cbe571a	180
45ea3fca	181	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
2cbe571a	182	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
45ea3fca	183	#define CFG_MAXARGS 32 /* max number of command args */
2cbe571a WD	184	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	185
	186	#ifndef __ASSEMBLY__
	187	/*-----------------------------------------------------------------------
	188	* Board specific extension for bd_info
	189	*
	190	* This structure is embedded in the global bd_info (bd_t) structure
	191	* and can be used by the board specific code (eg board/...)
	192	*/
	193
	194	struct bd_info_ext {
	195	/* helper variable for board environment handling
	196	*
45ea3fca WD	197	* env_crc_valid == 0 => uninitialised
	198	* env_crc_valid > 0 => environment crc in flash is valid
	199	* env_crc_valid < 0 => environment crc in flash is invalid
2cbe571a WD	200	*/
	201	int env_crc_valid;
	202	};
45ea3fca	203	#endif /* __ASSEMBLY__ */
2cbe571a	204
9455b7f3 WD	205	#define CFG_HZ 1000
9455b7f3 WD	206	#define CFG_HZ_CLOCK AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */
59acc296	207	/* AT91C_TC_TIMER_DIV1_CLOCK */
2cbe571a WD	208
	209	#define CONFIG_STACKSIZE (321024) / regular stack */
	210
	211	#ifdef CONFIG_USE_IRQ
	212	#error CONFIG_USE_IRQ not supported
	213	#endif
	214
45ea3fca	215	#endif /* __CONFIG_H */