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83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
3b7f0e10 VB |
2 | /* |
3 | * include/configs/silk.h | |
4 | * This file is silk board configuration. | |
5 | * | |
6 | * Copyright (C) 2015 Renesas Electronics Corporation | |
7 | * Copyright (C) 2015 Cogent Embedded, Inc. | |
3b7f0e10 VB |
8 | */ |
9 | ||
10 | #ifndef __SILK_H | |
11 | #define __SILK_H | |
12 | ||
3b7f0e10 VB |
13 | #include "rcar-gen2-common.h" |
14 | ||
f7aa3cd4 | 15 | #define STACK_AREA_SIZE 0x00100000 |
3b7f0e10 | 16 | #define LOW_LEVEL_MERAM_STACK \ |
eaf6ea6a | 17 | (SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) |
3b7f0e10 VB |
18 | |
19 | /* MEMORY */ | |
20 | #define RCAR_GEN2_SDRAM_BASE 0x40000000 | |
21 | #define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024) | |
22 | #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) | |
23 | ||
3b7f0e10 | 24 | /* FLASH */ |
3b7f0e10 | 25 | #define CONFIG_SPI_FLASH_QUAD |
3b7f0e10 VB |
26 | |
27 | /* SH Ether */ | |
3b7f0e10 VB |
28 | #define CONFIG_SH_ETHER_USE_PORT 0 |
29 | #define CONFIG_SH_ETHER_PHY_ADDR 0x1 | |
30 | #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII | |
31 | #define CONFIG_SH_ETHER_CACHE_WRITEBACK | |
32 | #define CONFIG_SH_ETHER_CACHE_INVALIDATE | |
33 | #define CONFIG_SH_ETHER_ALIGNE_SIZE 64 | |
3b7f0e10 VB |
34 | |
35 | /* Board Clock */ | |
f7aa3cd4 MV |
36 | |
37 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
07a8060a | 38 | "bootm_size=0x10000000\0" |
f7aa3cd4 MV |
39 | |
40 | /* SPL support */ | |
3b7f0e10 VB |
41 | |
42 | #endif /* __SILK_H */ |