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mmc: mv_sdhci: add driver model support
[u-boot.git] / drivers / qe / uec_phy.c
CommitLineData
83d290c5 1// SPDX-License-Identifier: GPL-2.0+
7737d5c6 2/*
2b21ec92 3 * Copyright (C) 2005,2010-2011 Freescale Semiconductor, Inc.
7737d5c6
DL		 4 *
5 * Author: Shlomi Gridish
6 *
7 * Description: UCC GETH Driver -- PHY handling
dd520bf3
WD		 8 * Driver for UEC on QE
9 * Based on 8260_io/fcc_enet.c
7737d5c6
DL		 10 */
11
b5bf5cb3
MY		 12#include <common.h>
13#include <net.h>
14#include <malloc.h>
1221ce45 15#include <linux/errno.h>
b5bf5cb3
MY		 16#include <linux/immap_qe.h>
17#include <asm/io.h>
7737d5c6
DL		 18#include "uccf.h"
19#include "uec.h"
20#include "uec_phy.h"
21#include "miiphy.h"
2459afb1 22#include <fsl_qe.h>
865ff856 23#include <phy.h>
7737d5c6 24
7737d5c6 25#define ugphy_printk(format, arg...) \
dd520bf3 26 printf(format "\n", ## arg)
7737d5c6 27
dd520bf3
WD		 28#define ugphy_dbg(format, arg...) \
29 ugphy_printk(format , ## arg)
30#define ugphy_err(format, arg...) \
31 ugphy_printk(format , ## arg)
32#define ugphy_info(format, arg...) \
33 ugphy_printk(format , ## arg)
34#define ugphy_warn(format, arg...) \
35 ugphy_printk(format , ## arg)
7737d5c6
DL		 36
37#ifdef UEC_VERBOSE_DEBUG
38#define ugphy_vdbg ugphy_dbg
39#else
40#define ugphy_vdbg(ugeth, fmt, args...) do { } while (0)
41#endif /* UEC_VERBOSE_DEBUG */
42
edf3fe7d
RR		 43/*--------------------------------------------------------------------+
44 * Fixed PHY (PHY-less) support for Ethernet Ports.
45 *
a47a12be 46 * Copied from arch/powerpc/cpu/ppc4xx/4xx_enet.c
edf3fe7d
RR		 47 *--------------------------------------------------------------------*/
48
49/*
1443cd7e
RR		 50 * Some boards do not have a PHY for each ethernet port. These ports are known
51 * as Fixed PHY (or PHY-less) ports. For such ports, set the appropriate
52 * CONFIG_SYS_UECx_PHY_ADDR equal to CONFIG_FIXED_PHY_ADDR (an unused address)
53 * When the drver tries to identify the PHYs, CONFIG_FIXED_PHY will be returned
54 * and the driver will search CONFIG_SYS_FIXED_PHY_PORTS to find what network
55 * speed and duplex should be for the port.
edf3fe7d 56 *
1443cd7e 57 * Example board header configuration file:
edf3fe7d 58 * #define CONFIG_FIXED_PHY 0xFFFFFFFF
1443cd7e 59 * #define CONFIG_SYS_FIXED_PHY_ADDR 0x1E (pick an unused phy address)
edf3fe7d 60 *
1443cd7e
RR		 61 * #define CONFIG_SYS_UEC1_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR
62 * #define CONFIG_SYS_UEC2_PHY_ADDR 0x02
63 * #define CONFIG_SYS_UEC3_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR
64 * #define CONFIG_SYS_UEC4_PHY_ADDR 0x04
edf3fe7d 65 *
1443cd7e
RR		 66 * #define CONFIG_SYS_FIXED_PHY_PORT(name,speed,duplex) \
67 * {name, speed, duplex},
edf3fe7d
RR		 68 *
69 * #define CONFIG_SYS_FIXED_PHY_PORTS \
78b7a8ef
KP		 70 * CONFIG_SYS_FIXED_PHY_PORT("UEC0",SPEED_100,DUPLEX_FULL) \
71 * CONFIG_SYS_FIXED_PHY_PORT("UEC2",SPEED_100,DUPLEX_HALF)
edf3fe7d
RR		 72 */
73
74#ifndef CONFIG_FIXED_PHY
75#define CONFIG_FIXED_PHY 0xFFFFFFFF /* Fixed PHY (PHY-less) */
76#endif
77
78#ifndef CONFIG_SYS_FIXED_PHY_PORTS
79#define CONFIG_SYS_FIXED_PHY_PORTS /* default is an empty array */
80#endif
81
82struct fixed_phy_port {
f6add132 83 char name[16]; /* ethernet port name */
edf3fe7d
RR		 84 unsigned int speed; /* specified speed 10,100 or 1000 */
85 unsigned int duplex; /* specified duplex FULL or HALF */
86};
87
88static const struct fixed_phy_port fixed_phy_port[] = {
89 CONFIG_SYS_FIXED_PHY_PORTS /* defined in board configuration file */
90};
91
23c34af4
RR		 92/*--------------------------------------------------------------------+
93 * BitBang MII support for ethernet ports
94 *
95 * Based from MPC8560ADS implementation
96 *--------------------------------------------------------------------*/
97/*
98 * Example board header file to define bitbang ethernet ports:
99 *
100 * #define CONFIG_SYS_BITBANG_PHY_PORT(name) name,
78b7a8ef 101 * #define CONFIG_SYS_BITBANG_PHY_PORTS CONFIG_SYS_BITBANG_PHY_PORT("UEC0")
23c34af4
RR		 102*/
103#ifndef CONFIG_SYS_BITBANG_PHY_PORTS
104#define CONFIG_SYS_BITBANG_PHY_PORTS /* default is an empty array */
105#endif
106
107#if defined(CONFIG_BITBANGMII)
108static const char *bitbang_phy_port[] = {
109 CONFIG_SYS_BITBANG_PHY_PORTS /* defined in board configuration file */
110};
111#endif /* CONFIG_BITBANGMII */
112
dd520bf3
WD		 113static void config_genmii_advert (struct uec_mii_info *mii_info);
114static void genmii_setup_forced (struct uec_mii_info *mii_info);
115static void genmii_restart_aneg (struct uec_mii_info *mii_info);
116static int gbit_config_aneg (struct uec_mii_info *mii_info);
117static int genmii_config_aneg (struct uec_mii_info *mii_info);
118static int genmii_update_link (struct uec_mii_info *mii_info);
119static int genmii_read_status (struct uec_mii_info *mii_info);
09c04c20
AF		 120u16 uec_phy_read(struct uec_mii_info *mii_info, u16 regnum);
121void uec_phy_write(struct uec_mii_info *mii_info, u16 regnum, u16 val);
7737d5c6
DL		 122
123/* Write value to the PHY for this device to the register at regnum, */
124/* waiting until the write is done before it returns. All PHY */
125/* configuration has to be done through the TSEC1 MIIM regs */
da9d4610 126void uec_write_phy_reg (struct eth_device *dev, int mii_id, int regnum, int value)
7737d5c6 127{
dd520bf3 128 uec_private_t *ugeth = (uec_private_t *) dev->priv;
da9d4610 129 uec_mii_t *ug_regs;
dd520bf3
WD		 130 enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum;
131 u32 tmp_reg;
7737d5c6 132
23c34af4
RR		 133
134#if defined(CONFIG_BITBANGMII)
135 u32 i = 0;
136
137 for (i = 0; i < ARRAY_SIZE(bitbang_phy_port); i++) {
138 if (strncmp(dev->name, bitbang_phy_port[i],
139 sizeof(dev->name)) == 0) {
140 (void)bb_miiphy_write(NULL, mii_id, regnum, value);
141 return;
142 }
143 }
144#endif /* CONFIG_BITBANGMII */
145
da9d4610 146 ug_regs = ugeth->uec_mii_regs;
7737d5c6 147
dd520bf3
WD		 148 /* Stop the MII management read cycle */
149 out_be32 (&ug_regs->miimcom, 0);
150 /* Setting up the MII Mangement Address Register */
151 tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
152 out_be32 (&ug_regs->miimadd, tmp_reg);
7737d5c6 153
dd520bf3
WD		 154 /* Setting up the MII Mangement Control Register with the value */
155 out_be32 (&ug_regs->miimcon, (u32) value);
ee62ed32 156 sync();
7737d5c6 157
dd520bf3
WD		 158 /* Wait till MII management write is complete */
159 while ((in_be32 (&ug_regs->miimind)) & MIIMIND_BUSY);
7737d5c6
DL		 160}
161
162/* Reads from register regnum in the PHY for device dev, */
163/* returning the value. Clears miimcom first. All PHY */
164/* configuration has to be done through the TSEC1 MIIM regs */
da9d4610 165int uec_read_phy_reg (struct eth_device *dev, int mii_id, int regnum)
7737d5c6 166{
dd520bf3 167 uec_private_t *ugeth = (uec_private_t *) dev->priv;
da9d4610 168 uec_mii_t *ug_regs;
dd520bf3
WD		 169 enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum;
170 u32 tmp_reg;
171 u16 value;
7737d5c6 172
23c34af4
RR		 173
174#if defined(CONFIG_BITBANGMII)
175 u32 i = 0;
176
177 for (i = 0; i < ARRAY_SIZE(bitbang_phy_port); i++) {
178 if (strncmp(dev->name, bitbang_phy_port[i],
179 sizeof(dev->name)) == 0) {
180 (void)bb_miiphy_read(NULL, mii_id, regnum, &value);
181 return (value);
182 }
183 }
184#endif /* CONFIG_BITBANGMII */
185
da9d4610 186 ug_regs = ugeth->uec_mii_regs;
7737d5c6 187
dd520bf3
WD		 188 /* Setting up the MII Mangement Address Register */
189 tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
190 out_be32 (&ug_regs->miimadd, tmp_reg);
7737d5c6 191
ee62ed32 192 /* clear MII management command cycle */
dd520bf3 193 out_be32 (&ug_regs->miimcom, 0);
ee62ed32
KP		 194 sync();
195
196 /* Perform an MII management read cycle */
dd520bf3 197 out_be32 (&ug_regs->miimcom, MIIMCOM_READ_CYCLE);
7737d5c6 198
dd520bf3
WD		 199 /* Wait till MII management write is complete */
200 while ((in_be32 (&ug_regs->miimind)) &
201 (MIIMIND_NOT_VALID | MIIMIND_BUSY));
7737d5c6 202
dd520bf3
WD		 203 /* Read MII management status */
204 value = (u16) in_be32 (&ug_regs->miimstat);
205 if (value == 0xffff)
84a3047b 206 ugphy_vdbg
dd520bf3
WD		 207 ("read wrong value : mii_id %d,mii_reg %d, base %08x",
208 mii_id, mii_reg, (u32) & (ug_regs->miimcfg));
7737d5c6 209
dd520bf3 210 return (value);
7737d5c6
DL		 211}
212
dd520bf3 213void mii_clear_phy_interrupt (struct uec_mii_info *mii_info)
7737d5c6 214{
dd520bf3
WD		 215 if (mii_info->phyinfo->ack_interrupt)
216 mii_info->phyinfo->ack_interrupt (mii_info);
7737d5c6
DL		 217}
218
dd520bf3
WD		 219void mii_configure_phy_interrupt (struct uec_mii_info *mii_info,
220 u32 interrupts)
7737d5c6 221{
dd520bf3
WD		 222 mii_info->interrupts = interrupts;
223 if (mii_info->phyinfo->config_intr)
224 mii_info->phyinfo->config_intr (mii_info);
7737d5c6
DL		 225}
226
227/* Writes MII_ADVERTISE with the appropriate values, after
228 * sanitizing advertise to make sure only supported features
229 * are advertised
230 */
dd520bf3 231static void config_genmii_advert (struct uec_mii_info *mii_info)
7737d5c6 232{
dd520bf3
WD		 233 u32 advertise;
234 u16 adv;
235
236 /* Only allow advertising what this PHY supports */
237 mii_info->advertising &= mii_info->phyinfo->features;
238 advertise = mii_info->advertising;
239
240 /* Setup standard advertisement */
09c04c20 241 adv = uec_phy_read(mii_info, MII_ADVERTISE);
dd520bf3
WD		 242 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
243 if (advertise & ADVERTISED_10baseT_Half)
244 adv |= ADVERTISE_10HALF;
245 if (advertise & ADVERTISED_10baseT_Full)
246 adv |= ADVERTISE_10FULL;
247 if (advertise & ADVERTISED_100baseT_Half)
248 adv |= ADVERTISE_100HALF;
249 if (advertise & ADVERTISED_100baseT_Full)
250 adv |= ADVERTISE_100FULL;
09c04c20 251 uec_phy_write(mii_info, MII_ADVERTISE, adv);
7737d5c6
DL		 252}
253
dd520bf3 254static void genmii_setup_forced (struct uec_mii_info *mii_info)
7737d5c6 255{
dd520bf3
WD		 256 u16 ctrl;
257 u32 features = mii_info->phyinfo->features;
258
09c04c20 259 ctrl = uec_phy_read(mii_info, MII_BMCR);
dd520bf3 260
8ef583a0
MF		 261 ctrl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 |
262 BMCR_SPEED1000 | BMCR_ANENABLE);
263 ctrl |= BMCR_RESET;
dd520bf3
WD		 264
265 switch (mii_info->speed) {
266 case SPEED_1000:
267 if (features & (SUPPORTED_1000baseT_Half
268 | SUPPORTED_1000baseT_Full)) {
8ef583a0 269 ctrl |= BMCR_SPEED1000;
dd520bf3
WD		 270 break;
271 }
272 mii_info->speed = SPEED_100;
273 case SPEED_100:
274 if (features & (SUPPORTED_100baseT_Half
275 | SUPPORTED_100baseT_Full)) {
8ef583a0 276 ctrl |= BMCR_SPEED100;
dd520bf3
WD		 277 break;
278 }
279 mii_info->speed = SPEED_10;
280 case SPEED_10:
281 if (features & (SUPPORTED_10baseT_Half
282 | SUPPORTED_10baseT_Full))
283 break;
284 default: /* Unsupported speed! */
285 ugphy_err ("%s: Bad speed!", mii_info->dev->name);
286 break;
287 }
288
09c04c20 289 uec_phy_write(mii_info, MII_BMCR, ctrl);
7737d5c6
DL		 290}
291
292/* Enable and Restart Autonegotiation */
dd520bf3 293static void genmii_restart_aneg (struct uec_mii_info *mii_info)
7737d5c6 294{
dd520bf3 295 u16 ctl;
7737d5c6 296
09c04c20 297 ctl = uec_phy_read(mii_info, MII_BMCR);
8ef583a0 298 ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
09c04c20 299 uec_phy_write(mii_info, MII_BMCR, ctl);
7737d5c6
DL		 300}
301
dd520bf3 302static int gbit_config_aneg (struct uec_mii_info *mii_info)
7737d5c6 303{
dd520bf3
WD		 304 u16 adv;
305 u32 advertise;
306
307 if (mii_info->autoneg) {
308 /* Configure the ADVERTISE register */
309 config_genmii_advert (mii_info);
310 advertise = mii_info->advertising;
311
09c04c20 312 adv = uec_phy_read(mii_info, MII_CTRL1000);
2b21ec92
KG		 313 adv &= ~(ADVERTISE_1000FULL |
314 ADVERTISE_1000HALF);
dd520bf3 315 if (advertise & SUPPORTED_1000baseT_Half)
2b21ec92 316 adv |= ADVERTISE_1000HALF;
dd520bf3 317 if (advertise & SUPPORTED_1000baseT_Full)
2b21ec92 318 adv |= ADVERTISE_1000FULL;
09c04c20 319 uec_phy_write(mii_info, MII_CTRL1000, adv);
dd520bf3
WD		 320
321 /* Start/Restart aneg */
322 genmii_restart_aneg (mii_info);
323 } else
324 genmii_setup_forced (mii_info);
325
326 return 0;
7737d5c6
DL		 327}
328
dd520bf3 329static int marvell_config_aneg (struct uec_mii_info *mii_info)
7737d5c6 330{
dd520bf3
WD		 331 /* The Marvell PHY has an errata which requires
332 * that certain registers get written in order
333 * to restart autonegotiation */
09c04c20 334 uec_phy_write(mii_info, MII_BMCR, BMCR_RESET);
7737d5c6 335
09c04c20
AF		 336 uec_phy_write(mii_info, 0x1d, 0x1f);
337 uec_phy_write(mii_info, 0x1e, 0x200c);
338 uec_phy_write(mii_info, 0x1d, 0x5);
339 uec_phy_write(mii_info, 0x1e, 0);
340 uec_phy_write(mii_info, 0x1e, 0x100);
7737d5c6 341
dd520bf3 342 gbit_config_aneg (mii_info);
7737d5c6 343
dd520bf3 344 return 0;
7737d5c6
DL		 345}
346
dd520bf3 347static int genmii_config_aneg (struct uec_mii_info *mii_info)
7737d5c6 348{
dd520bf3 349 if (mii_info->autoneg) {
f29c181c
JT		 350 /* Speed up the common case, if link is already up, speed and
351 duplex match, skip auto neg as it already matches */
352 if (!genmii_read_status(mii_info) && mii_info->link)
353 if (mii_info->duplex == DUPLEX_FULL &&
354 mii_info->speed == SPEED_100)
355 if (mii_info->advertising &
356 ADVERTISED_100baseT_Full)
357 return 0;
358
dd520bf3
WD		 359 config_genmii_advert (mii_info);
360 genmii_restart_aneg (mii_info);
361 } else
362 genmii_setup_forced (mii_info);
7737d5c6 363
dd520bf3 364 return 0;
7737d5c6
DL		 365}
366
dd520bf3 367static int genmii_update_link (struct uec_mii_info *mii_info)
7737d5c6 368{
dd520bf3 369 u16 status;
7737d5c6 370
ee62ed32 371 /* Status is read once to clear old link state */
09c04c20 372 uec_phy_read(mii_info, MII_BMSR);
7737d5c6 373
ee62ed32
KP		 374 /*
375 * Wait if the link is up, and autonegotiation is in progress
376 * (ie - we're capable and it's not done)
377 */
09c04c20 378 status = uec_phy_read(mii_info, MII_BMSR);
8ef583a0
MF		 379 if ((status & BMSR_LSTATUS) && (status & BMSR_ANEGCAPABLE)
380 && !(status & BMSR_ANEGCOMPLETE)) {
ee62ed32
KP		 381 int i = 0;
382
8ef583a0 383 while (!(status & BMSR_ANEGCOMPLETE)) {
ee62ed32
KP		 384 /*
385 * Timeout reached ?
386 */
387 if (i > UGETH_AN_TIMEOUT) {
388 mii_info->link = 0;
389 return 0;
390 }
391
f30b6154 392 i++;
ee62ed32 393 udelay(1000); /* 1 ms */
09c04c20 394 status = uec_phy_read(mii_info, MII_BMSR);
ee62ed32 395 }
dd520bf3 396 mii_info->link = 1;
ee62ed32 397 } else {
8ef583a0 398 if (status & BMSR_LSTATUS)
ee62ed32
KP		 399 mii_info->link = 1;
400 else
401 mii_info->link = 0;
402 }
7737d5c6 403
dd520bf3 404 return 0;
7737d5c6
DL		 405}
406
dd520bf3 407static int genmii_read_status (struct uec_mii_info *mii_info)
7737d5c6 408{
dd520bf3
WD		 409 u16 status;
410 int err;
411
412 /* Update the link, but return if there
413 * was an error */
414 err = genmii_update_link (mii_info);
415 if (err)
416 return err;
417
418 if (mii_info->autoneg) {
09c04c20 419 status = uec_phy_read(mii_info, MII_STAT1000);
91cdaa3a
AV		 420
421 if (status & (LPA_1000FULL | LPA_1000HALF)) {
422 mii_info->speed = SPEED_1000;
423 if (status & LPA_1000FULL)
424 mii_info->duplex = DUPLEX_FULL;
425 else
426 mii_info->duplex = DUPLEX_HALF;
427 } else {
09c04c20 428 status = uec_phy_read(mii_info, MII_LPA);
91cdaa3a 429
8ef583a0 430 if (status & (LPA_10FULL | LPA_100FULL))
91cdaa3a
AV		 431 mii_info->duplex = DUPLEX_FULL;
432 else
433 mii_info->duplex = DUPLEX_HALF;
8ef583a0 434 if (status & (LPA_100FULL | LPA_100HALF))
91cdaa3a
AV		 435 mii_info->speed = SPEED_100;
436 else
437 mii_info->speed = SPEED_10;
438 }
dd520bf3
WD		 439 mii_info->pause = 0;
440 }
441 /* On non-aneg, we assume what we put in BMCR is the speed,
442 * though magic-aneg shouldn't prevent this case from occurring
443 */
444
445 return 0;
7737d5c6
DL		 446}
447
300615dc
AV		 448static int bcm_init(struct uec_mii_info *mii_info)
449{
450 struct eth_device *edev = mii_info->dev;
451 uec_private_t *uec = edev->priv;
452
453 gbit_config_aneg(mii_info);
454
865ff856
AF		 455 if ((uec->uec_info->enet_interface_type ==
456 PHY_INTERFACE_MODE_RGMII_RXID) &&
457 (uec->uec_info->speed == SPEED_1000)) {
300615dc
AV		 458 u16 val;
459 int cnt = 50;
460
461 /* Wait for aneg to complete. */
462 do
09c04c20 463 val = uec_phy_read(mii_info, MII_BMSR);
8ef583a0 464 while (--cnt && !(val & BMSR_ANEGCOMPLETE));
300615dc
AV		 465
466 /* Set RDX clk delay. */
09c04c20 467 uec_phy_write(mii_info, 0x18, 0x7 | (7 << 12));
300615dc 468
09c04c20 469 val = uec_phy_read(mii_info, 0x18);
300615dc
AV		 470 /* Set RDX-RXC skew. */
471 val |= (1 << 8);
472 val |= (7 | (7 << 12));
473 /* Write bits 14:0. */
474 val |= (1 << 15);
09c04c20 475 uec_phy_write(mii_info, 0x18, val);
300615dc
AV		 476 }
477
478 return 0;
479}
480
09c04c20 481static int uec_marvell_init(struct uec_mii_info *mii_info)
41410eee
HW		 482{
483 struct eth_device *edev = mii_info->dev;
484 uec_private_t *uec = edev->priv;
865ff856 485 phy_interface_t iface = uec->uec_info->enet_interface_type;
582c55a0 486 int speed = uec->uec_info->speed;
41410eee 487
865ff856
AF		 488 if ((speed == SPEED_1000) &&
489 (iface == PHY_INTERFACE_MODE_RGMII_ID ||
490 iface == PHY_INTERFACE_MODE_RGMII_RXID ||
491 iface == PHY_INTERFACE_MODE_RGMII_TXID)) {
41410eee
HW		 492 int temp;
493
09c04c20 494 temp = uec_phy_read(mii_info, MII_M1111_PHY_EXT_CR);
865ff856 495 if (iface == PHY_INTERFACE_MODE_RGMII_ID) {
6185f80c 496 temp |= MII_M1111_RX_DELAY | MII_M1111_TX_DELAY;
865ff856 497 } else if (iface == PHY_INTERFACE_MODE_RGMII_RXID) {
6185f80c
AV		 498 temp &= ~MII_M1111_TX_DELAY;
499 temp |= MII_M1111_RX_DELAY;
865ff856 500 } else if (iface == PHY_INTERFACE_MODE_RGMII_TXID) {
6185f80c
AV		 501 temp &= ~MII_M1111_RX_DELAY;
502 temp |= MII_M1111_TX_DELAY;
503 }
09c04c20 504 uec_phy_write(mii_info, MII_M1111_PHY_EXT_CR, temp);
41410eee 505
09c04c20 506 temp = uec_phy_read(mii_info, MII_M1111_PHY_EXT_SR);
41410eee
HW		 507 temp &= ~MII_M1111_HWCFG_MODE_MASK;
508 temp |= MII_M1111_HWCFG_MODE_RGMII;
09c04c20 509 uec_phy_write(mii_info, MII_M1111_PHY_EXT_SR, temp);
41410eee 510
09c04c20 511 uec_phy_write(mii_info, MII_BMCR, BMCR_RESET);
41410eee
HW		 512 }
513
514 return 0;
515}
516
dd520bf3 517static int marvell_read_status (struct uec_mii_info *mii_info)
7737d5c6 518{
dd520bf3
WD		 519 u16 status;
520 int err;
521
522 /* Update the link, but return if there
523 * was an error */
524 err = genmii_update_link (mii_info);
525 if (err)
526 return err;
527
528 /* If the link is up, read the speed and duplex */
529 /* If we aren't autonegotiating, assume speeds
530 * are as set */
531 if (mii_info->autoneg && mii_info->link) {
532 int speed;
533
09c04c20 534 status = uec_phy_read(mii_info, MII_M1011_PHY_SPEC_STATUS);
dd520bf3
WD		 535
536 /* Get the duplexity */
537 if (status & MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX)
538 mii_info->duplex = DUPLEX_FULL;
539 else
540 mii_info->duplex = DUPLEX_HALF;
541
542 /* Get the speed */
543 speed = status & MII_M1011_PHY_SPEC_STATUS_SPD_MASK;
544 switch (speed) {
545 case MII_M1011_PHY_SPEC_STATUS_1000:
546 mii_info->speed = SPEED_1000;
547 break;
548 case MII_M1011_PHY_SPEC_STATUS_100:
549 mii_info->speed = SPEED_100;
550 break;
551 default:
552 mii_info->speed = SPEED_10;
553 break;
554 }
555 mii_info->pause = 0;
556 }
557
558 return 0;
7737d5c6
DL		 559}
560
dd520bf3 561static int marvell_ack_interrupt (struct uec_mii_info *mii_info)
7737d5c6 562{
dd520bf3 563 /* Clear the interrupts by reading the reg */
09c04c20 564 uec_phy_read(mii_info, MII_M1011_IEVENT);
7737d5c6 565
dd520bf3 566 return 0;
7737d5c6
DL		 567}
568
dd520bf3 569static int marvell_config_intr (struct uec_mii_info *mii_info)
7737d5c6 570{
dd520bf3 571 if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
09c04c20 572 uec_phy_write(mii_info, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
dd520bf3 573 else
09c04c20
AF		 574 uec_phy_write(mii_info, MII_M1011_IMASK,
575 MII_M1011_IMASK_CLEAR);
7737d5c6 576
dd520bf3 577 return 0;
7737d5c6
DL		 578}
579
dd520bf3 580static int dm9161_init (struct uec_mii_info *mii_info)
7737d5c6 581{
dd520bf3 582 /* Reset the PHY */
09c04c20 583 uec_phy_write(mii_info, MII_BMCR, uec_phy_read(mii_info, MII_BMCR) |
8ef583a0 584 BMCR_RESET);
dd520bf3 585 /* PHY and MAC connect */
09c04c20 586 uec_phy_write(mii_info, MII_BMCR, uec_phy_read(mii_info, MII_BMCR) &
8ef583a0 587 ~BMCR_ISOLATE);
ee62ed32 588
09c04c20 589 uec_phy_write(mii_info, MII_DM9161_SCR, MII_DM9161_SCR_INIT);
ee62ed32 590
dd520bf3
WD		 591 config_genmii_advert (mii_info);
592 /* Start/restart aneg */
593 genmii_config_aneg (mii_info);
7737d5c6 594
dd520bf3 595 return 0;
7737d5c6
DL		 596}
597
dd520bf3 598static int dm9161_config_aneg (struct uec_mii_info *mii_info)
7737d5c6 599{
dd520bf3 600 return 0;
7737d5c6
DL		 601}
602
dd520bf3 603static int dm9161_read_status (struct uec_mii_info *mii_info)
7737d5c6 604{
dd520bf3
WD		 605 u16 status;
606 int err;
607
608 /* Update the link, but return if there was an error */
609 err = genmii_update_link (mii_info);
610 if (err)
611 return err;
612 /* If the link is up, read the speed and duplex
613 If we aren't autonegotiating assume speeds are as set */
614 if (mii_info->autoneg && mii_info->link) {
09c04c20 615 status = uec_phy_read(mii_info, MII_DM9161_SCSR);
dd520bf3
WD		 616 if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_100H))
617 mii_info->speed = SPEED_100;
618 else
619 mii_info->speed = SPEED_10;
620
621 if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_10F))
622 mii_info->duplex = DUPLEX_FULL;
623 else
624 mii_info->duplex = DUPLEX_HALF;
625 }
626
627 return 0;
7737d5c6
DL		 628}
629
dd520bf3 630static int dm9161_ack_interrupt (struct uec_mii_info *mii_info)
7737d5c6 631{
dd520bf3 632 /* Clear the interrupt by reading the reg */
09c04c20 633 uec_phy_read(mii_info, MII_DM9161_INTR);
7737d5c6 634
dd520bf3 635 return 0;
7737d5c6
DL		 636}
637
dd520bf3 638static int dm9161_config_intr (struct uec_mii_info *mii_info)
7737d5c6 639{
dd520bf3 640 if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
09c04c20 641 uec_phy_write(mii_info, MII_DM9161_INTR, MII_DM9161_INTR_INIT);
dd520bf3 642 else
09c04c20 643 uec_phy_write(mii_info, MII_DM9161_INTR, MII_DM9161_INTR_STOP);
7737d5c6 644
dd520bf3 645 return 0;
7737d5c6
DL		 646}
647
dd520bf3 648static void dm9161_close (struct uec_mii_info *mii_info)
7737d5c6
DL		 649{
650}
651
edf3fe7d
RR		 652static int fixed_phy_aneg (struct uec_mii_info *mii_info)
653{
654 mii_info->autoneg = 0; /* Turn off auto negotiation for fixed phy */
655 return 0;
656}
657
658static int fixed_phy_read_status (struct uec_mii_info *mii_info)
659{
660 int i = 0;
661
662 for (i = 0; i < ARRAY_SIZE(fixed_phy_port); i++) {
1443cd7e
RR		 663 if (strncmp(mii_info->dev->name, fixed_phy_port[i].name,
664 strlen(mii_info->dev->name)) == 0) {
edf3fe7d
RR		 665 mii_info->speed = fixed_phy_port[i].speed;
666 mii_info->duplex = fixed_phy_port[i].duplex;
667 mii_info->link = 1; /* Link is always UP */
668 mii_info->pause = 0;
669 break;
670 }
671 }
672 return 0;
673}
674
8b69b563
HS		 675static int smsc_config_aneg (struct uec_mii_info *mii_info)
676{
677 return 0;
678}
679
680static int smsc_read_status (struct uec_mii_info *mii_info)
681{
682 u16 status;
683 int err;
684
685 /* Update the link, but return if there
686 * was an error */
687 err = genmii_update_link (mii_info);
688 if (err)
689 return err;
690
691 /* If the link is up, read the speed and duplex */
692 /* If we aren't autonegotiating, assume speeds
693 * are as set */
694 if (mii_info->autoneg && mii_info->link) {
695 int val;
696
09c04c20 697 status = uec_phy_read(mii_info, 0x1f);
8b69b563
HS		 698 val = (status & 0x1c) >> 2;
699
700 switch (val) {
701 case 1:
702 mii_info->duplex = DUPLEX_HALF;
703 mii_info->speed = SPEED_10;
704 break;
705 case 5:
706 mii_info->duplex = DUPLEX_FULL;
707 mii_info->speed = SPEED_10;
708 break;
709 case 2:
710 mii_info->duplex = DUPLEX_HALF;
711 mii_info->speed = SPEED_100;
712 break;
713 case 6:
714 mii_info->duplex = DUPLEX_FULL;
715 mii_info->speed = SPEED_100;
716 break;
717 }
718 mii_info->pause = 0;
719 }
720
721 return 0;
722}
723
7737d5c6 724static struct phy_info phy_info_dm9161 = {
dd520bf3
WD		 725 .phy_id = 0x0181b880,
726 .phy_id_mask = 0x0ffffff0,
727 .name = "Davicom DM9161E",
728 .init = dm9161_init,
729 .config_aneg = dm9161_config_aneg,
730 .read_status = dm9161_read_status,
731 .close = dm9161_close,
7737d5c6
DL		 732};
733
734static struct phy_info phy_info_dm9161a = {
dd520bf3
WD		 735 .phy_id = 0x0181b8a0,
736 .phy_id_mask = 0x0ffffff0,
737 .name = "Davicom DM9161A",
738 .features = MII_BASIC_FEATURES,
739 .init = dm9161_init,
740 .config_aneg = dm9161_config_aneg,
741 .read_status = dm9161_read_status,
742 .ack_interrupt = dm9161_ack_interrupt,
743 .config_intr = dm9161_config_intr,
744 .close = dm9161_close,
7737d5c6
DL		 745};
746
747static struct phy_info phy_info_marvell = {
dd520bf3
WD		 748 .phy_id = 0x01410c00,
749 .phy_id_mask = 0xffffff00,
750 .name = "Marvell 88E11x1",
751 .features = MII_GBIT_FEATURES,
09c04c20 752 .init = &uec_marvell_init,
dd520bf3
WD		 753 .config_aneg = &marvell_config_aneg,
754 .read_status = &marvell_read_status,
755 .ack_interrupt = &marvell_ack_interrupt,
756 .config_intr = &marvell_config_intr,
7737d5c6
DL		 757};
758
300615dc
AV		 759static struct phy_info phy_info_bcm5481 = {
760 .phy_id = 0x0143bca0,
761 .phy_id_mask = 0xffffff0,
762 .name = "Broadcom 5481",
763 .features = MII_GBIT_FEATURES,
764 .read_status = genmii_read_status,
765 .init = bcm_init,
766};
767
edf3fe7d
RR		 768static struct phy_info phy_info_fixedphy = {
769 .phy_id = CONFIG_FIXED_PHY,
770 .phy_id_mask = CONFIG_FIXED_PHY,
771 .name = "Fixed PHY",
772 .config_aneg = fixed_phy_aneg,
773 .read_status = fixed_phy_read_status,
774};
775
8b69b563
HS		 776static struct phy_info phy_info_smsclan8700 = {
777 .phy_id = 0x0007c0c0,
778 .phy_id_mask = 0xfffffff0,
779 .name = "SMSC LAN8700",
780 .features = MII_BASIC_FEATURES,
781 .config_aneg = smsc_config_aneg,
782 .read_status = smsc_read_status,
783};
784
dd520bf3
WD		 785static struct phy_info phy_info_genmii = {
786 .phy_id = 0x00000000,
787 .phy_id_mask = 0x00000000,
788 .name = "Generic MII",
789 .features = MII_BASIC_FEATURES,
790 .config_aneg = genmii_config_aneg,
791 .read_status = genmii_read_status,
7737d5c6
DL		 792};
793
794static struct phy_info *phy_info[] = {
dd520bf3
WD		 795 &phy_info_dm9161,
796 &phy_info_dm9161a,
797 &phy_info_marvell,
300615dc 798 &phy_info_bcm5481,
8b69b563 799 &phy_info_smsclan8700,
edf3fe7d 800 &phy_info_fixedphy,
dd520bf3
WD		 801 &phy_info_genmii,
802 NULL
7737d5c6
DL		 803};
804
09c04c20 805u16 uec_phy_read(struct uec_mii_info *mii_info, u16 regnum)
7737d5c6 806{
dd520bf3 807 return mii_info->mdio_read (mii_info->dev, mii_info->mii_id, regnum);
7737d5c6
DL		 808}
809
09c04c20 810void uec_phy_write(struct uec_mii_info *mii_info, u16 regnum, u16 val)
7737d5c6 811{
dd520bf3 812 mii_info->mdio_write (mii_info->dev, mii_info->mii_id, regnum, val);
7737d5c6
DL		 813}
814
815/* Use the PHY ID registers to determine what type of PHY is attached
816 * to device dev. return a struct phy_info structure describing that PHY
817 */
da9d4610 818struct phy_info *uec_get_phy_info (struct uec_mii_info *mii_info)
7737d5c6 819{
dd520bf3
WD		 820 u16 phy_reg;
821 u32 phy_ID;
822 int i;
823 struct phy_info *theInfo = NULL;
824
825 /* Grab the bits from PHYIR1, and put them in the upper half */
09c04c20 826 phy_reg = uec_phy_read(mii_info, MII_PHYSID1);
dd520bf3
WD		 827 phy_ID = (phy_reg & 0xffff) << 16;
828
829 /* Grab the bits from PHYIR2, and put them in the lower half */
09c04c20 830 phy_reg = uec_phy_read(mii_info, MII_PHYSID2);
dd520bf3
WD		 831 phy_ID |= (phy_reg & 0xffff);
832
833 /* loop through all the known PHY types, and find one that */
834 /* matches the ID we read from the PHY. */
835 for (i = 0; phy_info[i]; i++)
836 if (phy_info[i]->phy_id ==
837 (phy_ID & phy_info[i]->phy_id_mask)) {
838 theInfo = phy_info[i];
839 break;
840 }
841
842 /* This shouldn't happen, as we have generic PHY support */
843 if (theInfo == NULL) {
844 ugphy_info ("UEC: PHY id %x is not supported!", phy_ID);
845 return NULL;
846 } else {
847 ugphy_info ("UEC: PHY is %s (%x)", theInfo->name, phy_ID);
848 }
849
850 return theInfo;
7737d5c6
DL		 851}
852
865ff856
AF		 853void marvell_phy_interface_mode(struct eth_device *dev, phy_interface_t type,
854 int speed)
7737d5c6 855{
dd520bf3
WD		 856 uec_private_t *uec = (uec_private_t *) dev->priv;
857 struct uec_mii_info *mii_info;
f655adef 858 u16 status;
7737d5c6
DL		 859
860 if (!uec->mii_info) {
f30b6154 861 printf ("%s: the PHY not initialized\n", __FUNCTION__);
7737d5c6
DL		 862 return;
863 }
864 mii_info = uec->mii_info;
865
865ff856
AF		 866 if (type == PHY_INTERFACE_MODE_RGMII) {
867 if (speed == SPEED_100) {
09c04c20
AF		 868 uec_phy_write(mii_info, 0x00, 0x9140);
869 uec_phy_write(mii_info, 0x1d, 0x001f);
870 uec_phy_write(mii_info, 0x1e, 0x200c);
871 uec_phy_write(mii_info, 0x1d, 0x0005);
872 uec_phy_write(mii_info, 0x1e, 0x0000);
873 uec_phy_write(mii_info, 0x1e, 0x0100);
874 uec_phy_write(mii_info, 0x09, 0x0e00);
875 uec_phy_write(mii_info, 0x04, 0x01e1);
876 uec_phy_write(mii_info, 0x00, 0x9140);
877 uec_phy_write(mii_info, 0x00, 0x1000);
582c55a0 878 udelay (100000);
09c04c20
AF		 879 uec_phy_write(mii_info, 0x00, 0x2900);
880 uec_phy_write(mii_info, 0x14, 0x0cd2);
881 uec_phy_write(mii_info, 0x00, 0xa100);
882 uec_phy_write(mii_info, 0x09, 0x0000);
883 uec_phy_write(mii_info, 0x1b, 0x800b);
884 uec_phy_write(mii_info, 0x04, 0x05e1);
885 uec_phy_write(mii_info, 0x00, 0xa100);
886 uec_phy_write(mii_info, 0x00, 0x2100);
582c55a0 887 udelay (1000000);
865ff856 888 } else if (speed == SPEED_10) {
09c04c20
AF		 889 uec_phy_write(mii_info, 0x14, 0x8e40);
890 uec_phy_write(mii_info, 0x1b, 0x800b);
891 uec_phy_write(mii_info, 0x14, 0x0c82);
892 uec_phy_write(mii_info, 0x00, 0x8100);
582c55a0
HS		 893 udelay (1000000);
894 }
7737d5c6 895 }
f655adef
KP		 896
897 /* handle 88e1111 rev.B2 erratum 5.6 */
898 if (mii_info->autoneg) {
09c04c20
AF		 899 status = uec_phy_read(mii_info, MII_BMCR);
900 uec_phy_write(mii_info, MII_BMCR, status | BMCR_ANENABLE);
f655adef
KP		 901 }
902 /* now the B2 will correctly report autoneg completion status */
7737d5c6
DL		 903}
904
582c55a0 905void change_phy_interface_mode (struct eth_device *dev,
865ff856 906 phy_interface_t type, int speed)
7737d5c6
DL		 907{
908#ifdef CONFIG_PHY_MODE_NEED_CHANGE
582c55a0 909 marvell_phy_interface_mode (dev, type, speed);
7737d5c6
DL		 910#endif
911}
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