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83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
37a0c600 AF |
2 | /* |
3 | * Copyright (c) 2016 Andreas Färber | |
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4 | */ |
5 | ||
6 | #ifndef __CONFIG_RK3368_COMMON_H | |
7 | #define __CONFIG_RK3368_COMMON_H | |
8 | ||
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9 | #include "rockchip-common.h" |
10 | ||
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11 | #define CONFIG_SYS_CACHELINE_SIZE 64 |
12 | ||
15f09a1a | 13 | #include <asm/arch-rockchip/hardware.h> |
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14 | #include <linux/sizes.h> |
15 | ||
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16 | #define CONFIG_SYS_SDRAM_BASE 0 |
17 | #define SDRAM_MAX_SIZE 0xff000000 | |
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18 | #define CONFIG_SYS_CBSIZE 1024 |
19 | #define CONFIG_SKIP_LOWLEVEL_INIT | |
20 | ||
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21 | #define CONFIG_ROCKCHIP_STIMER_BASE 0xff830020 |
22 | #define COUNTER_FREQUENCY 24000000 | |
e78b04f9 | 23 | |
5f246808 KY |
24 | #define CONFIG_IRAM_BASE 0xff8c0000 |
25 | ||
37a0c600 | 26 | #define CONFIG_SYS_INIT_SP_ADDR 0x00300000 |
37a0c600 | 27 | |
6024467b | 28 | #define CONFIG_SPL_MAX_SIZE 0x40000 |
c61177aa PT |
29 | #define CONFIG_SPL_BSS_START_ADDR 0x400000 |
30 | #define CONFIG_SPL_BSS_MAX_SIZE 0x20000 | |
cd193462 | 31 | #define CONFIG_SPL_STACK 0x00188000 |
c61177aa | 32 | |
e436c499 HS |
33 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ |
34 | ||
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35 | #ifndef CONFIG_SPL_BUILD |
36 | #define ENV_MEM_LAYOUT_SETTINGS \ | |
37 | "scriptaddr=0x00500000\0" \ | |
38 | "pxefile_addr_r=0x00600000\0" \ | |
39 | "fdt_addr_r=0x5600000\0" \ | |
40 | "kernel_addr_r=0x280000\0" \ | |
41 | "ramdisk_addr_r=0x5bf0000\0" | |
42 | ||
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43 | #include <config_distro_bootcmd.h> |
44 | ||
45 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
a2a5053a | 46 | "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ |
ffaefb88 | 47 | ENV_MEM_LAYOUT_SETTINGS \ |
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48 | BOOTENV |
49 | ||
50 | #endif | |
51 | ||
52 | #endif |