[u-boot.git] / arch / arm / dts / mt7623.dtsi

/*
 * Copyright (C) 2018 MediaTek Inc.
 * Author: Ryder Lee <[email protected]>
 *
 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
 */

#include <dt-bindings/clock/mt7623-clk.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/mt7623-power.h>
#include <dt-bindings/reset/mtk-reset.h>
#include "skeleton.dtsi"

/ {
	compatible = "mediatek,mt7623";
	interrupt-parent = <&sysirq>;
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "mediatek,mt6589-smp";

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x0>;
			clocks = <&infracfg CLK_INFRA_CPUSEL>,
				 <&apmixedsys CLK_APMIXED_MAINPLL>;
			clock-names = "cpu", "intermediate";
			clock-frequency = <1300000000>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x1>;
			clocks = <&infracfg CLK_INFRA_CPUSEL>,
				 <&apmixedsys CLK_APMIXED_MAINPLL>;
			clock-names = "cpu", "intermediate";
			clock-frequency = <1300000000>;
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x2>;
			clocks = <&infracfg CLK_INFRA_CPUSEL>,
				 <&apmixedsys CLK_APMIXED_MAINPLL>;
			clock-names = "cpu", "intermediate";
			clock-frequency = <1300000000>;
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x3>;
			clocks = <&infracfg CLK_INFRA_CPUSEL>,
				 <&apmixedsys CLK_APMIXED_MAINPLL>;
			clock-names = "cpu", "intermediate";
			clock-frequency = <1300000000>;
		};
	};

	system_clk: dummy13m {
		compatible = "fixed-clock";
		clock-frequency = <13000000>;
		#clock-cells = <0>;
	};

	rtc32k: oscillator-1 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <32000>;
		clock-output-names = "rtc32k";
	};

	clk26m: oscillator-0 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <26000000>;
		clock-output-names = "clk26m";
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
		clock-frequency = <13000000>;
		arm,cpu-registers-not-fw-configured;
	};

	topckgen: clock-controller@10000000 {
		compatible = "mediatek,mt7623-topckgen";
		reg = <0x10000000 0x1000>;
		#clock-cells = <1>;
		u-boot,dm-pre-reloc;
	};

	infracfg: syscon@10001000 {
		compatible = "mediatek,mt7623-infracfg", "syscon";
		reg = <0x10001000 0x1000>;
		#clock-cells = <1>;
		u-boot,dm-pre-reloc;
	};

	pericfg: syscon@10003000 {
		compatible = "mediatek,mt7623-pericfg", "syscon";
		reg = <0x10003000 0x1000>;
		#clock-cells = <1>;
		u-boot,dm-pre-reloc;
	};

	pinctrl: pinctrl@10005000 {
		compatible = "mediatek,mt7623-pinctrl";
		reg = <0x10005000 0x1000>;

		gpio: gpio-controller {
			gpio-controller;
			#gpio-cells = <2>;
		};
	};

	scpsys: scpsys@10006000 {
		compatible = "mediatek,mt7623-scpsys";
		#power-domain-cells = <1>;
		reg = <0x10006000 0x1000>;
		infracfg = <&infracfg>;
		clocks = <&topckgen CLK_TOP_MM_SEL>,
			 <&topckgen CLK_TOP_MFG_SEL>,
			 <&topckgen CLK_TOP_ETHIF_SEL>;
		clock-names = "mm", "mfg", "ethif";
	};

	watchdog: watchdog@10007000 {
		compatible = "mediatek,wdt";
		reg = <0x10007000 0x100>;
	};

	wdt-reboot {
		compatible = "wdt-reboot";
		wdt = <&watchdog>;
	};

	timer0: timer@10008000 {
		compatible = "mediatek,timer";
		reg = <0x10008000 0x80>;
		interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&system_clk>;
		clock-names = "system-clk";
		u-boot,dm-pre-reloc;
	};

	sysirq: interrupt-controller@10200100 {
		compatible = "mediatek,sysirq";
		interrupt-controller;
		#interrupt-cells = <3>;
		interrupt-parent = <&gic>;
		reg = <0x10200100 0x1c>;
	};

	apmixedsys: clock-controller@10209000 {
		compatible = "mediatek,mt7623-apmixedsys";
		reg = <0x10209000 0x1000>;
		#clock-cells = <1>;
		u-boot,dm-pre-reloc;
	};

	gic: interrupt-controller@10211000 {
		compatible = "arm,cortex-a7-gic";
		interrupt-controller;
		#interrupt-cells = <3>;
		interrupt-parent = <&gic>;
		reg = <0x10211000 0x1000>,
		      <0x10212000 0x1000>,
		      <0x10214000 0x2000>,
		      <0x10216000 0x2000>;
	};

	uart0: serial@11002000 {
		compatible = "mediatek,hsuart";
		reg = <0x11002000 0x400>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&topckgen CLK_TOP_UART_SEL>,
			 <&pericfg CLK_PERI_UART0>;
		clock-names = "baud", "bus";
		status = "disabled";
	};

	uart1: serial@11003000 {
		compatible = "mediatek,hsuart";
		reg = <0x11003000 0x400>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&topckgen CLK_TOP_UART_SEL>,
			 <&pericfg CLK_PERI_UART1>;
		clock-names = "baud", "bus";
		status = "disabled";
	};

	uart2: serial@11004000 {
		compatible = "mediatek,hsuart";
		reg = <0x11004000 0x400>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&topckgen CLK_TOP_UART_SEL>,
			 <&pericfg CLK_PERI_UART2>;
		clock-names = "baud", "bus";
		status = "disabled";
		u-boot,dm-pre-reloc;
	};

	uart3: serial@11005000 {
		compatible = "mediatek,hsuart";
		reg = <0x11005000 0x400>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&topckgen CLK_TOP_UART_SEL>,
			 <&pericfg CLK_PERI_UART3>;
		clock-names = "baud", "bus";
		status = "disabled";
	};

	mmc0: mmc@11230000 {
		compatible = "mediatek,mt7623-mmc";
		reg = <0x11230000 0x1000>;
		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pericfg CLK_PERI_MSDC30_0>,
			 <&topckgen CLK_TOP_MSDC30_0_SEL>;
		clock-names = "source", "hclk";
		status = "disabled";
	};

	mmc1: mmc@11240000 {
		compatible = "mediatek,mt7623-mmc";
		reg = <0x11240000 0x1000>;
		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pericfg CLK_PERI_MSDC30_1>,
			 <&topckgen CLK_TOP_MSDC30_1_SEL>;
		clock-names = "source", "hclk";
		status = "disabled";
	};

	ethsys: syscon@1b000000 {
		compatible = "mediatek,mt7623-ethsys", "syscon";
		reg = <0x1b000000 0x1000>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	eth: ethernet@1b100000 {
		compatible = "mediatek,mt7623-eth", "syscon";
		reg = <0x1b100000 0x20000>;
		clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
			 <&ethsys CLK_ETHSYS_ESW>,
			 <&ethsys CLK_ETHSYS_GP1>,
			 <&ethsys CLK_ETHSYS_GP2>,
			 <&apmixedsys CLK_APMIXED_TRGPLL>;
		clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
		power-domains = <&scpsys MT7623_POWER_DOMAIN_ETH>;
		resets = <&ethsys ETHSYS_FE_RST>,
			 <&ethsys ETHSYS_MCM_RST>;
		reset-names = "fe", "mcm";
		mediatek,ethsys = <&ethsys>;
		status = "disabled";
	};
};
Commit	Line	Data
d84982db RL	1	/*
	2	* Copyright (C) 2018 MediaTek Inc.
	3	* Author: Ryder Lee <[email protected]>
	4	*
	5	* SPDX-License-Identifier: (GPL-2.0 OR MIT)
	6	*/
	7
	8	#include <dt-bindings/clock/mt7623-clk.h>
	9	#include <dt-bindings/gpio/gpio.h>
	10	#include <dt-bindings/interrupt-controller/irq.h>
	11	#include <dt-bindings/interrupt-controller/arm-gic.h>
	12	#include <dt-bindings/power/mt7623-power.h>
d9506a6f	13	#include <dt-bindings/reset/mtk-reset.h>
d84982db RL	14	#include "skeleton.dtsi"
	15
	16	/ {
	17	compatible = "mediatek,mt7623";
	18	interrupt-parent = <&sysirq>;
	19	#address-cells = <1>;
	20	#size-cells = <1>;
	21
	22	cpus {
	23	#address-cells = <1>;
	24	#size-cells = <0>;
	25	enable-method = "mediatek,mt6589-smp";
	26
	27	cpu0: cpu@0 {
	28	device_type = "cpu";
	29	compatible = "arm,cortex-a7";
	30	reg = <0x0>;
	31	clocks = <&infracfg CLK_INFRA_CPUSEL>,
	32	<&apmixedsys CLK_APMIXED_MAINPLL>;
	33	clock-names = "cpu", "intermediate";
	34	clock-frequency = <1300000000>;
	35	};
	36
	37	cpu1: cpu@1 {
	38	device_type = "cpu";
	39	compatible = "arm,cortex-a7";
	40	reg = <0x1>;
	41	clocks = <&infracfg CLK_INFRA_CPUSEL>,
	42	<&apmixedsys CLK_APMIXED_MAINPLL>;
	43	clock-names = "cpu", "intermediate";
	44	clock-frequency = <1300000000>;
	45	};
	46
	47	cpu2: cpu@2 {
	48	device_type = "cpu";
	49	compatible = "arm,cortex-a7";
	50	reg = <0x2>;
	51	clocks = <&infracfg CLK_INFRA_CPUSEL>,
	52	<&apmixedsys CLK_APMIXED_MAINPLL>;
	53	clock-names = "cpu", "intermediate";
	54	clock-frequency = <1300000000>;
	55	};
	56
	57	cpu3: cpu@3 {
	58	device_type = "cpu";
	59	compatible = "arm,cortex-a7";
	60	reg = <0x3>;
	61	clocks = <&infracfg CLK_INFRA_CPUSEL>,
	62	<&apmixedsys CLK_APMIXED_MAINPLL>;
	63	clock-names = "cpu", "intermediate";
	64	clock-frequency = <1300000000>;
	65	};
	66	};
	67
	68	system_clk: dummy13m {
	69	compatible = "fixed-clock";
	70	clock-frequency = <13000000>;
	71	#clock-cells = <0>;
	72	};
	73
	74	rtc32k: oscillator-1 {
	75	compatible = "fixed-clock";
	76	#clock-cells = <0>;
	77	clock-frequency = <32000>;
78	clock-output-names = "rtc32k";
79	};
80
81	clk26m: oscillator-0 {
82	compatible = "fixed-clock";
83	#clock-cells = <0>;
84	clock-frequency = <26000000>;
85	clock-output-names = "clk26m";
86	};
87
88	timer {
89	compatible = "arm,armv7-timer";
90	interrupt-parent = <&gic>;
91	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
92	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
93	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
94	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
95	clock-frequency = <13000000>;
96	arm,cpu-registers-not-fw-configured;
97	};
98
99	topckgen: clock-controller@10000000 {
100	compatible = "mediatek,mt7623-topckgen";
101	reg = <0x10000000 0x1000>;
102	#clock-cells = <1>;
103	u-boot,dm-pre-reloc;
104	};
105
106	infracfg: syscon@10001000 {
107	compatible = "mediatek,mt7623-infracfg", "syscon";
108	reg = <0x10001000 0x1000>;
109	#clock-cells = <1>;
110	u-boot,dm-pre-reloc;
111	};
112
113	pericfg: syscon@10003000 {
114	compatible = "mediatek,mt7623-pericfg", "syscon";
115	reg = <0x10003000 0x1000>;
116	#clock-cells = <1>;
117	u-boot,dm-pre-reloc;
118	};
119
120	pinctrl: pinctrl@10005000 {
121	compatible = "mediatek,mt7623-pinctrl";
122	reg = <0x10005000 0x1000>;
123
124	gpio: gpio-controller {
125	gpio-controller;
126	#gpio-cells = <2>;
127	};
128	};
129
130	scpsys: scpsys@10006000 {
131	compatible = "mediatek,mt7623-scpsys";
132	#power-domain-cells = <1>;
133	reg = <0x10006000 0x1000>;
134	infracfg = <&infracfg>;
135	clocks = <&topckgen CLK_TOP_MM_SEL>,
136	<&topckgen CLK_TOP_MFG_SEL>,
137	<&topckgen CLK_TOP_ETHIF_SEL>;
138	clock-names = "mm", "mfg", "ethif";
139	};
140
141	watchdog: watchdog@10007000 {
142	compatible = "mediatek,wdt";
143	reg = <0x10007000 0x100>;
144	};
145
146	wdt-reboot {
147	compatible = "wdt-reboot";
148	wdt = <&watchdog>;
149	};
150
151	timer0: timer@10008000 {
152	compatible = "mediatek,timer";
153	reg = <0x10008000 0x80>;
154	interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
155	clocks = <&system_clk>;
156	clock-names = "system-clk";
157	u-boot,dm-pre-reloc;
158	};
159
160	sysirq: interrupt-controller@10200100 {
161	compatible = "mediatek,sysirq";
162	interrupt-controller;
163	#interrupt-cells = <3>;
164	interrupt-parent = <&gic>;
165	reg = <0x10200100 0x1c>;
166	};
167
168	apmixedsys: clock-controller@10209000 {
169	compatible = "mediatek,mt7623-apmixedsys";
170	reg = <0x10209000 0x1000>;
171	#clock-cells = <1>;
172	u-boot,dm-pre-reloc;
173	};
174
175	gic: interrupt-controller@10211000 {
176	compatible = "arm,cortex-a7-gic";
177	interrupt-controller;
178	#interrupt-cells = <3>;
179	interrupt-parent = <&gic>;
180	reg = <0x10211000 0x1000>,
181	<0x10212000 0x1000>,
182	<0x10214000 0x2000>,
183	<0x10216000 0x2000>;
184	};
185
186	uart0: serial@11002000 {
187	compatible = "mediatek,hsuart";
188	reg = <0x11002000 0x400>;
189	reg-shift = <2>;
190	interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
191	clocks = <&topckgen CLK_TOP_UART_SEL>,
192	<&pericfg CLK_PERI_UART0>;
193	clock-names = "baud", "bus";
194	status = "disabled";
195	};
196
197	uart1: serial@11003000 {
198	compatible = "mediatek,hsuart";
199	reg = <0x11003000 0x400>;
200	reg-shift = <2>;
201	interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
202	clocks = <&topckgen CLK_TOP_UART_SEL>,
203	<&pericfg CLK_PERI_UART1>;
204	clock-names = "baud", "bus";
205	status = "disabled";
206	};
207
208	uart2: serial@11004000 {
209	compatible = "mediatek,hsuart";
210	reg = <0x11004000 0x400>;
211	reg-shift = <2>;
212	interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
213	clocks = <&topckgen CLK_TOP_UART_SEL>,
214	<&pericfg CLK_PERI_UART2>;
215	clock-names = "baud", "bus";
216	status = "disabled";
217	u-boot,dm-pre-reloc;
218	};
219
220	uart3: serial@11005000 {
221	compatible = "mediatek,hsuart";
222	reg = <0x11005000 0x400>;
223	reg-shift = <2>;
224	interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
225	clocks = <&topckgen CLK_TOP_UART_SEL>,
226	<&pericfg CLK_PERI_UART3>;
227	clock-names = "baud", "bus";
228	status = "disabled";
229	};
230
231	mmc0: mmc@11230000 {
232	compatible = "mediatek,mt7623-mmc";
233	reg = <0x11230000 0x1000>;
234	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
235	clocks = <&pericfg CLK_PERI_MSDC30_0>,
236	<&topckgen CLK_TOP_MSDC30_0_SEL>;
237	clock-names = "source", "hclk";
238	status = "disabled";
239	};
240
241	mmc1: mmc@11240000 {
242	compatible = "mediatek,mt7623-mmc";
243	reg = <0x11240000 0x1000>;
244	interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_LOW>;
245	clocks = <&pericfg CLK_PERI_MSDC30_1>,
246	<&topckgen CLK_TOP_MSDC30_1_SEL>;
247	clock-names = "source", "hclk";
248	status = "disabled";
249	};
250
251	ethsys: syscon@1b000000 {
d9506a6f	252	compatible = "mediatek,mt7623-ethsys", "syscon";
d84982db RL	253	reg = <0x1b000000 0x1000>;
d84982db RL	254	#clock-cells = <1>;
d9506a6f WG	255	#reset-cells = <1>;
	256	};
	257
	258	eth: ethernet@1b100000 {
	259	compatible = "mediatek,mt7623-eth", "syscon";
	260	reg = <0x1b100000 0x20000>;
	261	clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
	262	<&ethsys CLK_ETHSYS_ESW>,
	263	<&ethsys CLK_ETHSYS_GP1>,
	264	<&ethsys CLK_ETHSYS_GP2>,
	265	<&apmixedsys CLK_APMIXED_TRGPLL>;
	266	clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
	267	power-domains = <&scpsys MT7623_POWER_DOMAIN_ETH>;
	268	resets = <&ethsys ETHSYS_FE_RST>,
	269	<&ethsys ETHSYS_MCM_RST>;
	270	reset-names = "fe", "mcm";
	271	mediatek,ethsys = <&ethsys>;
	272	status = "disabled";
d84982db RL	273	};
d84982db RL	274	};